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`APPLICATION ELEMENTS
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`1083973
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`60601
`312-609-500
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`0003
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`SUBTOTAL (2)
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`niaina fPn7'iO‘Type}
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`Christopher J. Reckamp
`
`_
`
`34_414
`
`Teieprtane 312-609-7598
`
`WARNING: informa -" on this fonn may been . public. Credit oard inforination should not
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`" 954914
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicants: Leather et al.
`
`Serial No.:
`
`Examiner:
`
`Art Group:
`
`Filing Date: June 12, 2003
`
`Docket No: 00100.02.00S3
`
`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING A
`
`SUPER-TILING TECHNIQUE
`
`Mail Stop Patent Application
`Commissioner for patents
`13.0. Box I 450
`.
`memaml va zzmso
`
`Cernfieale ofExpress Man‘
`I hereby certify that this paper is being deposited with the
`United States Pas-:a!.‘1‘ervice “Express Mail Post agree to
`Addressee” service under 37 CFR (.10, on the data
`indicated and is addressed to Mail Stop Patent
`A
`I"
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`.03" I450.
`,::;;:::?:V:*;;;:;::::'J°*
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`Express Mai! No. E V 0633 M627 US.
`a
`1
`It
`Do is
`Winona K. JECJUIJ-II
`
`PRELIMINARY AMENDMENT
`
`Dear Sir:
`
`Prior to examination, Applicants respectfully request that the above-identified application
`
`be amended as follows:
`
`In The Specification:
`
`Please add the following new paragraph directly below the invention title on page 1 of
`
`the specification as follows:
`
`This application claims the benefit of U. S. Provisional Application Ser. No. 60/429,641
`
`filed November 27, 2002, entitled “Dividing Work Among Multiple Graphics Pipelines Using a
`
`Super-Tiling Technique", having as inventors Mark M. Leather and Eric Demers, and owned by
`
`instant assignee.
`
`CHIC AGO!!! 1083968.]
`
`0005
`
`

`
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`REMARKS
`
`Applicants submit that the specification is fully supported by the original provisional
`
`application, and the claims are fully supported by the originally filed provisional application.
`
`Respectfully submitted,
`
`By: 4 4
`Chris opher J. Rcckamp
`Reg. No. 34,414
`
`Dated: June 12, 2003
`
`Vedder, Price, Kaufman & Kammholz
`222 North Lasalle Street
`Chicago, Illinois 60601
`Telephone: (312) 609-7500
`Facsimile: (312) 609-5005
`
`CHICAGOM I 083958. I
`
`0006
`
`

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`Li.
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`9
`
`§"i '3’
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`
`020053
`
`PATENT APPLICATION
`ATTY. DOCKET NO. 00100.02.0053
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`FILING OF A UNITED STATES PATENT APPLICATION
`
`DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES
`USING A SUPER-TILING TECHNIQUE
`
`INVENTORS:
`
`Mark M. Leather
`12187 Woodside Drive
`
`Saratoga, California 95070
`
`Eric Demers
`
`901 Sycamore Drive
`Palo Alto, California 94303
`
`ATTORNEY OF RECORD:
`CHRISTOPHER J. RECKAMP
`
`REGISTRATION NO. 34,414
`VEDDER PRICE KAUFMAN & KAMMHOLZ
`222 NORTH LASALLE STREE'I', SUITE 2600
`CHICAGO, ILLINOIS 60601
`PHONE (312) 509-7500
`FAX (312)609-5005
`
`Express Mail Label No.: EV 063310627 US
`Date of Deposit: J une 12, 2003
`
`I hereby certify that this paper is being deposited with the
`U.S. Postal Service “Express Mail Post Office to
`Addressee" service under 37 C.F.R. Section l.l0 on the
`‘Date of Deposit‘, indicated above, and is addressed
`to: Mail Stop Patent Application, Commissioner of Parents,
`P. 0. Box 1450, Alexandria, VA, 22313-1450.
`
`Name of Depositor: Winona K. Jackson
`
`0007
`
`

`
`.1
`
`'i~5i:3l§ _'.I‘-'-”’ 3-" ...
`
`(:51!
`
`020053
`
`DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING A
`
`SUPER-TILING TECHNIQUE
`
`RELATED CO—PENDING APPLICATION
`
`[0001]
`
`This is a related application to a co-pending application entitled “Parallel
`
`Pipeline Graphics System” having docket number 010025, having serial number
`
`, having Leather et al. as the inventors, filed on even date,
`
`owned by the same assignee and hereby incorporated by reference in its entirety.
`
`FIELD OF THE INVENTION
`
`[0001]
`
`The present invention generally relates to graphics processing circuitry
`
`and, more particularly, to dividing graphics processing operations among multiple
`
`pipelines.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`Computer graphics systems, set top box systems or other graphics
`
`processing systems typically include a host processor, graphics (including video)
`
`processing circuitry, memory (e.g. frame buffer), and one or more display devices. The
`
`host processor may have a graphics application running thereon, which provides vertex
`
`data for a primitive (e.g. triangle) to be rendered on the one or more display devices to
`
`the graphics processing circuitry. The display device, for example, a CRT display
`
`includes a plurality of scan lines comprised of a series of pixels. When appearance
`
`attributes (e.g. color, brightness, texture) are applied to the pixels, an object or scene is
`
`presented on the display device. The graphics processing circuitry receives the vertex
`
`data and generates pixel data including the appearance attributes which may be presented
`
`on the display device according to a particular protocol. The pixel data is typically
`stored in the frame buffer in a manner that corresponds to the pixels location on the
`
`display device.
`
`[0003]
`
`FIG. 1 illustrates a conventional display device 10, having a screen 12
`
`partitioned into a series of vertical strips 13-18. The strips 13-13 are typically I-4 pixels
`
`in width. In like manner, the frame buffer of conventional graphics processing systems is
`
`partitioned into a series of vertical strips having the same screen space width.
`
`1
`
`0008
`
`

`
`020053
`
`Alternatively, the frame buffer and the display device may be partitioned into a series of
`
`horizontal strips. Graphics calculations, for example, lighting, color, texture and user
`
`viewing information are performed by the graphics processing circuitry on each of the
`
`primitives provided by the host. Once all calculations have been performed on the
`
`primitives, the pixel data representing the object to be displayed is written into the frame
`
`buffer. Once the graphics calculations have been repeated for all primitives associated
`
`with a specific frame, the data stored in the frame buffer is rendered to create a video
`
`signal that is provided to the display device.
`
`[0004]
`
`The amount of time taken for an entire frame of infonnation to be
`
`calculated and provided to the frame buffer becomes a bottleneck in graphics systems as
`
`the calculations associated with the graphics become more complicated. Contributing to
`
`the increased complexity of the graphics calculation is the increased need for higher
`
`resolution video, as well as the need for more complicated video, such as 3-D video. The
`
`video image observed by the human eye becomes distorted or choppy when the amount
`
`of time taken to render an entire frame of video exceeds the amount of time in which the
`
`display device must be refreshed with a new graphic or frame in order to avoid
`
`perception by the human eye. To decrease processing time, graphics processing systems
`
`typically divide primitive processing among several graphics processing circuits where,
`
`for example, one graphics processing circuit is responsible for one vertical strip (eg. 13)
`
`of the frame while another graphics processing circuit is responsible for another vertical
`
`strip (e. g. 14) of the frame. In this manner, the pixel data is provided to the frame buffer
`
`within the required refresh time.
`
`[0005]
`
`Load balancing is a significant drawback associated with the partitioning
`
`systems as described above. Load balancing problems occur, for example. when all of
`
`the primitives 20-23 of a particular objector scene are located in one strip (e.g. strip 13)
`
`as illustrated in FIG. 1. When this occurs, only the graphics processing circuit
`
`responsible strip 13 is actively processing primitives; the remaining graphics processing
`
`circuits are idle. This results in a significant waste of computing resources as at most
`
`only half of the graphics processing circuits are operating. Consequently, graphics
`
`processing system performance is decreased as the system is only operating at a
`
`maximum of fifty percent capacity.
`
`0009
`
`

`
`020053
`
`[0006]
`
`Changing the width of the strips has been employed to counter the system
`
`performance problems. However, when the width of a strip is increased, the load
`
`balancing problem is enhanced as more primitives are located within a single strip;
`
`thereby, increasing the processing required of the graphics processing circuit responsible
`
`for that strip, while the remaining graphics processing circuits remain idle. When the
`
`width of the strip is decreased (e.g. four hits to two bits), cache (e.g. texture cache)
`
`efficiency is decreased as the number of cache lines employed in transferring data is
`
`reduced in proportion to the decreased width of the strip. In either case, graphics
`
`processing system perfonnance is still decreased due to the idle graphics processing
`
`circuits.
`
`[0007]
`
`Frame based subdivision has been used to overcome the performance
`
`problems associated with conventional partitioning systems. In fi-ame based subdivision,
`
`each graphics processor is responsible for processing an entire frame, not strips within the
`
`same frame. The graphics processors then alternate frames. However, frame subdivision
`
`introduces one or more frames of latency between the user and the screen, which is
`
`unacceptable in real-time interactive environments, for example, providing graphics for a
`
`flight simulator application.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0008]
`
`The present invention and the related advantages and benefits provided
`
`thereby, will be best appreciated and understood upon review of the following detailed
`
`description of a preferred embodiment, taken in conjunction with the following drawings,
`
`where like numerals represent like elements, in which:
`
`[0009]
`
`FIG. 1 is a schematic block diagram of a conventional display partitioned
`
`into several vertical strips:
`
`[0010]
`
`FIG. 2 is a schematic block diagram of a graphics processing system
`
`employing an exemplary multi-pipeline graphics processing circuit according to one
`
`embodiment of the present invention;
`
`[0011]
`
`FIG. 3 is a schematic block diagram of a memory partitioned into an
`
`exemplary super-tile pattern according to the present invention;
`
`0010
`
`

`
`[(1012]
`
`FIG. 4 is a schematic block diagram of a memory partitioned into a super-
`
`tile pattern according to an altemate embodiment of the present invention;
`
`[0013]
`
`FIG. 5 is a schematic block diagram of a.n exemplary multi—pipelinc
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`graphics processing circuit used in a multi processor configuration according to an
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`alternate embodiment of the present invention;
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`[0014]
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`FIG. 6 is a flow chart of the operations performed by the graphics
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`processing circuit according to the present invention;
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`[0015]
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`FIG. 7 is a diagram illustrating a polygon bounding box to determine
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`which, if a polygon fits in a tile or super tile; and
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`[0016]
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`FIG. 8 is a schematic block diagram of an exemplary rnulti—pipeline
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`graphics processing circuit used in a multi processor configuration according to an
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`alternate embodiment of the present invention.
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`0011
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`

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`DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
`
`[0017]
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`A multi-pipeline graphics processing circuit includes at least two pipelines
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`operative to process data in a corresponding tile of a repeating tile pattern, a respective
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`one of the at least two pipelines is operative to process data in a dedicated tile, wherein
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`the repeating tile pattern includes a horizontally and vertically repeating pattern of square
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`regions. The multi-pipeline graphics processing circuit may be coupled to a fiarne bufier
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`that is subdivided into a replicating pattern of square regions (e.g. tiles), where each
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`region is processed by a corresponding one of the at least two pipelines such that load
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`balancing and texture cache utilization is enhanced.
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`[0018]
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`A multi-pipeline graphics processing method includes receiving vertex
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`data for a primitive to be rendered, generating pixel data in response to the vertex data,
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`detennining the pixels within a set of tiles of a repeating tile pattern to be processed by a
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`corresponding one of at least two graphics pipelines in response to the pixel data, the
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`repeating tile pattem including a horizontally and vertically repeating pattern of square
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`regions, and performing pixel operations on the pixels within the determined set of tiles
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`by the corresponding one of the at least two graphics pipelines. An exemplary
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`embodiment of the present invention will now be described with reference to Figures 2-6.
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`[0019]
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`FIG. 2 is a schematic block diagram of an exemplary graphics processing
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`system 30 employing an example of a multi-pipeline graphics processing circuit 34
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`according to one embodiment of the present invention. The graphics processing system
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`30 can be implemented with a single graphics processing circuit 34 or with two or more
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`graphics processing circuits 34, 54. The components and corresponding functionality of
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`the graphics processing circuits 34, 54 are substantially the same. Therefore, only the
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`structure and operation of graphics processing circuit 34 will be described in detail. An
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`alternate embodiment, employing both graphics processing circuits 34 and 54 will be
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`discussed in greater detail below with reference to FIGS. 4-5.
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`[0020]
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`Graphics data 31, for example, vertex data of a primitive (e.g. triangle) 80
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`(FIG. 3) is transmitted as a series of strips to the graphics processing circuit 34. As used
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`herein, graphics data 31 can also include video data or a combination of video data and
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`graphics data. The graphics processing circuit 34 is preferably a portion of a stand-alone
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`graphics processor chip or may also be integrated with a host processor or other circuit, if
`
`0012
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`

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`"1! "El"? mg"
`T! ‘:35.
`P.‘ um! um! 2-13.! Emu than Rial“
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`020053
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`desired, or part of a larger system. The graphics data 31 is provided by a host (not
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`shown). The host may be a system processor (not shown) or a graphics application
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`running on the system processor.
`In an alternate embodiment, an Accelerated Graphics
`Port (AGP) 32 or other suitable port receives the graphics data 31 from thelhost and
`provides the graphics data 3] to the graphics processing circuit 34 for further processing.
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`[0021]
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`The graphics processing circuit 34 includes a first graphics pipeline 101
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`operative to process graphics data in a first set of tiles as discussed in greater detail
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`below. The first pipeline 101 includes front end circuitry 35, a scan converter 3?, and
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`back end circuitry 39. The graphics processing circuit 34 also includes a second graphics
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`pipeline 102, operative to process graphics data in a second set of tiles as discussed in
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`greater detail below. The first graphics pipeline 101 and the second graphics pipeline
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`102 operate independently of one another. The second graphics pipeline 102 includes the
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`fiont end circuitry 35, a scan converter 40, and back end circuitry 42. Thus, the graphics
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`processing circuit 34 of the present invention is contigured as a multi-pipeline circuit,
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`where the back end circuitry 39 of the first graphics pipeline 101 and the back end
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`circuitry 42 of the second graphics pipeline 102 share the front end circuitry 35, in that
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`the first and second graphics pipelines 101 and 102 receive the same pixel data 36
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`provided by the front end circuitry 35. Alternatively, the back end circuitry 39 of the first
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`graphics pipeline 101 and the back end circuitry 42 of the second pipeline 102 may be
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`coupled to separate front end circuits. Additionally, it will be appreciated that a single
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`graphics processing circuit can be configured in similar fashion to include more than two
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`graphics pipelines. The illustrated graphics processing circuit 34 has the first andisecond
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`pipelines 101-102 present on the same chip. However, in alternate embodiments, the first
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`and second graphics pipelines 101-102 may be present on multiple chips interconnected
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`by suitable communication circuitry or a communication path, for example, a
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`synchronization signal or data bus interconnecting the respective memory controllers.
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`|0022|
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`The front end circuitry 35 may include, for example, a vertex shader, set
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`up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data 31
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`and generate pixel data 36 to be further processed by the back end circuitry 39 and 42,
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`respectively. The front end circuitry 35 generates the pixel data 36 by performing, for
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`example, clipping, lighting, spatial transformations, matrix operations and rasterizing
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`0013
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`

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`\
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`operations on the primitive data 31. The pixel data 36 is then transmitted to the
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`respective scan converters 3? and 40 of the two graphics pipelines 101-102.
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`[0023]
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`The scan converter 37 of the first graphics pipeline 101 receives the pixel
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`data 36 and sequentially provides the position (e.g. x, y) coordinates 60 in screen space of
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`the pixels to be processed by the back end circuitry 39 by determining or identifying
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`those pixels of the primitive, for example, the pixels within portions 81-82 of the triangle
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`80 (FIG. 3) that intersect the tile or set of tiles that the back end circuitry 39 is
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`responsible for processing. The particular tile(s) that the back end circuitry 39 is
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`responsible for is determined based on the tile identification data present on the pixel
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`identification line 38 of the scan converter 37. The pixel identification line 38 is
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`illustrated as being hard wired to ground. Thus, the tile identification data corresponds to
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`a logical zero. This corresponds to the back end circuitry 39 being responsible for
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`processing the tiles labeled “A” (e. g. 72 and 75) in FIG. 3. Although the pixel
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`identification line 38 is illustrated as being hard wired to a fixed value, it is to be
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`understood and appreciated that the tile identification data can be programmable data, for
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`example, from a suitable driver and such a configuration is contemplated by the present
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`invention and is within the spirit and scope of the instant disclosure.
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`[0024]
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`Back end circuitry 39 may include, for example, pixel shaders, blending
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`circuits, 2-buffers or any other circuitry for perfonning pixel appearance attribute
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`operations (e. g. color, texture blending, z-buffering) on those pixels located, for example,
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`in tiles 72, 75 (FIG. 3) corresponding to the position coordinates 60 provided by the scan
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`converter 37. The processed pixel data 43 is then transmitted to graphics memory 48 via
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`memory controller 46 for storage therein at locations corresponding to the position
`coordinates 60.
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`[0025]
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`The scan converter 40 of the second graphics pipeline 102, receives the
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`pixel data 36 and sequentially provides position (e.g. x, y) coordinates 61 in screen space
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`of the pixels to be processed by the back end circuitry 42 by determining those pixels of
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`the primitive, for example, the pixels within portions 83-84 of the triangle 80 (FIG. 3)
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`that intersect the tiles that the back end circuitry 42 is responsible for processing. Back
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`end circuitry 42 tile responsibility is determined based on the tile identification data
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`present on the pixel identification line 41 of the scan converter fill. The pixel
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`0014
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`

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`identification line 4] is illustrated as being hard wired to Vcc; thus, the tile identification
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`data corresponds to a logical one. This corresponds to the back end circuitry 42 being
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`responsible for processing the tiles labeled “B” (e.g. 73-74) in FIG. 3. Although the pixel
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`identification line 41 is illustrated as being hard wired to a fixed value, it is to be
`understood and appreciated that the tile identification data can be programmable data, for
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`example, from a suitable driver and such configuration is contemplated by the present
`
`invention and is within the spirit and scope ofthe instant disclosure.
`
`[0026]
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`Back end circuitry 42 may include, for example, pixel shaders, blending
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`circuits, 2-butters or any suitable circuitry for performing pixel appearance attribute
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`operations on those pixels located, for example, in tiles 73 and 74 (FIG. 3) corresponding
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`to the position coordinates 61 provided by the scan converter 40. The processed pixel
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`data 44 is then transmitted to the graphics memory 48, via memory controller 46, for
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`storage therein at locations corresponding to the position coordinates 61.
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`[0027]
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`The memory controller 46 is operative to transmit and receive the
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`processed pixel data 43 -44 from the back end circuitry 39 and 42; transmit and retrieve
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`pixel data 49 from the graphics memory 43; and in a single circuit implementation,
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`transmit pixel data 50 for presentation on a suitable display 51. The display 51 may be a
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`monitor, a CR1‘, a high definition television (HDTV) or any other device or combination
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`thereof.
`
`[0028]
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`Graphics memory 48 may include, for example, a frame buffer that also
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`stores one or more texture maps. Referring to FIG. 3, the frame buffer portion of the
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`graphics memory 48 is partitioned in a repeating tile pattern of horizontal and vertical
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`square regions or tiles 72-75, where the regions 72-75 provide a two dimensional
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`partitioning of the flame buffer portion of the memory 48. Each tile is implemented as a
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`16 x 16 pixel array. The repeating tile pattem of the frame buffer 48 corresponds to the
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`partitioning of the corresponding display 51 (FIG. 2). When rendering a primitive (cg.
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`triangle) 80, the first graphics pipeline 101 processes only those pixels in portions 81, 82
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`of the primitive 80 that intersects tiles labeled “A", for example, 72 and 7'5, as the back
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`end circuitry 39 is responsible for the processing of tiles corresponding to tile
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`identification 0 present on pixel identification line 38 (FIG. 2). In corresponding fashion,
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`the second graphics pipeline 102 processes only those pixels in portions 83, 84 of the
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`0015
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`

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`primitive 80 that intersects tiles labeled “B", for example 73-74, as the back end circuitry
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`42 (FIG. 2) is responsible for the processing of tiles corresponding to tile identification 1
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`present on pixel identification line 41 (FIG. 2).
`
`[0029]
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`By configuring the flame buffer 48 according to the present invention, as
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`the primitive data 31 is typically written in strips, the tiles (e.g. 72 and 75) being
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`processed by the first graphics pipeline 10] and the tiles (e.g. 73 and 74) being processed
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`by the second graphics pipeline 102 will be substantially equal in size, notwithstanding
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`the primitive 80 orientation. Thus, the amount of processing perfonned by the first
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`graphics pipeline 101 and the second graphics pipeline 102, respectively, are
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`substantially equal; thereby, efiectively eliminating the load balance problems exhibited
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`by conventional techniques.
`
`‘ [0030]
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`FIG. 4 is a schematic block diagram of a ti-ame buffer 68 partitioned into a
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`super-tile pattern according to an alternate embodiment ofthe present invention. Such a
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`partitioning would be used, for example, in conjunction with a multi-processor
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`implementation to be discussed below with reference to FIG. 5. As illustrated, the frame
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`buffer 68 is partitioned into a repeating tile pattern where the tiles, for example, 92-99
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`that form the repeating tile pattern are the responsibility of and processed by a
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`corresponding one of the graphics pipelines provided by the muiti-processor
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`implementation.
`
`[0031]
`
`FIG. 5 is a schematic block diagram of a graphics processing circuit 54
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`which may be coupled with the graphics processing circuit 34 (FIG. 2), for example, by
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`the AGP 32 or other suitable port, to form one embodiment of a multi-processor
`
`implementation. The graphics processing circuit 54 is preferably a portion of a stand-
`
`alone graphics processor chip or may also be integrated with a host processor or other
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`circuit, if desired, or port of a larger system. The multi-processor implementation
`
`exhibits an increased fill rate of, for example, 9.6 billion pixels/sec with a triangle rate of
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`300 million triangles/sec. This represents a tremendous performance increase as
`
`compared to conventional graphics processing