Applicatiorilcontrol Number:
`1 0!459,T97
`Art Unit: 2628
`
`_
`
`DETAILED ACTION
`
`2 Information Disclosure Statement
`
`1.
`
`Information disclosure statement (IDS) submitted on November 28, 2007 was filed after
`
`mailing date of application on June 12, 2003. Submission is in compliance with provisions of 37
`
`CFR 1.97. Accordingly, information disclosure statement is being considered by the examiner.
`
`-Response to Arguments
`
`2.
`Applicant’s arguments, see pages 9-11, filed November 28, 2007, with respect to the
`rejeetion(s) of claim(s) 1-4, 7, 10, 12, 14, 20-22, and 25 under 35 U.S.C. 102(c)' and claims 5, 6,
`
`11, 13, 15-19, and 24 under 35 U.S.C. l03(a) have been fully considered and are persuasive. So,
`
`the rejection has been withdrawn. However, upon further consideration, a new ground(s) of
`
`rejection is made in view of Former (US006778177B1) and Maclnnjs (US0065?0579Bl).
`
`3.
`
`' Applicant argues Perego (USO06864896B2) does not teach multi-graphics pipeline
`
`circuitry on same chip nor memory controller on the same chip but instead teaches discrete
`memory modules having separate and single graphics engines thereon. The memory controller
`
`taught in Perego is not on a same chip nor is it part ofthe memory module (page 10).
`
`' In reply, new grounds of rejection are made in view of Furtner and Maclnnis.
`
`Claim Rejections - 35 USC § I 03
`
`- 4.
`
`-
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in
`section [02 of this title, if the differences between the subject matter sought to be patented and the prior art are
`such that the subject matter as a whole would have been obvious at the time the invention was made to a person
`having ordinary skill in the art to which said subject matter pertains. Patentahility shall not be negatived by the
`manner in which the invention was made.
`
`0401
`
`Volkswagen 1002 - Part 5 of 8
`
`

`
`Applicationlcontrol Number:
`10I459,797
`Art Unit: 2628
`
`Page 3
`'
`
`- The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. I; 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. 103(a) are summarized as follows:
`
`Determining the scope and contents of the prior art.
`Ascertaining the differences between the prior art and the claims at issue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence present in the application indicating obviousness -
`or nonobviousness.
`
`5.
`
`Claims 1-4, 6, 7, 10, 12, 14, and 17 are rejected under 35 U.S.C. l03(a) as being
`
`unpatentable over Perego (US006864896B2) in view of Furtner (US006778177Bl), further in
`View ofMaclnnis (US0065”/'0S79Bl).
`.
`
`6.
`
`As per Claim 1, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, 11. 61-63)
`
`having at least 2 graphics pipelines (312) operative to process data in corresponding set of tiles
`
`ofrepeating tile pattern corresponding to screen locations, respective one of at least two graphics
`
`pipelines operative to process data in dedicated tile (c. 5, ll. 19-27, 38-44); and memory
`
`controller (310, Fig. 3) in‘ communication with at least 2 graphics pipelines (312), operative to
`
`transfer pixel data between each of 1” pipeline and 2”” pipeline and shared memories (314) (c. 3,
`
`11. 65-67; c. 4, 11. 1-10, 48-65). Shared memories (314) are each part of main memory (c. 1, ll. 44-
`
`54; c. '3, ll. 3-6), and so are considered to be one memory. Repeating tile pattern includes
`
`horizontally and vertically repeating pattern of regions of square regions, as shown in Fig. 5 (c.
`
`5, 11. 19-27, 38-44).
`
`However, Perego does not teach that the graphics pipelines are on a same chip. However,
`
`Furtner teaches that the graphics pipelines -are on a same chip (0. 6, ll. 30-32).
`
`0402
`
`

`
`Applicationicontrol Number:
`10l459,797
`Art Unit: 2628
`
`it would have been obvious to one of ordinary skill in the art at the time of invention by
`applicant to modify device ofPerego so graphics pipelines are on same chip as suggested by
`
`Furtner. Placing plurality of modules on single chip takes up less space as compared to using
`multiple chips, and this is well-known in the art.
`
`However, Perego and Furtner do not teach memory controller is also on the same chip.
`
`However, Maclnnis teaches memory controller (54) is on same chip (10) as graphics pipeline
`
`(58), as shown in Fig. 2 (c. 4, 1]. 65-67; c. 5, 11. 36-41; C. 6, 11. 10-13). This would be obvious for
`
`same reasons given above.
`
`7.
`
`As per Claim 2, Perego teaches square regions have two dimensional partitioning of
`
`memory (c. 5, ll. 19-33).
`
`8.
`
`9.
`
`As per Claim 3, Perego discloses that the memory is a frame buffer (c. 5, 11. 32-33).
`
`As per Claim 4, Perego teaches each of at least two graphics pipelines includes front end
`
`circuitry (308, Fig. 3) operative to generate pixel data corresponding to primitive to be rendered,
`
`and back end circuitry (312), coupled to front end circuitry, operative to receive and process
`
`portion of pixel data (c. 3, ll. 64-c. 4, ll. 2; c. 5, II. 19-44). In order for front end circuitry (308) to
`
`generate pixel data, it must inherently receive vertex data.
`
`10.
`
`As per Claim 6, Perego does not explicitly teach each tile of set of tiles has 16x16 pixel
`
`array. But, Furtner teaches each tile of set of tiles has 16x16 pixel array (c. 1 1, 11. 45-48, 64-65).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego so each tile of set of tiles further has 16x16 pixel array because
`
`Furtner suggests depending on number of parallel image-rendering pipelines and depending on
`
`memory organization, optimum tile size and shape can be selected (c. 11, 11. 45-43, 64-65), and
`
`0403
`
`

`
`Applicationlcontrol Number:
`101459397
`Art Unit: 2628
`
`Page'5
`
`so it would be obvious to modify tile size to be 16x16 pixels if that would be optimum tile size
`
`for particular number of parallel image-rendering pipelines and particular memory organization.
`
`1 1.
`
`. As per Claim 7, Perego teaches the at least two graphics pipelines (312,-Fig. 3) separately
`
`receive the pixel data from the front end circuitry (308) (c. 3, ll. 64-c. 4, ll. 2; c. 5, 11. 19-44).
`
`12.
`
`As per Claim 10, Pere_go teaches first of at least two graphics pipelines (first rendering
`
`engine of 312, Fig. 3) processes pixel data only inifirst set of tiles (tiles labeled _“REO” in Fig. 5)
`
`in repeating tile pattern (c. 5, 11. 23-44).
`
`13.
`
`As per Claim 12, Perego teaches second of at least two graphics pipelines (second _
`
`rendering engine of 312, Fig. 3) processes pixel data only in second set of tiles (tiles labeled
`
`‘tRB1;’ in Fig. 5) in repeating tile pattern (c. s, 11. 23-44).
`
`14.
`
`' As per Claim 14, Claim 14 is similar to Claims 4 and 10, except that Claim 14 is for a
`
`third and fourth graphics pipeline. Perego teaches four graphics pipelines (c. 5, ll. 41-44). So
`
`Claim 14 is rejected under the same rationale as Claims 4 and 10.
`
`15.
`As per Claim 17, Perego does not teach 3"‘ and 4"‘ graphics pipelines are on separate
`chips. However, Furtner teaches 3'” and 4"‘ pipelines are on separate chips (c. 6, 1]. 47-51).
`
`It would have been obvious to one of ordinary skill in the art at the time ofinvention by
`
`applicant to modify Perego so pipelines are on separate chips because Furtner teaches this makes
`
`system more configurable by being able to easily add more graphics pipelines to increase
`
`performance (c. 6, 11. 29-30, 42-51).
`
`16.
`
`Claims 5, 18, and 24 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Perego (US005864896B2), Furtner (US0067781 77B1), and Maclnnis (US006570579B1) in view
`
`of Kelleher (USO0S?940l6A).
`
`0404
`
`

`
`Applicationlcontrcl Number:
`101459.797
`Art Unit: 2628
`
`Page 6
`-
`
`17.
`
`As per Claim 5, Perego, Further, and Maclnnis are relied upon for teachings for Claim 4.
`
`But, Perego, Further, and Maclnnis do not explicitly teach at each of at least two graphics
`
`pipelines further includes scan converter, coupled to back end circuitry, operative to determine
`
`portion of pixel data to be processed by back end circuitry..But, Kelleher teaches each of at least
`
`two graphics pipelines (20A, 20B, Fig. 3; c. 3, 11. 22-23; c. 4, 11. 9-14) further includes scan
`
`converter (update stage, Fig. 7), coupled to back end circuitry, operative to determine portion of
`
`pixel data to be processed by back end circuitry (c. 8, 1]. 52-61; c. 9, 11. 1-23; c. _6, 11. 26-28).
`
`1 It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify devices of Perego, Furtncr, and Maclnnis so at each of at least two graphics
`
`pipelines further includes a scan converter, coupled to the back end circuitry, operative to
`
`- determine the portion of the pixel data to be processed by the back end circuitry because
`
`Kelleher suggests scan converters are needed in order to define image data as array of pixels by
`
`calculating pixel addresses (c. 9, ll. 1-23), as is well-known in the art.
`
`18.
`
`As per Claim 18, Perego does not teach a bridge operable to transmit vertex data to each
`
`of the first, second, third and fourth graphics pipelines. However, Kelleher discloses a bridge
`
`(38, Fig. 3) operative to transmit vertex data to each ofthe first (20A), second (20B), third (20C) .
`
`and fourth (20N) graphics pipelines (c. 3, II. 22-23; c. 4, 11. 9-14; c. 8, [L 56-65; c. 3,11. 46-50).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego to include a bridge operable to transmit vertex data to each of the
`first, second, third and fourth graphics pipelines as suggested by Kelleher because Kelleher
`
`suggests the advantage of being able to convert the vertex data to pixel data in parallel, which
`
`increases the efficiency of the graphics system (c. 2, 11. 31-35; c. 8, 11. 56-65; c. 9, 11. 1-23).
`
`0405
`
`

`
`Applicationfcontrol Number:
`1 01459.79?
`Art Unit: 2628
`
`Page 7
`
`19.
`
`As per Claim 24, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, 11. 61-63),
`
`having front end circuitry (308) operative to generate pixel data in response to primitive data for
`
`primitive to be rendered (c. 5, 11. 19-23); first back end circuitry (first rendering engine 312),
`
`coupled to front end circuitry 308, operative to process first portion of pixel data (labeled “RED”
`
`in Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be
`
`processed by first back end circuitry, repeating tile pattern including horizontally and vertically
`
`repeating pattern of square regions, as shown in Fig. 5; second back end circuitry (second
`
`rendering engine 312), coupled to front end circuitry 308, operative to process second portion of
`
`pixel data (labeled “RE1 " in Fig. 5) in response to position coordinates; set of tiles of repeating
`
`tile pattern are to be processed by second back end circuitry (c. 3, ll. 63-c. 4, ll. 2; c. 5, 11. 19-44);
`
`and memory controller (310), coupled to first and second back end circuitry (312) operative to
`
`transmit and receive processed pixel data (c. 3, 11. 65-67; c. 4, 11. 1-53; c. 5, 11. 32-44).
`
`However, Pprego does not explicitly teach first scan converter and second scan converter.
`
`However, Kelleher teaches first scan converter, coupled between front end circuitry (14, Fig. 3)
`
`and first back end circuitry (update stage, Fig. 7 in 20A, Fig. 3), operative to determine which set
`
`oftiles of repeating tile pattern are to be processed by first back endcircuitry (ci. 3, 11. 22-23; c. 8,
`
`ll. 33-c. 9, ll. 23), and operative to provide position coordinates to first back end circuitry in
`
`response to pixel data (c. 4, 11. 60-62; e. 8, 1]. 52-65; c. 6, 11. 36-38); second scan converter,
`
`coupled between front end circuitry and second back end circuitry (update stage, Fig. 7 in 20B,
`
`Fig. 3), operative to determine which set of tiles of repeating tile pattern are to be processed by
`
`second back end circuitry, and operative to provide position coordinates to second back end
`
`0406
`
`

`
`Applicationlcontrol Number:
`10l459.797
`Art Unit: 2628
`
`Page 8
`
`'
`
`circuitry in response to pixel data (c. 3, 11. 22-23; c. 8, 11. 33-0. 9, ll. 23; c. 4, 11. 60-62; c. 8, ll. 52-
`
`65; c. 6, 11. 36-38). This would be obvious for same reasons given in the rejection for Claim 5.
`
`However, Perego and Kelleher do not teach front end circuitry, first back end circuitry,
`
`first scan converter, second back end circuitry, and second scan converter are all on same chip.
`
`However, Furtner teaches graphics pipelines are on same chip (c. 6, 11. 30-32). Front end
`
`circuitry, first back end circuitry, and first scan converter of Perego-Kelleher combination make
`
`up one graphics pipeline, and ficnt end circuitry, second back end circuitry, and second scan
`
`converter of Perego-Kelleher combination make up another graphics pipeline, as discussed
`
`above‘. Since Furtner teaches graphics pipelines are on same chip, this teaching from Furtne-1' can
`
`be applied to Pei-ego-Kelleher combination so front end circuitry, first back end circuitry, first
`
`scan converter, second back end circuitry, and second scan converter are all on same chip. This
`
`would be obvious for reasons for Claim 1.
`
`However, Perego, Kelleher, and Furtner do not teach memory controller is also on the
`
`same chip. However, Maclnnis teaches this limitation, as discussed in the rejection for Claim 1.
`
`20.
`
`Claims 11, 13, 15, and 16 are rejected under 35 U.S.C. 103 (a) as being unpatentable over
`
`Pere go (US006864896B2), Furtner (US006778177B1), and Maclnnis (USOO6570579Bl) in view
`
`of Kellcher (US005794016A), further in View of Hamburg (US00590S506A).
`
`Perego, Furtner, and Maclnnis are relied upon for teachings relative to Claim 10.
`
`I-Iotvever, Perego, Furtner, and Maclnnis do not explicitly teach scan converter.
`
`However, Keileher teaches first ofthe at least two graphics pipelines‘(20A, Fig.‘ 3; c. 3, 11. 22-23;
`
`c. 4, 11. 9-14) further includes scan converter (84, Fig. 7), coupled to front end circuitry (80, 32)
`
`and back end circuitry (c. 8, ll. 52-c. 9, ll. 23). Sean converter determines which groups of blocks
`
`0407
`
`

`
`Applicationlcontrol Number:
`10l459.797
`Art Unit: 2628
`
`Page 9
`
`52 within graphics memory 22 are allocated to and controlled by graphics pipelines (c. 8, ll. 52-
`
`65; c. 6, 11. 26-28). Graphics memory is partitioned into plurality ofpixel blocks that are tiled in
`
`x-and y-direction of graphics memory (c. 4, 11. 60-62). So, scan converter is inherently operative
`
`to provide memory addresses or position coordinates of pixels within first set of tiles to be
`
`processed by back end circuitry. This would be obvious for reasons for Claim 5..
`
`But, Perego, Furtner, Maclnnis, Kelleher do not explicitly teach using tile identification
`
`data to indicate which tiles are to be processed. But, Hamburg teaches pixel identification line
`
`for receiving tile identification data indicating which tiles are to be processed (c. 5, II. 35-52).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify devices of Perego, Furtner, Maelnnis, and Kelleher to include using tile
`
`identification data to indicate which tiles are to be processed because Hamburg suggests
`
`advantage ofusing tile identification data to easily track storage locations oftile pixel data and
`
`being able to easily retrieve data for particular image tile (c. 1, ll. 46-54).
`
`21.
`
`Claim 19 is rejected under 35 U.S.C. l03(a) as being unpatentable over Perego
`
`(US00-586489632), Furtner (US006778177B1), and Maclnnis (US006S70579B1) in view of
`
`Kent (US 20030164830A1).
`
`' Perego, Furtner, and Maclnnis are relied on for teachings for Claim 17. Perego teaches
`
`data includes polygon (c. 5, 11. 19-23). Furtner teaches third and fourth graphics pipelines are on
`
`separate chips (e. 6, 1]. 47-51), as discussed for Claim 17.
`
`But, Perego, Furtner, and Maclnnis do not teach creating bounding box around polygon
`
`and each corner of bounding box is checked against super tile that belongs to each separate chip
`
`and if bounding box does not overlap any of super tiles associated with separate chip, then
`
`0408
`
`

`
`Applicationlcontrol Number:
`101459397
`Art Unit: 2628
`
`-
`
`Page 10
`
`processing circuit rejects whole polygon and processes next one. But, Kent teaches graphics
`
`pipeline [0006] calculates bounding box ofprimitive and testing this against VisRect. If
`
`bounding box of primitive is contained in other P10’s super tile the primitive is discarded at this
`
`stage [0129]. Primitive can be polygon [0088]. Method used is to calculate distance from each
`
`subpixel sample point in point’s bounding box to point’s center and compare this to point’s
`radius. Subpixei sample points with distance greater than radius do not contribute to pixel’s
`
`coverage. Cost of this is kept low by only allowing small radius points hence distance calculation
`
`is a small multiply and by taking a cycle per subpixel sample per pixel within bounding box
`
`[U144]. Since method calculates distance from each subpixel sample point in point’s bounding
`
`box, this must include all corners ofbounding box. So, Kent teaches data includes polygon and
`
`graphics pipeline creates bounding box around polygon and wherein each corner of bounding
`
`box is checkedlagainst super tile that belongs to graphics pipeline and if bounding box does not
`
`overlap any of super tiles, ‘then processing circuit rejects whole polygon and processes next one.
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego, Furtner, and Maclnnis to include bounding box as because Kent
`
`suggests processing super tiles one at a time in order to hide page break costs [0l29, 0051].
`
`22.
`
`. Claims 2022 and 25 are rejected under 35 U.S.C. 103(3) as being unpat-entable over
`
`Perego (US006864896B2) in view of Former (US006778177B1).
`
`23.
`
`As per Claim 20, Perego teaches graphics processing method, comprising generating
`
`pixel data (c. 5, ll. 19-25), which is inherently generated in response to received vertex data;
`
`determining pixels within set of tiles of repeating tile pattern corresponding to screen locations to
`
`be processed by corresponding one of at least two graphics pipelines (312, Fig. 3) in response to
`
`0409
`
`

`
`Applicationlcontrol Number:
`10l459.797
`Art Unit: 2628
`
`pixel data, repeating tile pattern including horizontally and vertically repeating pattern of square
`
`I
`
`regions, as shown in Fig. 5; performing pixel operations on pixels within determined set of tiles
`
`by corresponding one of at least two graphics pipelines (c. 5, 11. 19-44); and transmitting
`
`processed pixels to memory controller (310), wherein at least two graphics pipelines share
`
`memory controller (c. 3, 11. 65-0. 4, ll. 25; c. 5, 11. 31-44).
`
`However, Perego does not teach that the graphics pipelines are on a same chip. However,
`
`Furtner teaches graphics pipelines are on a same chip (c. 6, 11. 30-32), as discussed for Claim 1.
`
`24.
`
`As per Claim 21, Perego teaches determining pixels within set of tiles of repeating tile
`
`pattern to be processed further comprises determining set of tiles that corresponding graphics
`
`pipeline is responsible for (c. 5, 11. 19-50).
`
`25.
`
`-As per Claim 22, Perego teaches determining pixels within set oftiles of repeating tile
`
`pattern to be processed comprises providing position coordinates ofpixels within determined set
`
`of tiles to be processed to corresponding one of at least two graphics pipelines (c. 5, ll. 19-44).
`
`26.
`
`I As per Claim 25, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, 11. 61-63)
`
`having at least two graphics pipelines (312) operative to process data in corresponding set of tiles
`
`of repeating tile pattern corresponding to screen locations, respective one of at least two graphics
`
`pipelines operative to process data in a dedicated tile (c. 5, 11. 19-27, 38-44), wherein the
`
`repeating tile pattern includes a horizontally and vertically repeating pattern of regions of square
`
`regions, as shown in Fig. 5 (c. 5, 11. 19-27, 38-44).
`
`However, Perego does not teach. that the graphics pipelines are on a same chip. However,
`
`Furtner teaches graphics pipelines are on a same chip (c. 6, 11. 30-32), as discussed for Claim 1.
`
`0410
`
`

`
`Applicationlcontrol Number:
`101459.797
`_Art Unit: 2628
`
`Conclusion
`
`Applicanfs amendment necessitated the new ground(s) of rejection presented in this
`
`Ofiice action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP §.’706.07(a).
`Applicant is reminded ofthe extension oftime policy as set forth in 37 CFR 1.136(a).
`
`A shortened statutory period for reply to final action is set to expire THREE MONTHS
`
`'
`
`from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of
`
`the mailing date of this final action and the advisory action is not mailed until after the end of the
`
`THREE-MONTH shortened statutory period, then the shortened statutory period will expire on
`
`the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be
`
`calculated from the mailing date of the advisory action. In no event, however, will the statutory
`
`period for reply expire later than SIX MONTHS from the date ofthis final action. I
`- Any inquiry conceming this communication or earlier communications from the
`
`examiner should be directed to Joni Hsu whose telephone number is 571-272-7785. The
`
`examiner can normally be reached on M-F _3arn-5pm.
`
`If attempts to reach the examiner by telephone are unsuccessful, the exarniner’s
`
`supervisor, Kec Tung can be reached on 571-272-7794. The fax phone number for the
`
`organization where this application or proceeding is assigned is 571-273-8300.
`
`0411
`
`

`
`Applicationlcontrol Number:
`1 0!459,797
`Art Unit: 2628
`
`Infonnation regarding the status of an application may be obtained from the Patent
`
`Application Infonnation Retrieval (PAIR) system. Status information for published applications
`
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished
`
`applications is available through Private PAIR only. For more information about the PAIR
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`
`JH
`
`KEE M.TL]NG
`SUF’EFlViSOFlY PATENT EXAMINER
`
`0412
`
`

`
`Index Of Claims
`
`10459797
`
`LEATHER ET AL.
`
`Appllcatiunfcontrol No.
`
`Applicant(s)1Patent Under
`Reexamination
`'
`
`|||||||
`
`|||
`
`||l1|W|ll|l|| Hlll
`
`I Cancelled
`I
`
`CLAIM
`
`Original
`
`‘IZIOTIZDO?
`
`“.5. Pa?-Bl" Bfld Trademark OFFICE
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`'
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`Pan of Paper No_ -_ 112307
`
`0413
`
`

`
`Applieationlcontrol No.
`
`Search Notes
`
`10459797
`
`'
`
`Examiner
`
`Hsu, Joni
`
`AppIicant(s)!Patent Under
`Reexamination
`LEATHER ET.AL.
`
`Art. Unit
`
`2628
`
`J J
`
`13
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`SEARCH NOTES
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`U.5. Patent and Tradernark Oflioa
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`0414
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`Undertho Pa v orworit Reduction hotel 1595 no - rsons are a -
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`Joni Hsu
`U.S. PATENT DOCUMENTS
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`Maclnnis et al.
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