PCI System Architecture
`
`
`Deslner May Step Address, Data, PAH (and PAR64)
`and IDSEL
`
`The address may be stepped onto the AD bus (incluxiing the 64-bit extensicm)
`because it is qualified by FRAME#. PAR [and PAR64} may also he stepped be-
`cause _t.t_1e}§ _a_.re
`qualified one clock_ after the end of the address
`phase and each data phase. IDSBL can he stepped because it 'i5"'C11-131ified'by
`the I""RAM.E# signal (refer to the section erltitled "R£sistivelyhCoup1ed IDGEL
`I3 Slow” in the chapter Entitled "'CoI_'Ifigurétio:1'
`'l‘ramact-ions”). Data can he
`stepped onto the AD bus ctuzring each data phase because it is-qualified by the
`assertion of IRDY# (cm a write) or'I'RDY# (an a read).
`
`Table B-3 defines the relatianship of the AD bus, PAR, PAR54,
`DEVSEH and the
`that qualify them as valid.
`
`and
`
`"'“-'-M-man--
`
`3-
`
`'
`
`-
`
`W "WW e=1==mPe
`
`' asserted at the end of the address hase.
`
`AD bus during data phase on Qualified when 'I‘RDY# signal sampled
`read
`assemedmarfimgdockedgedlmxlgme
`data haze.
`AD bus cl_I.n-lug data phase on Qualified when I1-!DY# signal sampled
`write
`asserted on a rising clock edge during the
`data hasfi.
`
`I
`'
`
`PARandI-‘AR54
`
`Implicitly qualified on rising clock edge
`after address phase, or by IRDY# and
`TRDY# data hase .
`
`Qualified when FRAME! sampled as-
`set-ted at‘ the end of the address phase
`and a. type zero configuration ’com.tna'nd
`is present on the CUBE bus (with AD[1:D]
`
`continuous and Discrete Stepping
`
`The initiator (or the target) may use one of two melhods to step a valid id‘
`dressordataont-otl1eADbu.s,ora\raltdleve1ontothePARa:-.dPAR6-£55
`li.n.es,orID5EL:
`
`
`
`-
`
`
`
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`
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`
`

`
`--
`
`.
`
`'
`
`Chapter 8: The Read. and Write Transfers
`
`I
`
`If the device driving the AD bus and the parity pins or IDSEL, either ini-
`tiator or target, uses very weak output drivers, it may take several clocls
`For if to ¢11'i‘|-'8 a. Valid level unto these bus signals (i.e., the propagation
`delay may be lertgflry became it may take several reflections, with the re-
`sultant voltage-doubling effect, before the -address [or data) is in the cor-
`rect state on the bus)- This is known as continuous st-epp:Lng.. See note in
`the_r_t_extsecl1'on.
`,
`_
`0- The device clrivingthe Aflhussnd the'paritypins or IDSEL, either init1'a-
`tor or target, may have strong output drivers and may drive a subset of
`them on eadi ofseverei dock edges until all ofthemhave been driven.
`This is known as discrete stepping.
`
`_
`
`-
`
`--
`
`Disadvantages of Stepping
`
`There are two disadvantages associated with stepping:
`
`0 Duetothe prolongedperiod itlakes tosel:uptheaddre.sso_r dataon the
`bus, there is a performance penalty associated in any address or data
`phase where stepping is used.
`In the midst of stepping the address onto Ene bus, the arbiter may remove
`the grant from the stepping master. This subject is covered in the next
`section.
`
`I
`
`The specification strongly discourages the use of continuous stepping because
`it results in poor perfom-.aru_:e and also because it creates violations of the in-
`put setup time at all inputs.
`
`Preemption While Stepping in Progress
`
`When the PCI bus arbiter grants the ‘bus to a bus master, the master then waits
`for bus idle before initiating its trensai-:l'ion. If, during this period of time, the
`arbiter detects arequest from a higher priority master, it can remove the grant
`from the first master before it begins a transaction (is, before it asserts
`1"-RAME#}.
`
`Assuming that this doesn't_oocur, the master retains its grant and awaits bus
`idle. Upon detection of the bus idle state, the roasterbegins to step the addrms
`onto the AD bus, but delays the assertion of FRAME! for several clocks until
`the address is fully-driven.
`this period of time, the arbiter may still
`remmie the grant from the master. The arbiter hasn't detected FRAME? as-
`
`
`
`157
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`
`

`
`PC! Sgtem Arcliitecture
`
`I
`
`_
`
`_
`
`gerigcl andngay therefocre assume Ehat thernaster ham‘! yet started a transac-
`tion{eventhoughthe arbit:eroanseetl1atthebteisidle).If1he arbiter receives
`a request from a higher-prioflty master, it may remove the grant from the
`master that is currently engaged ln stepping an address onto the AD bus. In
`response to the loss of grant. the-stepping masher must immediately hi-st-ate
`iIsD_utpu,tdrivers.___
`-
`_
`_
`
`It is a rule that the arbiter cannot deassert one master's grant and assert grant
`toanothermasterduringthesameelockoellifthebusisidle. Thebusmay
`ntminfact. be idle. A mestermay nothave asserted FRAME! yet because itis
`in the act of stepping the address onto the AD bus.
`.
`
`If the arbiter were to simultaneously remove the stepping master’: GN'l'# and
`issue GNN to another master. the followiltg problem would result. On the
`next rising-edge of the clock, the stepping inaster detects removal of its GNT#
`and begins to turn off its address drivers. Al: the same time, the other master
`detects its GN'I‘# and bus idle (because the stepping master had not yet as-
`sertedFRAl'v£E#)and1'n1tiatesa transacIJ'on.'I'hisresults in a oolhaion on the
`AD bus.
`
`
`'- &fi1hfi..«:m-u.:..r.....qnlheiufindierura
`
`
`
`Whenthebus appears tobeidlefihearbsitermustremove Ihegrant from one
`master, wait one clock cell, and then assert pant to the other master. This
`provides a one clock cell buffer zone for the stepping master to disconnect
`completely before the Other master detects ils gent plus bus idle and starts its
`transaction.
`
`It is permissible for the orbiter to simultaneously remove one master's grant.
`and assert anothefs during the same clock cell it‘ the bus isn't idle (Le, a
`tranaactionis inpr-ogres's).Thereisr1o dangerofacollisionbecause themasber
`that has just received the grant cannot start driving the bus until the current
`master idles the bus.
`
`Broken Master
`
`-'
`
`g.
`
`The arbiter may assume. that a master is broken if the arbiter has issued GN'I'# T
`tsotheanaster, thebushasbeerLidle£or16clocl:s,a'Ir1thenI.asberhasnuta*.t- .
`- sorted FRA_ME# to start its transaction. The arbiter is permitted to ignore all
`further requests from the broken master and may optionally report the failure
`to the operating -system (in a device-specific fashion}.
`
`158
`
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`
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`
`

`
`Chapter 8: The Read and Write Transfers
`
`Stepping Example
`
`Figure 8-5 provides an example of an initiator using stepping over a period of
`three clocks to drive the address unto the AD bus. The initiator can start the
`transaction on clock three (GN'I'# sampled asserted and bus idle: FRAME#
`and IRDY# sampled. deasserted}. It then begins to drive the address onto the
`AD bus and line command onto the C/BE bus. During the clock cell four, it
`- contiIiues' to dfiire the eddress imte the AD bus. During the clock cell five, it
`finalizes the driving at the address and asserts FRA.ME#. indica ling the pres-
`-ence of the address and oclmmarld. When the targets sample FRAME# ass
`set-ted cm the rising-edge of clock six [the end of the address phase), they latch
`the address and earrumand and begin the address decode. Since this is an ex-
`ample of 1 write transactien, the initiator begins to drive the data onto the AD
`bus at the start of the data phase (clock six). Once again, it uses stepping, as-
`serting the write-data ever a period of two clocks. It wittuhelds the assertion of
`TRDY# until the data has been fully driven.
`
`,
`
`159
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`
`

`
`I’L] 52518!!! Al'Cl.1ltECfl‘.lI'E
`
`Figure 8-5. Example gfAddress Stepping
`
`160
`
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`
`

`
`Chagter 8: The Read and Write Transfers
`
`when Not to Use Stepping
`
`Stepping must not be utilized when using 64-bit addressing because tergels
`that respond to 54-bit addressing expect the upper 32 bits of the address to be
`presented one
`after FRAMCE# is sampled asserted.
`
`_ _'M1o MusL_Support.Stepplng?_
`
`_
`
`_
`
`_,
`
`All PEI devices mustbe able to handle address ms data stepping performed
`by the other party in a transaction. The ability to use stepping, however, is
`optional.
`
`
`“
`
`Response to Illegal Behavior
`
`Upon detection of illegal use of bus protocol, all PCI devices should be de-
`gned to gracefully return to the idle state [i.e., cease driving all bus signals)
`as quiclgly as possible. The specification is understandably vague on this point.
`It depends on the nature of the protocol violation as to whether the devices
`can gracefully return to their idle states and still fimction properly. As an ex—
`ample, the specification cites the E5B.‘Wl'lEl!E the in.it1'ator simultaneously deali-
`serts FRAME# and IRD‘1'll‘. IN this case, when the large! detects this illegal end
`to the transaction, it is suggested that the target deassert all target-related sig-
`nals and return its state mad1inc to the idle state. In the event that a protocol
`vlolatlml leaves a target device questioning its ability to function correctly in
`the future, it can respond to all future access attempts with a target abort. If
`the target thinks that the protocol violation has not impaired its ability to
`flsnction correctly, it just surrenclers all sigrula, returns to lite idle state, and
`does not imlicate any type of error.
`
`161
`
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`
`

`
`Part VIIF
`
`66MHz PCI
`
`Implementation %
`
`_... .. ._n4.n.nI-IE-
`
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`Petitioners HTC & LG - Exhibit 1019, p. 177
`
`

`
`Chapter 22: 66MHz PCI Implementation
`
`Chapter 22
`
`Prior To This chapter
`
`The previous chapter provided a detailed description of issues related to
`caching from PC! memory targets. T1155 subject was segregated in the latter
`part of the book because most PCI systems currently on the market do not
`support cacheable memory on the PCI bus. It injects considerable complexity
`into system and component deaiyl and the rewards may not be jnsfified (due
`to the resultant degradation in perforrnance).
`
`In This chapter
`
`This chapter describes the impletrtentation of a 615MHz bus and components.
`
`111e Next Chapter
`
`The next I::ha.pter provides an overview of the Vl'_.SITecl1no1og'y VL.B2(39x So-
`percore PCI chlpselj.
`
`
`Introduction
`
`The revision 2.1 PCI specification defines support for the implementation of
`buses and components that operate at speeds of up to 66M.Hz. This czhapter
`covers the issues related to this topic.
`
`
`66MHz Uses 3.3V Signaling Environment
`
`EGMI-lz components only operate correctly in a 3.3? signaling environment.
`'l'he,5V environment is not supported. ‘this mean: that 66M!-Iz add-in cards
`are keyed to install in 3.3V or universal card connectors and cannot be in-
`stalled in 5V card connectors.
`
`
`
`'-0-.1-.4-rs,——ur
`
`
`
`489
`
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`
`

`
`"
`
`‘
`
`PCI System Architecture
`
`How components Indicate sous: Support
`
`The 66M'H.s PCI component or add-in card indicates its support in two fash;
`iorus: electricalljr and prog;ramJr|eticall.}’.
`
`A 66MHz.~'PCI bus includes -a newly-defined signaL This signal‘ must
`be hussed to the M66EN pin on all 66MI-Iz-capable devices embedded on the
`system board and in a redefined pin (referrecl to as N_I66EN) on any 3.3V oun-
`nectors that reside on the bus. The system board designer must supply a sin-
`glepullup onthistraoe.'I11eredefinedpinontl1e3.3VconnectorisB&9 andis
`usedasegrotmdpinbjr33MHzPCIdevioes.Urdessg:oundedbyaPCIde-
`viceylhenaluralstateoftheM6fiEN8igna1isasse:ted(dueto1hepuItup).
`66M!-I2: embedded devices and cards either use MGGEN as an input or don't
`use it at all (this is discussed later in this chapter).
`
`--
`
`must include a 0.01914 capacitor located within .25” of the
`The
`M66ENpin oneachadd-incozmeetorin or-dertaprovide an'AC returnpath
`a:ndtodecaupletheM66EN signalta ground.
`
`The PC! devices embedded on a 56M}-I2 PCT has are all 66M}-Iz devices. A
`eardinstalledirnsoonnector ont1rebusmaybeeith‘era66MHzora33MHz
`card. If the card eor:ne::tor(s) aren't populated, M65EN stays asserted (by vir-
`tue of the pullup). If any 33M!-lz component is installed in a comrnector, the
`gro1mdpIsneonthe33MHzcardiscm1nectedto t'heM66BNsigna],deassert-
`infg it.
`
`How Clock Clreult Sets Its Frequency
`
`'1'heM66ENsigi-ualisprovidedssaninputto thePCl dockdrcuit onthesys-
`temboard. l£M66ENis sampled assertedbythe clock drcuibitpmvidess
`66M}-Iz PC! clock to all PCI devices. If MGGEN is sampled cleasserted, the
`dock circuit supplies a 33MHz PCI clock. It should be fairly obvious that if
`any 33M.Hz oomponents are installed on a 661‘vfl-Iz bus, the bus then operates
`at 33MHz.
`
`
`Does clock Have to be 6BMHz?
`
`As defined in revision 1.0 and 2.0 of the specificatiort, the PCI bus does not
`have to be implemented at its top rated. speed of SSMI-Iz. Lower speedfi 51‘
`
`490
`
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`
`

`
`Chapter 22: 66MHz PCI Implementation
`
`acceptable. The same is true of the SEMI-lz PCI bus description found in revi-
`sion 2.1 of the speciiicafim. All SEMI-Iz-rated components are required to
`support operation from El through SEMI-Iz. The system designer may choose,
`however, to implememt a SDMI-Iz PCI bus, 3, GUMI-Iz PCI bus, etc.
`
`
`«clock-SignalSource-and-Routing -
`
`-
`
`-
`
`—
`
`-
`
`-
`
`_
`
`t
`
`The specification recommends that the PCI clock be individually-sourced to
`each PCI component as a point-to-point signal from separate, low-skew clock
`drivers. This dimirdshes signal refleclion effects and improves signal iriiiegrity.
`In addition, the system board and add-in card designer must adhere to the
`clock signal maximum trace length defined in revision 2.0 of the specification
`:25").
`
`
`Stopping Clock and Changing Clock Frequency '
`
`As with the 33MHz PCI bus specification, the 66MI-I2 specification states that
`the clock frequency may be changed at any time as long as the clock edges
`remain clean and the minimum high and low times are not violated. However,
`the clock frequency may not be changed except in conjunction with assertion
`of the PCI RST# signal. As an exception, components designed to be inte-
`grated onto the system-t board Inay be designed to operate at a fixed frequency
`(up to 66M!-Iz) and may require that no clock frequency charlges occur.
`
`The clock may be stopped. but only in the low state (to conserve power).
`
`
`How 66MHz Components Determine Bus Speed
`
`When a GISMHZ-capable device senses M66EN deasserted (at reset time). this
`automatically disables the device's ability to perfonn operations at speeds
`above 33MI-Is. If M66EN is sensed asserted, this indicates that no 33MI-Is de-
`vices are installed on the bus and the clock circtlit is supplying a high-speed
`PCI clock.
`
`A ISSMI-Iz device uses the MGGEN signal in one of two fashions:
`
`I9
`
`The device is not connected to MGGEN at all (because the devim has no
`need to determine the bus speeciin order to operate correctly).
`
`
`
`491
`
`5
`
`i
`
`3_
`
`i
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`
`

`
`
`
`.-..-“gamma
`
`r.-«'-Nun.
`
`I
`
`
`
`I"5'5'26.")-:'a-o'_-v-'=I---Cb-w-h-41*.4:‘.-Lah"ato.....‘.-an-=$:i.1-r.
`
`
`
`
`
`PCI System Architecture
`
`I As described above, the device implements MISGEN as an input (ll-ecatjag
`the device nequires lmowledge of the bus speed in order to operate ‘cor.
`rectly).
`
`
`‘System BoardwltI'rSeparate Buses
`
`-
`
`—
`
`-.
`
`.
`
`The system board designer can partition the board into two or more PCI
`buses. A 56M!-lz bus can be populated with devices that demand low-latency
`and high throughput. A separate 331%!-I2 PCI bus is populated only with
`33M}-Izdevices.
`
`
`Maximum Achievable Throughput
`
`The theoretimlmasdmumacltievablethroughputone 66MHzPCIbus would
`be:
`
`0
`
`data phases per second a
`4 bytes per data phase “ 65
`264MBfsecond..'I'hiswou1dbea32~bitbusmaster burstingwitl1a32-hit
`target.
`0 Bhytaperdatsphase'66m1'lliondataphasesperseoond=
`528MB/second. This wouldbe a 64-bit bus master bursting with s 64~hit
`target.
`
`
`Electrical Characterlstics
`
`To ensure compatibility when operating in .a 33M!-I: PCI bus environment,
`66M!-I2 PC! drivers must meet the same DC dtarsctetistics and AC drive
`points as 331MHz bus,d.1-ivers. However, 66M}-Iz PCI bus operation requizea -_
`faster tilningpsxemeters and redefinedmeasurernentoonditions. Becsuseof
`this, s 66M!-I2. PCI bus may require less loading and shorter trace lengths than '
`the 33M}-IIPCI bus envinoruznent.
`'
`
`Figu.ne22—-1 illustratestttediiferencesizttimirtghetweeruafiartdfiéltli-Izaonv
`ponent operation. The chapter entitled “Intro To Reflected-Wave S1-vifaclifl-'l5'
`provides detailed information refirdlng 33M!-Iz bus timing and the vasious“
`timing components [e.g., Tvsl, Tptop, em}.
`
`
`
`491
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`
`

`
`Chapter 22: GEM!-Iz PCI Int lementation
`
`
`
`Figure 22-1. 33 versus 66MIfi Turning
`
`33M!-Iz drivers are specifieclby their VII curves, while 561541-lz drivers are
`specified in l:en:I'ls of their AC and DC drive points, fiming parameters, and
`slew rate. The specification defines the following parameters:
`
`a
`
`-
`
`I
`I
`
`The rnlrlimurn. AC drive point defines an acceptable first step voltage and
`must be reached
`the maximum Tval time.
`
`The maximum AC drive. point limits the amount of overshoot and under-
`shuot in the system.
`The DC drive point specifies steady-state oondifiom.
`1lteminimumalewrateandthefimingpa1ametersguarantee6&MHzop-
`eratiun.
`
`0 The maxin-unn % rate minimizes systan noise.
`
`65M!-IzP£‘_‘I designers must design drivers that launch sufl’-1-zient energy into a
`259 transmission line so that correct input levels are guaranteed after the East
`reflection.
`
`At 66M!-12., the clock qcle time is 15:15 (Vs. Slln.-5 at 33MI-Iz), while the mini-
`mum eloek high and low times are fins each (vs. 11:15 at sfilvfl-Iz). ‘Die clock
`slew rate has a minimum specification of 1.5 and a maximum of 4 voltsfns
`(same as.33MI-Iz specification). Table 22-1 defines the GEMI-Iz timing parame-
`ters and provides a side-by-side comparison with the 33M]-I2 timing pumme-
`Iaers. The Following exception applies to the 66_MHz values in the table: RI-IQ#
`and GNT# are point-to-point signals and have different setup times than do
`busaed signals. They have a setup time of 5115.
`
`
`
`693
`
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`
`

`
`PCI System Architecture
`
`
`Table 22-1. EGMHZ Timi
`
`; Parameters
`
`
`
`__.
`CLK to signal valid delay, bussed
`Si. 315
`
`ELK
`
`:9E e E
`Active to float dela
`
`Input setup time to CLK. bussed
`-9 an
`Input setup time to Ci.-K, point.-
`I
`B‘ 31
`In ut hold time from CT."-K
`Reset active time after power eta-'
`
`t’
`
`Reset active time after CLK stable
`Reset active to on ut float dela
`
`REQ54# to RSI'# setu - time
`R5T# to REQ64-#11o1d time
`
`_H sEEE:
`I-ii-Il-II-I:1HI4|-iI-I-
`
`'3:
`
`
`
`asses;EIIIIIEIEEE
`
`lifiililififitslslllllilsss
`sitesii 5
`
`100
`
`
`
`When computing the GGMI-iz bus loading model, a maxiinum pin capacitanoe
`o£ 1CipF must be assumed for add-in boards, whereas the aciuai pin capacia
`tance may be used for devices embedded on the system board.
`
`
`Addition to configuration Status Register
`
`A 66'MHz-capable device adds one additional bit to its configuration status
`register. Bit 5 is.defiI'led as the 66MHZ.-CAPABLE bit. A 66M!-Iz-capable de-
`vice hardwires this bit to one. For all 33MHz devicw, this bit is reserved and
`is hardwired to zero. Software can detennine the speed capability of a PCI bus
`by
`the state of this bit in the status register of the bridge to the bus in
`question (host/PCI or PCI-to-PCI bridge). Software can also check this bit in
`the status register of each additional device discovered on the bus in question
`to determine if all of the devices on the bus ere 66M]-lz-capable. If even just
`one device returns a zero from this bit, the bus runs at 133MHz, not 66MHz-
`Table 22-2 defines the combinations of bus and device capassmy that may be
`detected.
`
`494
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`
`

`
`Chapter 22: 66MHz PCI Im-plementat-lion
`
`m1: 22-2. Combinations . 66MHz—C be Bit 3ett' ;
`
`Bridge'e 66MHz- Device’: 66MHz-
`Cble Bit _ ble Bit
`_
`_
`Descri ‘on
`_
`_
`_
`—— 33MI—Iz device located on 33MJ_-lz bus. Bus
`
`
`
`
`
`
`
`
`and all devices o - rate at 33MI'I2-.'-
`
`
`
`EGMI-Iz-cepable device located on 33MI-lz— -
`bus. Bus and all devices operate at SBMI-I2.
`If the device is anndd-in device and is only
`capable of proper operation when _in.st'alled
`on a 66M!-I2 bus, the configuration soft-
`ware may decide to prompt the user to in-
`stall the card in an add-in connector on a
`
`
`
`
`
`'33MHz device located on EEIVEHZ-capable
`bus. Bus andall devices o rate at 33MI-Iz.
`66MHz-capable clevioe located on 66]V[Hz-
`
`capable bus. If status checl: oi all other de-
`vices on the bus indicates that ‘all of the
`devices are 661*/II-Iz capable, the bus and all
`
`devices :3 - crate at 66M!-Iz.
`
`
`
`
`Latency Flule
`
`Devices residing on the 66M!-Iz PCI bus are typically low-latency devices. The
`revision 2.1 specification requires that, on a read transaction, the Hme from ae-
`serlcion of FRAME# to the completion of the first data phase not exceed 16 PCI
`clocks. If it will, the target device must issue retry to the master. For multi-
`media _‘¢'t]Jpl.'lCfifiO1't5, themajority of accesses are writes‘, not reads. Typically, a_
`target device can acnept write data. faster than it may be able to supply read
`data. On a read, the device may need to access a slow medium. 'I'he device-
`cannot be permitted to tie up the bus While fetching the requested data.
`
`
`66M!-lz Component Recommended Pinout
`
`The revision 2.0 specification suggested a recomrn.ended..PCI component pin-
`out wherein the signals wrapped around the component in the same order as
`the pin sequence on the add-in connector. The revision 2.1 specification states
`that "the designer may modify the suggested pi.nout...as required” to meet the
`ISGIVIHZ electrical specificatiorn
`
`495'
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`
`PCI System Architecture
`
`
`Adding More Loads ancvor Lengthening Bus
`
`. Rimming tl1ePCIbus at66Ml-Izimposes tightercanstraints on trace
`and the number of loads the bus supports. The system board designer may
`ohoose to run the bus at a lower speed (e.g., 50MHz], Ihereby pemfiifing
`longer traces and} or additional loads.
`
`
`Number of Add-In connectors
`
`-
`
`*
`
`As a general rule, there is only one add-in connector on a 66M]-I2 bus, but the
`spec:i.fi£'at|.01"l does not preclude the inclusion of additional connectors (as long
`as the electrical integrity of the bus is maintained).
`
`496
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`

`
`
`W L % i iPczrti-VIII 1
`
`ii
`Overview ofVLSI
`Technology VL82C59x
`SuperC0re PCI Chipset
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`

`
`
`
`Chagter 23: Overview of VL82C59x PCI Chizset
`
`Chapters 23 ——
`
`Prlor To This Chapter
`
`The previous chapter described the irnplernentatimt of a 156MHz bus and
`oomponents.
`_
`
`F-
`2
`
`|
`
`In This chapter
`
`0
`
`The PC! specification supports many permutations of system and therefore
`chipoet design. This chapter provides an overview of the VL82C59x Super-
`Core PCI chip set from VLSI Technology. This overview is provided to pres—
`ent an example of PCI chipset implementation. It is not intended to provide a
`detailed dasaiplion of the chipset operation. The VLSI component specifica-
`tionshouldbeoonsultedforthatpurpose Inadditlon, itisassumedthatlhe
`reader already has an understanding of the ISA bus. For detailed information
`on the ISA bus operation and environment, refer to the Addison-Wesley pub-
`lication entitled ISA System Architecture, also authored by Mindshere. The
`author would like to thank V151 Technology for providing aocess to the :hip-
`set speclflmtlon.
`
`—-——————-——————————
`chipset Features
`
`The VLSI VT.B2C59x chipset provides the core logic necessary to design a
`Pentium-based system that incorporates both the PCT and ISA buses. It sup-
`ports all 5V and 3.3V Pentium processors with host bus speeds of up to
`6EMHz. This includes the P5, P54C, P54CM and I-‘54CT. It also supports dual-
`P54C processors. The chipset dfign incluela the following features:
`
`Bridges thehoat and PCI buses.
`Bridges the PCI and ISA buses.
`Integrated L2 lookaside, direct mappeci, wr'1te—through cache.
`Integrated system DRAM controller.
`Integrated PCI bus arbiter.
`
`
`495
`
`;_
`3'1]
`
`ty
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`1
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`P
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`39
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`,
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`
`

`
`PCI System Architecture
`
`lIUIIIIjIII
`
`Provision of poated-metrtotjr write buffers in both bridges.
`Supports Pentium processors pipelinedbus cylzbea;
`_Se1f:configuring3ystem DRAMhanks.
`__ _
`.
`Shadow RAM support
`SMM support.
`Decouplecl DRAM refreah.
`Supports syncluordzed. or asynclu-onous processor and PCI clocks.
`Supports optional posting ofI/O writes.
`Optimal support for memory pretetcmang.
`PCImasterreadsfiomsyster_rLDRAMmenIorycanbe serviced frolII.proc-
`essor’s L2 cache or system memory.
`Pctmaster writestn system DRAMmemor_yam absorbedby the bridge’;
`posted-write buffet-.
`Supports multiple-data phase PCT burst transactions.
`
`Intro to chipsat Members
`
`Refer to figure 23-1. The VLSI VL32G59x Supercore PCI chipset consists of the
`following entities:
`
`.-
`
`VI.82C591 Pentium System Controller. In contunctton with ‘two VL82C592
`Data Buffem 1:113 SIMEIIX controller comprises the bridge between the host
`processor's local bus and the-PCI bus.
`'
`Vl.32C592 Pentium Processor Data Buffer. Taken together, two data buff-
`ers provide a triple-yorted dntabus bridge b-etweenthehost databus. sys-
`tem DRAM data bus and the PCI data bus [AD bus].
`between the ISA
`VL82C593 PCI/ISA Bridge. The '593 provides the
`and PCI buses. In addition, the '59S incorporates much of the ISA system
`support logic.
`
`The sections that follow provide additional irtfotmntion about the capabilities
`of the chipaet.
`
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`

`
`Chapter 23: Overview of VL82C59x PCI (Ihipset
`
`I
`
`Figure 23-1. sysum} neagu Llsing VLSI VL82C5.9x Sup.-.rCore Chipoet
`
`
`VL82c592 Pentium Prooeseor Data Butter
`
`As illustrated in figure 23-1. the hoot/PCI bridging function consists of the
`VL82C591 Pentium system controller and two VLB2C592 data buffets. The
`two data butter chips are controllecl by the ‘S91. They provide the following
`basic capabilities:
`
`In On host processor reads from systan memory. the ‘591 reads the re-
`quested data from DRAM and instructs the '592 data buffers to pass it to
`the hoot data bus.
`'
`
`I On host processor writes to system memory, the ‘S91 instructs the data
`buffers to accept the write data into the posted-write-buffer. This permits
`the host processor to conclude the memory write quickly. The posted-
`write buffer then oflloads the write data to DRAM memory.
`
`._a-«.
`
`501
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`
`'
`
`I I
`
`PC] Sfitem Architecture
`
`3 On PCI-initiated memory reads from system DRAM memory, the '591
`reads the requested data from memory and instructs the ‘592. data buffers
`to pass it to the requester on the PCI data bus.
`- Dn PC1.-initiated memory writes to system DRAM memory. the "591 ad-
`dressesmemoryanctinstructs the’592 databuffersto soeeptthe data pub
`seated on the PC! dstabus and route it into system DRAM.
`
`A discussion of the this buffer posted write capability can be found later in
`thischapter.
`
`The foilowing section discusses the functionality of the host/PCI bridge.
`
`
`‘591l’592 HOSHPCI Brldge
`
`
`General
`
`As stated earlier, the l'lost{PCI bridge functionality is provided by the '591 in
`combination with two -‘592 data buffers. The bridge performs the following
`basic functions:
`
`-
`
`-
`
`In
`o
`
`Services system DRAM memory reeds and writes initiated by the host
`processor.
`I’ermits_host prooeasor(s) L1 cad-ne(s) to snoop system memory accesses
`initiated by PG and ISA masters.
`o Translates host processor-initiated memory and 1/ 0' accesses into PC!
`memory and I/O accesses.
`Services system memory accesses initiated by PCI and ISA masters.
`Itarislatas specific host prooessomnitiated U0-operations into PCI core
`figuration read. or write operations.
`It Translates specific host processor-initiated 1/O operations into I-‘CI special
`cycle transactions.
`Incorporates the PCI and host bus arbiters.
`-
`I Translates host processor-initiated interrupt admowledge bus cycles inlfi
`PCI interrupt acknowledge transaction.
`
`
`System DRAM controller
`
`The controller for system DRAM memory resides within the ‘591. Each K‘-‘-'f“'
`cry bank (up to four) is either 64-bits {without parity) or '72-bits wide (with
`
`
`502
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`

`
`
`
`parit_y}.Eacl1bar1km1ybeupto?.55MB insize. yieldingan-Lanrieutmrpoatible
`memory population of 1GB. In additicllt, each bank may be populated with 32
`or 36-bit: memory modules, pernfiflirtg lees-costly memory upgrade. The
`DRAM configuration regiehers permit the DRAM controller to work with
`DRAMg o_‘r' va;_1-tons speeds and diifemnt geometries.
`The controller supports two-way inherleoved. page-nroude i:nerr1ory.'Dne or‘
`lwopages (onein each bank) canbe hep! open at a time. For page-mode
`DRAMs that have 1 page open timeout out’ less than 15545, the controller auto-
`matically closes ll page that has been open for a period of 101:5. When using
`DRAME with at maximum page open timeout in excess of 151,15, the 'I'Up.8
`automatic page close feature may be disabled and the refresh cycles-can take
`cereofensuring thatepegedoesnotremairr openfor anexoessiveperiod.
`Non-page mode DRAM is not supported.
`
`Refresh cycles may he set to occur every 15.625p.e, 62.5p.s, 17.'ius or '250p.a.
`DRAM refresh cycles are transparent to the processor.‘ If the processor initi-
`ates e DRAM access request simultaneously with e refresh cycle, the processor
`is atallcd (i.e., wait states are inserted in its bus cycle} Until the refresh cycle
`complete.
`
`When 3. system DRAM parity error is detected, it is reported by the assertion
`of the PCI SERR# signal (assuming that the SERRN enabled and parity error
`response bits are set in the bridge’: configuration coutmmd register). SEEM
`i.etypi::a1l_vgoonne-ctedto the ’593wh1ch asoertsNM1to thehoetprocessor
`when SBRR#. is asserted. An option perrnite bed parity to be deliberately writ-
`ten to system DRAM to facilitate-test and diagrtostics.
`.
`
`Host processor-irtitiated memory accesses that target locations above the top
`ol’i1:IsIal!edsystemDRAMare passed tothe PCI bus Indore not cached in the
`L1 and L2 caches. In addition, memory address range defined by the bn'dge’s
`eeytent attribute and program:-u:-Led memory region registers are also passed
`to the PCIb'ue and are not cached from.
`
`The chipset does not permit the L1 and L2 caches to cache inforrmrtlort from
`mmtory beyond the host/PC! bridge 6.2., PCI and ISA rrteroory). This being
`the ease, the ‘591 does not irnplement the snoop result outputs QSDONE and
`5301:).
`
`503
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`

`
`PCI System Architecture
`__,___.____...___.___
`L2 Cache
`The L2 cache controller is embedded within the ‘591 system controller. It is a
`-mapped, lookwide, buffered write-through cache. The L2 cache only
`memory. '_Ihe-DRAM.cc:ntroIler maybe pregrarrurted to recognize sub-ranges
`within the overall memory address range assigned to‘ system DRAM
`memory. when the processor inittatm a memory transaction targeting an ad.
`dress in any of these programmed sub-ranges, the transaction is passed to the
`PCI’bus and the debris not cachedinL1 orL2.
`The recommended L2 cache sizes are 256KB, 511KB and 1MB, but the L2
`d as any desired size. The limitation is the amount
`cache may be implements
`of tag SRAM supplied by the system designer. The tag seam (i.e., the -cache
`and can be of any size. Optionally, the L2.
`directory) is external to the ‘591
`cache may be parity-protectsd.
`The cache controller supports L2 cache line sizes of both 32 and 64bytes. A.d«
`ditional SRAM is necessary to support the larger line size. when the 64 byte
`ce