ChaE1:_er 2: Solutions, VESA and PCI
`
`
`
`G'nmponq:t:dcIig:\nHorflnePC2I -n. nnPCI-sp|:1fiq,not
`procumr-s'pa:lII:,
`Ih-allay isohun; durlae design hum
`...,_... m.dum_
`5upportfcrIqbin156l'C1'fin'IL~'
`.I\3|hnIflI'Ilyphll'GhuimpIImu1taIion:uppoI|s up-
`
`thIn.ldevicupu'PC‘lI:I.I
`pmucinuhlylmelecflicallnads, |u.11PCl clnviu: plchue
`m-Iy'Im|iIlauptoel§htIq:InhPUI1nncIionI.'IluPC|bus
`
`lng|flIIIyInppo:III1p|n32plIy!inlPCI&vlmpachg!A,fat
`mumzss uIfi1el’Qfu.|'I.I:IinwI -
`- Pclbus.
`
`
`_
`
`
`
`
`
`a -
`
`.
`
`JI
`
`.
`
`,
`
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`
`
`
`
`S11ppo:II132MhyhuaperaaouII1paIkIrIn:h-rmafor-bulb
`Ieadlndwrltllnnnfnsiilflbyhupnriaaclldpn-khan-
`6|-NIl‘GtmIsf=u.‘n:daI rnuufnp to
`ulunmldanldwlevahilomafidl-‘E-tzPC1ha:s
`
`
`
`wan.
`
`'lJ'a.'....
`
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` Ei;
`
`
`ppurlnflflbllinlflnhnallunspua-h-puzflii
`Illllflflli.-Hltlnfllflfillhmlllmellnfyllldixpllllinn
`
`
`busd.e\'i¢tsIhrbu5hFI2l|ndeItpanIlot|I:usb:lrlg1en.!nnd-
`
`
`diflm|,.IPCImunrunnc.uunuqatt!utn:id.san|n-
`oIII£rl’C1hmlnwu-inll'n|aulhl:rIrrh._
`
`
`
`
`
`AmHIuIim':EI_:rII0l'ClbnlclnIIRlpluwhi1eaJ1otl1ubIn
`:maurh1npnaa:sInuaIfl'iePClbur.11Ih:lIninnuula-
`fancy anulunuidthdnghlsnhllnfloa in bag ailm-
`
`
`
`Iignals_a1lows I.|'l'Iplll'l'|vII'I.lI|iI:m.u.'.|
`hncflonnlfdnrptwififlpmandnhnumflrfibm
`11I.i|'llin|"wiII|I9=
`E
`mm‘ufmemory.uomn,...am..u....-
`
` it
`
`Ei
`
`
`
`
`
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`
`Full Inna-ea spedficllion or me umsguuuun pgiilns
`
`neuauuy In tupparl automalic porlphnrll datedinn Ind
`urn '_:'_g___u__ r-:1-u
`
`5ol'lw|ndrivnsurlIiau:uIrI¢ctan:nndnetit1:lsIahaIdefl-
`union vim aolnmunicnbing with PCI device at in expu-
`sinnhul-orlaaunedmushi.
`
`
`
`i
`°""‘
`Eacplnsioncaadsize
`
`add-herds.
`
`Iltetpoclfiufinndefina-Hmaemrdahszlolwyshmund
`
`
`
`
`
`
`Page 56 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 56
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`Petitioners HTC & LG - Exhibit 1019, p. 56
`
`

`
`PCIsgcemArchitecture
` _
`1'‘!
`
`51$ ."Hr_"fn:_‘:.r {,-'
`CPU j,(n..:.' Bu? gg-p;
`Bus.
`
`i
`
`.._:....,__-__
`
`
`
`“
`
`
`
`
`Bus
`Marla
`
` Expansion Bus
`
`
`
`Figure 24- The per Bus
`
`
`
`Page 57 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 57
`
`Petitioners HTC & LG - Exhibit 1019, p. 57
`
`

`
` _
`
`. Chazter 2: Solutions, VESA and PCI
`
`_ Market Nlctna. for R6,! and_\!E$A_\lL_
`
`Mmyinflieixtdlahymeuaingflaixuyltalballawpmdictflleoutuonteaf
`this"huewar.’bul&|1nwiJ1notbeawhflosefiIualion.VLiaagaod.coat-
`afiective approochforlow-erldmachina that require fastdata tI'an3fercapa-
`bflityudfi1mesubsyslemntafimeir1ordertoadfievenooeptab1eoyetanpu-
`formanoe.Dneho&\emmpleadtynEfl1ePC1d1ipsehwhencompuedto_Ihe
`logic req1firodbyVL1.U,PCI-ba3adsyshemsa:enfi3l1flymoreexpu1aive.Bal-
`andng this added me! with PCI's superior perfiomuruze in eupporling bus
`concurrency, I afim and Inultlple Bun rnastem, FCI—bued me-
`chineawflldomirntefixemidandhigh-a1dnuchi:I9:mrinetrdd1ao.
`
`It ahouid benoIed,hawen_r.thartamad1inecanbedesignedwiIhuutany
`bridges.
`uornponents. including the prooeasorandmain memory, would
`interf&oedimct1ytufl1ePCIbus.DuemH1eredncflonmlo3ieyieldedbyfl1e
`deJe&onoiIhebridgelagic.tr&sPCInnd1hnewmddbevayp:ioe-mmpefifive
`varl|luVE:AVL-baaedmaohine.
`
`PCI Device
`
`The typim1PC'.ldE\"icec:ons'B|: oiammplelepefiphual 'ad.apbeI'¢I1capsulata:l
`ndfi1irLanICpedmgemh1tog:ItedmtoaPCla:panEiancard.Typiulexam«-
`pies would be unetwork, display or SCSI tdaplaer. During the initial period ah
`ter the introduction of the PCIspecifinlio11., many vendors chose to interface
`pro-existerxt. non-PC1coarLpJinntdevinestoI&:ePC1bua. '1'hiscanheem'1yac-
`oomplfluairlgpmgl-aumublelogicarreys (PLAs).Pigure2-5 illuslntesten
`PC!-compliant devices amcludoo thePCI bus onlhe system board. Itahuuld
`also be noted that each PCI-compliant ‘package (VLSI component or add-in
`card) may contain. up to eight PCI funcflons.
`
`Page 58 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 5 8
`
`Petitioners HTC & LG - Exhibit 1019, p. 58
`
`

`
`PCI 5 steni Arclfited-are
`
`'
`
`
`
`
`r-E-iii‘
` |||| 3‘ ,
`
`
`
`
`
`
`
`
`
`S'|'ubs
`
`Side bdnd
`Slncls
`
`Figure 2.5. PC} Device: Attached to the PCI Bus
`
`Specifications Book is Based On
`
`I11isbooki.sba5edontl1edocumenlsihdicatedintab1e2-3.
`
`Table 2-3. This Bmkis Based On
`
`PClLocs.1BusSeciflca1:I.on
`
`PCI BIOSS - cihcaiiun
`
`PCI-to-PCIBri ecificahon
`PCIS smmDesi Guide
`
`'34.
`
`Page 59 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 59
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`Petitioners HTC & LG - Exhibit 1019, p. 59
`
`

`
`
`
`Chagter 2: Solutions, VESA and PC]
`
`Obtaining POI Bus 5pecificatIon(s)
`
`.- The_PC_I bus .sp.ecifi.cafim.ve.rsim:_L 1.l1._1!~:aa.e1.ev:t=.lop.ed by Intel Corporation.
`The specificafim is now
`by a consortium of industry partners
`known as the PCI Special Interest Group (SIG). Mindshare, Inc. is a member
`of l:heSIG. The specifications are commercially available for purchase. The lat-
`est revision of the specification (as of this printing) is 1.1. For information re-
`garding the specifications and!or SIG membership, contact:
`
`.
`
`. - __
`
`PCI Spatial Interest Group
`PLO. Box 141070
`Portland, OR 97211
`Tel. (503) '79?-flu? Ilniermlionnll
`Fax (503) 234-6762
`[500] 453-5117? [in 11.5.}
`
`.
`
`Page 60 of 235
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`_ Petitioners HTC & LG — Exhibit 1019, p. 60
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`Petitioners HTC & LG - Exhibit 1019, p. 60
`
`

`
`
`
`Pmftfl
`
`
`
`Revision 2.1 Essentials
`
`Page 61 of 235
`
`
`“
`
`——————~——__.-_
`
`Petitioners HTC & LG — Exhibit 1019, p. 61
`
`Petitioners HTC & LG - Exhibit 1019, p. 61
`
`

`
`
`
`Chapter 3: Intro To PC! Bus Ogeratiqn
`
`to
`
`L ChiaptJer3'
`
`The Previous Chapter
`
`ThapteViouschapterin&oduoedtheLocalbusconcepgtheVESAVLbusand
`t1\ePCIbus.
`_
`
`In This chapter
`
`This chapter provides an i.ntrocluct'Lon to the PC! transfer mechanism, includ-
`ing a definition of the following basic concepts: burst lzramafezs, fne irlilziator,
`targeb, agents, single and multi-ftmcflon devices, the PCI bun élock, the ad-
`dress phase, claiming the transaction, the data phase, truuacfion completion
`andtherehnnoffitebus toiheidlestate.
`
`The Next chapter
`
`Unlike most buses, the PCI bus does not inootpou-ate teunlnation teaiatons at
`the physicalend oi thebus to absorb voltage changes and prevent the wave
`frontcausedtrythe voltageohangefrombeirigtetlectedtaackdownlimebus.
`Rather, PCI use-a refleeliom to advantage. The next chapter ptovides an intro-
`duction to reflected-wave switching.
`
`- B
`
`urst Transier
`
`Abinsttransfaisoneoonsisfingofasingieaddressphasefollowedbytwoor
`moredatapha5ea.'IhebI.Ismnster or|1yhastoarh§hntefcn'bueowM_t'fi|iporIe
`flmelhestartaddresamidtransacfimtypeareissueddmingtheaddress
`p1'1nse.The target devioelatdieethestaztaddras inhoan adclresaoountaea-aru:1
`is responsible for incrementing the addressframdalaphasetodataphase
`
`In the 486, EISA arldlvlicro Channel environments, the ability to pedomlbuxst
`transfers is the product of negotlalion between the bus master and the target
`device. If eithe: or both of them do not support burst mode transfers, the data
`
` -T‘
`'39
`
`Page 62 of 235
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`Petitioners HTC & LG - Exhibit 1019, p. 62
`
`

`
`PCI System Architecture
`
`—
`
`..
`
`pachetganmlylpeugrtsfeneduuljzhtgaseriesofsepautebmuamufiens
`lhebiiamutermustubihatefuramtetshipoffltehxstapecfonneachimb
`vidual transaction that
`the series. Altolherblts master may acquire
`bus nwneratflpafterfl\emashercnmp1etesa:lytransaeEonintttesefies.Ttas
`canseve:elyin1paettheh:n:maatex‘sdatathroughpuL
`
`MostPCIdatauana£ersareamomplisheduakLgburatu1nafera.MostPC[bus
`mastersandtargetcleviceaare desigmedtnsuppartburatmode.Itshouldbe
`r[otedthataFCItargetn-saybedaigrnedsndt fl'latitC3:I'lOI'l1]fha1'Idles.iugIe
`datapltaseharlsaefimnawttertabusnmsteratteutptsmperfmmabtamt
`uuuacuonfltemgethrmfiutesfiuhamacfimatflnemnpleflmuifitefint
`dataphase.Thisfomesthemasterto re-arbitrate forfltebustaattemptre
`sumptiano£t11eburstwit11t11.ene:<tdataitem.1‘t1etaxget terutinabeseaeh
`burst t-.1-ansfer afterfhefixat data. phase completes. This would 3-ield-very poor
`performanee. but may be the correct approach for 3 device that doesn't me-
`quite high throughput. Each bunt transfer cansisls of the following basic
`mmponents:
`
`Iheaddreasandtransfiertypeareoutputduringtheaddressphase.
`o
`o A data object (up to 32-bits in a 32-bit implementation or IE4-bits in 3. 64-bit
`implementation) may then be transferred duflng each subsequent data
`phase.
`
`-
`
`,
`
`Asmmingfitatneiflaerfiteififlatornmfitetargetdeviuehsertswaitstataah
`ead1dataphaae,adataobjectmaybetrmefenedmt therising-edgeofeach
`PCIc1ockcyc1E.AtaPCIbusc1ockE:equatcyotE33MHz.arra11sfer rateof
`132Mhytes/second may be achieved. A transfer rate of 26-filvflnytes/second
`maybe mdtievedina 64—bitin1pIementatioImrhenper£omIing64-bittransteta
`dufingeachdataphase.Afi6MHzPCIlmsimp1ementafimcanad:ieve264m
`524MbybesfsemmdIrmsferratesusing32or64—bitumafus.1}dsd1apterflr
`koduceafiteburstmedtaniam-naedinpufonnhtgh*amfasoverfitePC1h1&
`
`
`Inltiator, Target and Agents
`
`There aretwoparlic£pn|taineveryPCIbu:3HIInafienI:heinitiator andlhe
`target. The tnitiator,orbusmaster,is the devioethatinltiatesat:artsfer.'1'hE,3
`tennabus masher andirdtiator eanheused.inIarc]1a:1geab1y,butthePCI speci-
`fication strictly adhemesto the terminitiatnr.
`'
`
`
`
`P899 63 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 63
`
`Petitioners HTC & LG - Exhibit 1019, p. 63
`
`

`
`_
`
`Chapter 3: Intro To PC] Boa Ogation
`
`the
`The target, or slave, is the device currently eddreseedbyfite
`purpose ofperfoflrlinga data transfer. The temtstarget erLe!._ala_1.r_e can be used_
`interchangeably, butihe Pclspeciticitiorfstrictlyr adheres to the term target.
`
`' " * '
`
`'
`
`Al1PCIin£tiauorand!argetdevioesareom:1morflyreferredtoaePCl-
`compliantagents.
`
`
`single vs. Multl-Function Pcl Devices
`
`A PC! physical device package may take the‘ form a component integrated
`onto-lhesyatemboardorthefiorm o£aPC'.Iadd-incard. EachPCIpackage
`may incorporate firom one to eight separate
`is analogous to a
`mu1tH11ncIionoardfountIit|aI:yI5A.,BI5AorlvIicro Channelmachine. A
`packagecontainirigmefimcfioniarefenedtoasaaingle-fimcflmtffldevioe.
`wtfileapackage oontaining two or morePCIfI.mctionsiareferred to as a
`multi-funeliondevioe.
`
`- P
`
`OI Bus Clock
`
`Al1acfiflnaonihePCIbusare5ynduorfiaedtoihePCICLKsignaL'I1te£:e-
`quencyofthe Cllisignal maybe anywhere from OM!-Ie to 33MI-]z.."I'i:1erevi-
`sion 1.!) specificationstated fliatafldeuicamnstatipportoperltion {teen 16 to
`33MHz.. while recommending support for operation down to UMHZ. '.{he re-
`vision 2.: PCI .spe'd£icati9n indicates that ALL PC! devices MUST. support
`PCI operationwithin thaI'.'.IMHz to 3SMI-Ix tango. Support for operation down
`to (Ml-Iz provides low-power and static debug capability. The PC! CLK fire.-
`quetnqrmay be changed at any time and my be stopped (but only in the low
`state). Components integrated onto the ayehem board may opemte at a single
`frequent.-yaend mayrequire a poflcyofm Ereque.ncyd1ange.Devioes madd-
`in cards must support operation from El through .33M1-Iz. (because the card
`must operate in any platform that it maybe installed in).
`
`Thereviaimzlspedfleafion aleodefinuPC[bus operationatspeedsofup to
`66M]-12.. The chapter entitled “66M'l-Iz PC! In-Lpleznentatiom“ describes the op-
`erational charactefisfics of the 663MHz PCI bus, embedded devices and add-“in
`cards.
`
`A1lPCIbustrarnaadim1soomiatofanadd1esapi1ase£oflowedbyoneoruwre
`data phases. The exception is a transaction wiherein the initiator uses 64-bit
`addreeaingdeiiveredintwo addreasphIaes.Ana.ddre5sphaeeis onePC1
`
`*
`
`_ 4
`
`1
`
`
`
`Page 64 of 235
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`.
`Petitioners HTC & LG — Exhibit 1019, p. 64
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`Petitioners HTC & LG - Exhibit 1019, p. 64
`
`

`
`PCI System Architecture
`
`- CLK-in duration. Thenumher otdettphaeee depends unhew men_y_ date
`.tre1'tsfera are to take place duringthe everallhurst transfer. Each data phase '
`hesaminimmndu1afimofm1ePCICL.I<.Eachwsitsteteinsertedinadete
`phneeextendsitbyanedditi.0naIPCIClC.K.
`.
`
`' A
`
`ddress Phase
`
`As stated earlier, every PC! transaction (with the exce})ti.on of a transaction
`anmgfl-bltedd:eeshng}starhoHwlthaneddteesphaeeortePCIC11(pedod
`indtn'_a.tlon.Du1ingthe edclreesp!1aee,tl1eiIIi6etor idettlifiesthe tergettlevitze
`andd1etypeafuumecfimt.111etergetdevieeiside:1fifiedbydrtvi1|gas1afi
`address within its assigned range onto the PC! address/detabus. At the same
`time,Iheittitiat:uridenHfieathetypea£ttansectienbydrivir1gttte commend
`type onto the PCI Commend/Byte Enable bus. The
`asserts the
`PRAME#slgmltomdieansthepmeenoeo£evafidstartadd:essanduensec-
`fientypeonthehusfiincedtehdfietneunlypmaenteflmstsrtaddressforune
`PCIclockcy‘C1e.itistheresponsibl1ityo£eve:}'}'CItergetdevieetolatehthe
`address so thatit may stlbsequentlybe decoded.
`
`Bydecodingtheeddteeslatdtedframflweddressbusertdflneeemmandtype
`letchedftomthecmmnand/Byte Enable bus,e_terget devleeeendetexmineit
`itisbeingadd1esaedandthetypeofh‘amacfiminpmgees&It'aimpartmlm
`note that the initiator only supplies a start addteea to the target (during the
`addxaephase).Uponeunp1eflunoffl1eaddteesphese.theedd1eesfdetabus
`lstltemnsedtotransferdeteineechuftheclatepheaeeltisthe responsibility
`ofthetargettoletchthestartaddressandtoautn-incremexttittepointtnflze
`nextgroupof!ocationsdu1ingeacl1suheequentdata transfer.
`
`
`claiming the Transaction
`
`When a PCI target detexmines that it is the target of a transaction, it must
`claim the trmsactiun by asserting DEVSEI.# (device 5e1ect).I£ the initiator‘
`doesn't sample DEVSEHI asserted within a predetermined amount of time, it
`’I.-
`eborts the transaction.
`
`! D
`
`ata Phase(s)
`
`Thedataphesecfauansactimisfisepeliodduxingwhidtadataubjecl.
`transferred between me
`the target. The ntxlrlberofdatabyfl-'-9.
`beh‘ansfer1edcIurh1gedatephaseied.eteuninedbytl1enumberofC
`
`
`
`Page 65 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 65
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`Petitioners HTC & LG - Exhibit 1019, p. 65
`
`

`
`Chapter 3:I1'1t1-n To PCI Bus Operation p
`
`mmd/Byte Enable signals that are assumed by the initiator timing the data
`Phase‘...
`.
`.
`..
`.
`.
`_
`_..- .-
`.
`_
`.
`.
`
`Buththeintttatnr and the targetmust indicate that Iheyarereadytn complete
`adataphase,urtheclataphaseisextendedbyawaitstatemePC1CLKpe-
`riodfi1durafimL1TtePCIbusdefinareadysig|1alIhesusadbybothEteini~
`tiator {IltDY§}and1he-target (‘I'RD‘t‘ll}forthispurpoae-
`
`
`Transaction Duration
`
`transfer with the
`The initiator identifies the overall duxatian‘ of a burst
`FRAMBH signal FRAMEtlris amerted at the start of the address phase and-re
`mains asserted until the initiator is ready (asserts lIRDY#) to complete the final
`data phase.
`
`' T
`
`ransaction completion and Return of Bus to Idle state
`
`The inittatorindicates that the last data t1'anafer(ofabursttntnsfe:)isinprog-
`reesbydeasaerttngFRAME#andassertingIRD'Ytl. ‘whenthelestdatatransier
`has_bemcumpleted, theinitiatur netI.|msthePC'.lbus to the idle statebyd¢as-
`setting its ready line (lIRDY#).
`
`Ifanodterbusmasterhadprevioualybemgrantedmvnerslflpofthebusby
`thePClbu.aarbiter andwete waiting for the current irdfiatortosunextder the
`bus, it can detect that the bus has returned to the idle state by detecting
`FRA'MIB#andIRDY#bothdeasserte_d.
`'
`
`“Green” Machine
`
`In keeping with the goal of low power consumption, the specification calls for
`low-«power, CMOS output drivers and reneivers to be used by PCI devices.
`
`describes the reflected-wave switching used in the PCI bus
`The next
`environment to permit low-power, CM05 drivers to succaafully drive the
`
`lftheaddress/databus gnals atladiedto I.’neCMOSinput receivezsare
`permitted to float. (around the switching regiam-of input butters] for extended
`periods of time, the receiver inputs would oscillate and draw excessive cur-
`mnt. To prevent this fmmhapp-wing, it is a rule in PC! that the address/data
`
`43
`
`Page 66 of 235
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`
`Petitioners HTC & LG - Exhibit 1019, p. 66
`
`

`
`PCI Szstem Architecture
`
`busmu3tnotbepermith2dmflont£urextmdedpe1iodsoftime.Sh:ce&Leb1n
`isnamlally drlvenmoet ofthe time, it maybe amumed that the pre-c'h.argecl
`buswiflretainitsstatewhflenotbeingdrlven for briefperiodaoftimeduring
`tui'naro1IEhd'c-ycles
`areflescdhed in the chapherenlitlead ' " " *
`"'I'heReadandWriheTram£er."
`.
`
`‘
`
`'
`
`Theaection enfit1ed"BusPa1kingf’i:1thzchap1:eranbnsa:bihraIiond=ascribes
`tlaemedianismutilizedtopreventtlte address/databmh-omfloat1ng'when
`the bus is idle. The duptar entitled ”'I'.he Read and Write Transfer” describes-
`Ihe mecham'smuli1ized. dining data phases with wait states. ‘flue d1.apterentt-
`tled “lheel-BitExterIsinn”deaa-ihesthenuedxanismufilized to keg: then}:-
`perszbitsaflheaddreasldalabm from floattngwhen they aré.natin1.1se
`{d1'::inga32-bit transfer}.
`
`P398 57 of 235
`
`Petitioners HTC & LG — Exhibit 1019, p. 67
`
`Petitioners HTC & LG - Exhibit 1019, p. 67
`
`

`
`Chapter 5: The Functional Signal Groups
`
`The Previous chapter
`
`The previous chapter provided an introduction to refleeted-wave switching.
`
`This chapter
`
`This chapter divides the PCI bus signals into functional -groups and describes
`the function of each signal
`
`The Next chapter
`
`Whena Pclbusmasterrequiresthe use oftheI-‘Clbustoperfonne data
`transfer, it must request the use of the bus from the PCI bus arbiter. The next
`chapter provides a detailed discussion of the PCI bus arbitration ti.u1.i.ng. The
`PC! specification defina the ‘timing of the request and grant handshsking, but
`not the procedure used to deterniine the winner of a competition. The algo-
`rithm usedby a system's PCI'bus arbiter to decide which of the requesting,-bus
`masters will be granted use of the PCI bus is system-specific and outside the
`scope of the specilicafion.
`
`
`Introduction
`
`This chapter introduces the 'signa.l_s utilized to interface a PCI~eomplimt d.e~
`vise to the PCI bus. Figures 5-1 and 5-2 illustrate the required and optional
`signals for master and target PCI devices, respectively. A PC} device that can
`act as the initiator or target of a transaction would obviously have to incorpo-
`rate both initiator and target-related signals. In actuality, there is no such
`thingasa devioetltatispunelyabusmasterandneveratarget Ataminir
`mum, a device must act as the target of configuration reads and writes.
`
`Each of the signal groupings are described in the following sections. It should
`benoted that some of the optional signals are not optional for certain types of
`
`I
`
`.
`
`53
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`Petitioners HTC & LG - Exhibit 1019, p. 68
`
`

`
`PCI System Architecture
`
`PCI agents. The sections that follciw idenfify the circumstances where signals
`musthe implemented.
`
`_
`
`Required
`flsnals
`
`n
`
`A DIS’ 1:0}
`
`Acldaess/Data
`and Command
`
`'
`
`—
`
`Figure 5-1. PC!-Complimt Master Device Signals
`
`
`
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`Petitioners HTC & LG - Exhibit 1019, p. 69
`
`

`
`Chapter 5: The Functional Sigal Gm-uEs
`
`I Q
`
`I
`
`SBO#
`
`xsE+:{7:41 I
`PAR64
`Rmfifl
`ACK64#
`[053
`|
`|-Lsi=im Clbckcontml
`snows
`mi
`1'01
`
`.
`
`693“
`E‘°°"“"°"
`
`‘Atomic
`
`.TR51‘#
`
`TCK
`
`‘”°
`TMS
`]NTA#
`mmmm
`
`rm
`%
`mm
`Rem“?
`
`Figure 5-2. PC!-Cnmphani Target Device Sfgnalé
`
`
`55
`
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`
`Petitioners HTC & LG - Exhibit 1019, p. 70
`
`

`
`PCI Sgtem Architecture
`
`
`. 9f5'_°‘_"-"'7'.-°!'9_’_‘..a'o:"
`
`
`PCI clock signal (CLK)
`
`'I‘heCI..I<aigna1isaninput’roaJ1c1evioa rasirii;1gon&\ePCIlbus.Itprovides
`um.-ingtoun transactions, InchJ.dJng"bus arbitration. AJ1 inputs to PCI devices
`amaunpledmfl\erbk1ged3eo£&1eClK§gnaL'lhestateo£aflinputo1gna1s
`areclon't'-careatall ofl1ertimes.Al1PCIt1nLi|1gpa:ImeteL-aarespecifiedwixh
`reopectbofheriaing‘-adgeo£fl1eCLK5igrIal.
`
`AJ1acfionaonfl1ePCIbusaIeaync}umimdtufl1ePCIC1.KsignaL'Ihefie-
`quencyo£fl1eCLKoig11alnuybeonywherefromDMHzto33lwfl-IL1he:evi-
`sion 1.0PC{specifica1i.on stated tlutalldevices must support operation from
`16to33-MI-Izartditstronglyrecommendedsupport foroperaliondownto
`OM‘!-Izfurstatic debugantlltlwpoweroperaliom. The revision 1.xPC‘.'Is1:edfl-
`cation indicates th_at ALL PCI devices (with one exception noted below)
`MUSTsopportPCI operation within the UM1-I2 to 33MHz.ra:'I.ge.
`
`'Ihednck£1'equencymaybe changed ataimyfimse aalangas:
`
`"I‘hem.in.lmum dockhlghandlowtimeoarenot violated.
`There are nobusrequests outstanding.
`Lflclitisnotasaerted.
`
`The clock may onlybe stopped in 1 low state (to conserve power].
`
`Asmenozpfloaxoomponausdeaigned who integrotedontothe sja-otemhoaxd
`maybe deoignedtooperateatafixedfrequency(ofupto33MI-Iz)andmay
`only operate at that frequency.
`
`roradismssionatesivu-Izbusope:aann,reterm:rechapmmoued«‘
`"66M1-Iz PCI Implentetitafion."
`'
`
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`Petitioners HTC & LG - Exhibit 1019, p. 71
`
`

`
`Chapter 5: The Functional Signal 4GrouE
`
`
`
`’ CLI(HUN# Signal
`
`General
`
`‘
`
`The CLKRUN# signal is optional and is defined for the mobile (1-Ev Portable)
`envirmiment.It'BnotavaflahlsomfltePCIadd-inaxmectorfillfissecfion
`providesanintroductlonto tl1issubject.Amone detailed desaziptimlofthe
`mobile environmeni and the CLKI{UN# signal’: role can be fiound in the
`document entitled PC! Mobile Design Guide {available from the SIG).
`
`AlEhoughtheP[1spa':'.ficaIianstates that tlteclockmaylaestoppedorltsfrea
`queasy chan3ed,:itd.oesnot define a method for g when to stop (or
`slow down} the clock. or a method for determirrlng when tonestsrttl-Le clock.
`
`A portable system includes: oentralre-.-Iource that includes the PCIc‘loclc gen-
`eration logic. With respect to the clock generation logic, the CLKRUN# signal
`is a sustained tri-state input/output
`The clock ge:rLersl:lon logic keeps
`CLKRUN#asserl:ed WhetItl'Leclocl:'m111rLningnonnnll}r.DIn'ingpe1ioI.’:s when
`the cloclchas beenstopped (oralowecl), the clockgenerationlogicmonitots
`CLICRUN# to recognize requests from master and target devices for 9. change
`tobemadeinthestateoffl1ePCIdocl£signaLIhecIockcmmotbe5toppedif
`thahusisnotldle.Be£oteitstops(ora;lows down)tl'neclockfiequenc}v, the
`clockgenue1'ationlogi.cdeassert8CLI(RU§hlflrforonec1ock loinformPC[de-
`vices that the clock is about to stopped (of slowed). Aitet driving CLKRT.TN#
`high (deasserbecl) for one clock. the clock generation logic tri-states its
`C1KRl.IN#oulputd1ivet.11wkeq)er:esistoronCLKRUN#fl|masmmesre-
`aponsibility for maintaining the deasserted stalse of CLI<RUN# during the pe-
`riod in which the clock is stopped (on; slowed).
`‘
`'
`
`medockmnunuas bonxoltrlcharlgedfmnxhitdmumoffiatrdocksafterflm
`clock generation logic deasserts CLl<IlUN#. Afhe: deasserlion of Cl..I<RUN#,
`theclock generation logic must monitor CLKRUNIF for two possible cases:
`
`1. After the clockhas been stopped (or slowed}, in master (or multiple mas»
`tersjmay reqqire clockrestartirt ordertorequerstuse ofthelma. Prior to
`issuing the bus request, the master{s)n1ust first request clock tutu-t. This
`is accomplished by assertion of CLlCRUN#. When the clock generation
`logicdehecls the assertionofC1.K'RUN#bymotl1e:- party, itturns onto:
`apeedsup) the clockandtums onitsCLKRUN-fioutput driver to assert
`CLKRUN#. What: the master desects that CLI<RUN# has been asserted for
`
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`
`Petitioners HTC & LG - Exhibit 1019, p. 72
`
`

`
`PCI Szstem Architecture
`
`'
`
`two ofthePC1CLKsigr1al,themastermay thentti-state its
`CLIGUN#output driver.
`2. When the dock genera_ti0rl logic has deasserted CT..KRUl‘_~l#, indicating its
`'
`irtteltiiun to stop (or slow) the clock, the clock must continue to £1,111 for a
`of four clocks. During this period of time, a target (or masmr)
`that requires continued clock operation (e.g., in order to perform internal
`houselcseping after the completion of a trellsaction), may reassert
`CI.I<ZRUN# for two PCI clock cycles to request continued generation of
`CLK. When the clock generation logic samples CLKRUN# reasserted, it
`continues to generate the clock (rather than stopping it or slowing it
`down). The specification doesrft define the period of time that the clock
`will oontinue to run after a request for eonlinues,-1_ operation. The author in—
`terprets this as implying that-the period is system desigrl-specific.
`
`
`Reset Signal (FtST#}
`
`When asserted. the reset -signal forces all PCI configuration registers, master
`and target state machines and output drivers to an initialized state. RS'i‘# may
`be asserted or deasserted a5ym:hrDno1.1sly to the PCI CLK edge. T.he assertion
`of R513? also
`other, device-.specifie functions, but this sutgiect is be-
`yond the soope of the PCI specification. All PC! output signals must be driven
`to theirbencign-states. In general. thismeanstheymustbeui-stated. Excep- _
`tions are:
`
`0
`
`SERRH is floated.
`
`If'5BO# and SDONE eannotbe tri-stated, they will be driven low.
`n
`a. To prevent theAD bus, the CfBEbus and the PAR signals from floating
`during reset, they may be driven low by a central resource during reset.
`
`Refer to the chapter entitled “The 64-Bit PCI Extension" for a discussion of the
`I-lEQ64# signals behavior during reset.
`
`
`Addressmata Bus
`
`The PCI bus uses a time-multiplexed address/data bus. During the adore
`phase of a transaction:
`
`In The AD ‘bus, Alj[31:fl], carries the start address. The resolution of this
`address is on a doubleworcl boundary (address divisible by four) during it
`“memory or a configuration trarlsaclion, or a
`address d.1.11'iIlE
`
`
`
`53
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`Petitioners HTC & LG - Exhibit 1019, p. 73
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`

`
`Chapter 5: The Functional Signal Groups
`
`o
`
`u
`
`an IIO read or write lzransaction. Additional information on mernory and
`I/O addressing can be found in the chapter erltifled “The Read and Write
`Traiisfer." Additional information on configuration addressing can be
`foundiripartslllartdlifoftltisbook.
`The Command or Byte Enable bus, C!BEt![3:0], defines the type of trans-.
`action. The chapter entitled "The Commands" defines the transaction
`i3’PE5-
`-
`'
`The Parity signal", PAR, is driven by the initiator one clock after eorn'_pIe-
`tion of the address phase and completion of each data phase of write
`transactions. It is driven by the eurr_entl'y-addressed" target one clock after
`the eornpletiorl of each data, phase of read transactions. One clock after
`eompletion of the address phase, the initiator drives PAR either high or
`low to ensure even parity across the address bus, AD[31.-O]. and the four
`Commarndjflyte Enable lines, C.°"BB#[3:0]. Refer to the chapter entified
`"Error Detection and Handling” for a discussion of parity.
`
`During cod! data phase:
`
`a
`
`e Thedata bus, AD[51:lJ], is driven by the initiator (during a write] or the
`currently-addressed target (duringpa read).
`PAR. is driven by either the initlator (during a write) or the currently»
`addressed target (during a read) one clock after completion of the data
`phase and ensures even parity across AD[31:0] and C/BE#[3_:D]. If all four
`data paths are not being used during a data phase, the agent driving the
`data bus (the master duringa write or the target during a read) must en-
`sure that valid data is being driven onto all data paths (including those
`not being used to transfer data]. This is necessary because PAR must re-
`flect even parity across the entire AD and C/BE‘ buea."
`to
`L The Commmd/Byte Enable bus, C!BE#[3I0], is driven by the
`indicate the bytes to be transferred
`the currently-addressed dou-
`bleworcl and the data paths to be used to transfer the data. Table 5-1 indi-
`cates the rnapping of the byte enable signals to the data paths and to the
`locations
`the ctI.trentl'y~acldressed doubleworcl. Table 5-2 defines
`the interpretation of the byte enable signals during each data phase. Any
`combirlation of byte enables is considered valid and the byte enables may
`change from data phaseto data
`
`Page 74 of 235
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`Petitioners HTC & LG - Exhibit 1019, p. 74
`
`

`
`I’.CI Sfitem Architecture
`
`_
`
`Table 5!. Byte Enable Mapping To Date Paths and locations Within the
`Current —Addresssd' Doubleword
`
`/BE-'.':3# "
`
`path
`addressed doubleword.
`
`"uh location in the cuIi.'ently-
`--
`
`
`
`C/BE2-if
`
`C/BE1#
`
`C/BEO#
`
`Data path 2, AD[23:1fi], and the third location in the currently-
`addressed doubleword.
`
`Data path 1,_AD[15:B], and the second lotion in the eu1'rentIy-
`addresseddoublewomd.
`
`Data path 0, AD[7:D], and the first
`addressed doubleword. -
`
`location in the cu:n:ently-
`
`bytes within the currently-addressed dou-
`' ; allfour-data the.
`
`The initiator intends to irarlsfer the upper
`three bytes within the currently-sddxessed
`doublewnrd using the upper three data
`oths.
`
`Theinitiatorintendstotransferttteupper.
`twobytes andthefiIstl;ytewithinthecuI:-
`rentiy-addressed doubleword using the
`upper two data paths and the first data
`--:th.
`
`'
`
`The iniiiator intends to transfer the upper
`two bytes within the currently-addressed
`doubleword using the upper
`two data
`atha.
`,
`-
`
`The initiator intends to transfer the upper
`byte and file lower two byta within the
`unrenfly-addrased doubleword using the
`upper data path and the lower two data
`aths.
`
`60
`
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`Petitioners HTC & LG - Exhibit 1019, p. 75
`
`

`
`Cha ter 5: The Functional Signal Grou s
`
`‘
`
`'"
`
`me e amfel-11e
`and
`byte. within the cur;er_tI1y_-
`addressed doublewoittusirig the second
`nths.
`
`'1_'t:einitiatorirttencistoiIattsfer1he_iirstamt
`the fourth bytm within the currently-
`eddreased dqubieword using the first and
`
`'
`
`iritettdstotnnaferfiteupper
`The
`byte within the etmartly-addressed dou-
`
`three byte.s_within the currently-addressed
`doubleworcl using the lower three data
`
`two bytm within the currently-addressed
`doubleword using the middle two data
`
`Theinitintorittte:tdstoharts£erth¢.firstand
`third bytes within the cuxrerttly-addressed
`dnuhleword using the first and the third
`v the.
`
`'I11e"'tor'intendstot1'at1e£ertheti1h-d
`
`byte within the currently-add.-tmed dou-
`blewnrd us‘
`-_ the third data ath.
`The htitiatctr intends to transfer the lower
`
`two bytes within the currently-addressed
`doubleword using the lower
`two data
`atha.
`The tnitiator intends to transfer the second
`
`byte within the currently-addressed don-
`blewordusin the second data nth.
`The Initiator intends in transfer the first.
`
`'
`
`currerrtly-addressed dou-
`
`
`
`61
`
`Page 3'6 of 235
`
`-
`
`-
`
`-
`
`—
`
`____.___,_ _
`
`Petitionerg I-_I_TC _& LG — Exhibit 1019, p. 76
`
`Petitioners HTC & LG - Exhibit 1019, p. 76
`
`

`
`PCI 5 tem Architecture
`
` o£thefou1byteewithinthecurxentIy-
`
`. addressed do1.;b]e_wot_‘d mdwfll not use my
`aflialhisishmdldate haste.
`
`Preventing Excessive current Drain
`
`to fleet fai-lung periods.
`If Hie iapul:sfoC.MOS input reeei-were are
`fi1emoeiverstmdto0sdflateenddnwexceeeivecu:rent.h1¢rdertopr¢vmt
`thispheno=mez1aarIdpreserveIheg:eenaatureefIhePCIlbus. sevetalrules
`are applied:
`
`at Whenthebusisidle nndnulmsmastera arerequeating awnerehip,either
`Ihebusaxbiteroramasterflxathnsthebtnpaflcedmiitmusterlahleits
`AD, CIBE and PAR output drivers and drive a stable pattern onto these
`si5:na1]inee.'I'h1's issueis discussed in the chapter emitted ‘PC! Bus Arhi.
`u-aficm” under the heading “Bus Parking.‘
`mu3tdrivenata-
`.Dun'ng'n data phueinawrilte I1-anseclian.
`blepattem enI:otheAD.bua when itisnotyetready to deliver thenextset
`of data bytes. ‘This subject is covered In the chapter entitled "me Read
`and Write 'I'ranefers.’
`
`Dm'ingIdataphaaeinameadu'amaction,thetargetmustdriveaatabJe
`paliem mite the AD bus when it is not yet ready to deliver the nex_t set of
`data bytes. This subject is caveled in the chapter -enlifled "The Read and
`Write Transfers.‘
`
`A 64-bit cam’. phllgged into a 32-bit expansion slot must keep its AD[I53:32],
`CfBE#[?:4] and PAR64 input receivers from floating. This eutfiecr is eav-
`ered in the chaptere:1titlecl”'I'he 64-bit PCI Extension.’
`
`Page ?7 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 77
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`Petitioners HTC & LG - Exhibit 1019, p. 77
`
`

`
`a.
`
`
`
`Chapter 5: The _Functional Siflal Gruugs
`
`Transaction control signals
`
`"I‘abie 5-Bvplrh“ea a-brief." -desert"lptionl of sigttal taaedltol ooriIro1aPCi
`
`‘
`
`
`
`cecontrofs Is
`
`
`
`
`
`
`
`Cycle Frame is driven by line current initiator and
`indicates the -start (when it's first asserted} and du-
`ration (the duration of its amertion) of :1 names-
`tion. In order to determine that bus ownership has
`been acquired, the master must sample I_?R.AME#
`
`andIRl_3Y#b-olhdeassertedonflaesame rising-edge
`
`ofthe PCICLK.signa1.A transactianmajrcortaiat of
`
`one or more data transfers between the curnent ini-
`tiator and the currerrtljr-addressed target. FR.AME#
`
`is deaaeerted when the initiator is ready to com-
`
`lete the final data hase.
`
`
`
`
`Target Ready is driven by the currenliy-addressed
`
`.target.ItisaseertecIwhertIhetar5etisreadyto
`complete the current data phase (data transter). ‘A
`data phase is completed when the target is assert-
`ing TRDY# and the initiator is"
`lRDY# at
`
`the rising-edge of the‘CL1( signal. During a read.
`
`'I‘RI1_Y# asserted indicates that the target is
`valid daIaontoliIedatabtas.Durirtgawrite,
`'l'RDY# asserted irtdicates that the target is ready to
`accept data from the master. Wait atates are in-
`sertedinthecurrentdataphase1mfi1both'.!'Dl{Y#
`
`artdIRDY#are :
`-
`I u asserted.
`
`
`
`
`
`
`Initiator Ready is driven by t