it
`‘
`
`F
`
`i
`5
`:
`
`I i
`
`I
`
`-
`
`Stop
`Rewind
`Fast Forward
`Fast Reverse
`Random Seek
`
`(by playing only I frames)
`(bf Playing on I frames)
`
`The player optionally allows the user to odntrol the deooding of various frame types to provide a scalable perfortnanee knob
`‘ by skipping the decoding ofB frames.
`'
`
`Following is a listing of the API supported by we decoder:
`
`1)
`2)
`
`3)
`-l)
`5)
`5)
`
`Mpgpeclnfo
`MpgDecSlart
`
`MpgDecE.nd
`Mpg.Der:I-‘tame
`Mpgseekframe
`Mpgllewind
`
`This API allows for random seeking. so that the player can implement fast forward, reverse play type of operation, For
`bitstrearns oontaining only I Frames. this is a relatively simple operation. For bitstreams containing I. P and 3 frames Ll'|e
`Mpgseekl-'1-arne operation becomes a little complicated sinoe we cartrtot decode P or B frames without decoding the
`reference frames on which they are dependent. We overcame this problem by implementing the Mpgseekfrarne function to
`always find the nearest 1 frame in the direction of the seek.
`
`1.9" REFERENCES
`
`[1]
`
`[2]
`
`[3]
`
`[4]
`
`Patel. Ketan, et. a.l., "Petforrnanoe of a Sofiware NEPEG Video Decoder‘, Proceedings of the ACM Multimedia
`conference, S993.
`v
`
`Lllicttney, EL, Digital Hamming, MIT Press, Carnrnbridge. Mass. 198?.
`
`“Coded Representation of Picture, Audio and Multimediafl-Iypermedia Infonrtation’, Committee Draft of Standard
`ISOIIEC 11172, December 61991.
`
`"MicrosnfiWindows3.1SDK:ProgrammersRef.VolI.-Oi-erview",MicrosoftPress.1993.
`
`Q
`
`243159;: vol. zrsr
`
`I
`
`Petitioners HTC & LG — Exhibit 1002,
`
`Petitioners HTC & LG - Exhibit 1002, p. 141
`
`

`
`
`
`
`Highly Integrated Controller
`Eases MPEG-1 Adoption
`
`PRODUCT INNOVATION
`
`MPEG-1 Decoder
`
`Lowers The Cost
`
`Ofaldding VideoAnd
`Audio To P03.
`
`DAVE Bunsn
`
`he drive to add multi-
`media capabilities to
`the
`personal
`com-
`puter, either by ofi‘er-
`ing add-in cards or by
`building the capabil-
`ity directly on the motherboard, is
`' forcing card and chip suppliers to find
`new ways to reduce costs. Individual
`add-in MPEG-1 decoder cards, al-
`though reasonable at several hundred
`dollars, must have their costs cut in
`half. The aim is to trim the user’s cost
`ofaddingin MPEG-1 decodingto $100
`for an off-the—sl1e1l'card.. and even less
`if the system nnanufacturer is to in-
`
`
`
`‘
`
`clude the capability as part of the base
`feature set of the PC.
`With that in mind, designers at Cir-
`rus Logic studied system partitioning
`issues and came up with s three-chip
`solution that trims the cost of a full
`MPEG-1 subsystem to less than $50 in
`components (Fig. 1). The three chips
`include
`the newly-designed CL-
`GD5520 MPEG-1 video decoder chip,
`the already available CS-£921 audio
`decoder. and a commodity, 256-kword
`by 16-bit DRAM. The DRAM buffer
`can be expanded by adding a second
`2561-: by 16 DRAM. The larger bufier
`improves the quality of the displayed
`video and allows the subsystem to
`handle larger audio:‘v'ideo streams.
`With the three chips, designers can
`build systems that decade full-motion
`MPEG video from a variety of video
`sources. That includes CDs, MPEG-1
`CD-i movies, D05 0311-)
`{Open
`MPEG consortium} compatible titles.
`and Microsoft Windows MPEG MCI i
`standard video.
`Designed from the ground up to of-
`fer the simplest intelface in the PC 1
`environment.
`the
`CD-GL552D's ,'
`MPEG-1 video decompressor is based
`on the MPEG-1 core technology li- i
`caused from CompCore Inc. The core I
`is surrounded with all the fimctions it
`needs to communicate with the rest of
`the system at data rates of 80
`Mpixelsfs off the video port, and at up
`to 132 Mbytesfs on the host-bus inter-
`face. Unlike several other highly inte-
`grated MPEG-1 chips that incorpo-
`rate the audio playbnck channel on the
`chip, designers at (.‘i.n-us Logic de-
`cided to keep the function off the chip.
`That’s because the economics of inte-
`grating the sound onto the video de-
`coder chip shows that the all-in-one I
`approach doesn'tresl1y lower the cost |
`I of materials.
`The decompression chip also in- i
`eludes both PCI and ISA host-bus in-
`terihces (including PCI bus ma.ste1-
`
`
`
`
`
`1.GAREFULO0NSIDERA'I'IONmwu:n
`parddnninghasxunltadhahtghlydnegztulflrfifl-ldewdu
`deielooedhytilrruslaglelhacl-GD5530.'lbahnalit§ra3nn:
`oefigI,Iaacl:tphclodcsviIl:odaonI1Itwoulo§c,ahost-system
`tnmrneetnBAP(:lbnes,DltAIlmtrdlngtc,sguounpu:tng
`uunoolasdaottiolrloteonindiioaizntlonhgleh-old-{canned
`ootpotponplwidesntmhsdnnoedibsmomutectortlltlifi).
`smahdfumemnmrhmkawanwfltuytfipm
`enhaneedtmrruoetoru-usfierringvideolnnas.
`ELEGTRDNID lIBflIG_N.~“i\UflU3'l.' 31» 1995
`
`
`
`
`
`Petitioners HTC & LG — Exhibit 1002,
`
`Petitioners HTC & LG - Exhibit 1002, p. 142
`
`

`
`
`
`Low Profile .2" ht. ‘
`
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`
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`andaaadioconiporngats. Referencede
`MIPEG-lsyahem-layerhitah'enm.F‘ar
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`aignlciuareavanabiesoaaazaessgn.
`t.heaudioeha.nne1,thechipde]ivera
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`Odialho D00-431-1084
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`
`
`
`
`Page 143 of 280
`
`Petitioners HTC & LG — Exhibit 1002,
`
`Petitioners HTC & LG - Exhibit 1002, p. 143
`
`

`
`Wmnmnm an @
`
`Juan: 21, _I995 Volume 4:, Number If
`COVER STORY
`
`
`
`
`lflodulor Dc-D: Converter Sepcls Power llensily Soorin p. 59
`I
`A 500-“? module with a 90 Wlin. power density shrinks fi'on$-end supp yes.
`FERTURES
`
`
`
`
`
`
`
`
`
`E
`uilpiinulflnouliu
`‘”shl:.nI-'n.fl|IIrqIad'n:d:|I
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`pa ur_aoa. Hg-g. ;2n1|39o-aoao.. ans‘--Iumll
`BE
`ILBCTIONIG DBSIGNIAUGIJBT 21. 1995
`
`
`
` Page 144 of 280
`
`Petitioners HTC & LG — Exhibit 1002,
`
`'
`
`I
`
`ll{lIII|.OG'l' flfi
`
`ModIinesT|Iot|.lsleeBe11erI'|uIIC|Ii|:lrenp.53
`Speak-wcagvtifiontechndagyieoflflhedmwkrgbmrtimsdwmingtayowhome.
`
`Grip-Stole Potkoges Bridge The Gap Between lore Die And BGAs p. 65
`
`packaging techniques could be the ticket to solving the known-good-die dilemma.
`
`A Designer’: Guide To Real-Thne Operating Systems p. 75
`Real-time :93: span. a wide range of kernel sizes, twget processors, and licensing fees.
`me
`A Selection Methodology For EDA Tools p. 81
`eke
`
`-
`
`Highly Inlegroied Controller Eases HPEG-I Adoption p. 141
`
`
`
`
`
`
`
`Petitioners HTC & LG - Exhibit 1002, p. 144
`
`

`
`ELEIITIIIINII} DESIGN
`
`Alan! 1!, 19.95 Volume 93, Number 1?’
`DEPARTMENTS
`
`lflhntsfigohalkdrollicileslgn..........
`Cmcpuxcrstorawtubejbrbimry-digimlgednns;
`Wivuusadwprfizcfifechmubguarmihdaudaatoamb
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`Shldgitfdfigusgfihcbiujiberfim ....... “£5
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`Smnlflifiananoniwfilhmctm-ROE........... "8
`Lsflsldfflfiflaswarflproducts............... .; .... ..:8
`
`Upcoming Meetings.......... ..30,32,80,1-I4
`
`Tedmologyldvunces ........................ ..37
`Imprnoedbaaamvmmuagememviasqfhmesistmhy
`wiangursgstnnuytimu ....................... .. 89'
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`Qabrswuamhwu ........................... .. GIK
`£§uct!Komcr................................... .. 6-iL
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`Laflawfiumhudon ............................. .. 6&8
`Eurallhwh ..................................... .. 6'4!’
`mm ........................................ new
`HatPGhuduch................................. .. 6&3
`............ ..fl.DD
`
`99
`...............
`Ideas For Doslgl .........
`_Low-mupmiaiannbennmaw .................... "99
`Boundadpulsadiscrimialalor .................... .. 100
`Low-diuarfionsgrhauoaciflalor ................. .. 100
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`mwbefliflufirflavagz ..................... .. 10!
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`Nmsfigtas ..................................... ..
`I15
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`Dasfgniugamulfipofiflswfaua ................... .. 185
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`Patnflelfiliceyicldslfiuearspudiumvasa.......
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`
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`compdadcode .................................. .. -B
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`proaausiag ..................................... .. «I8
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`I46
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`Analog ......................................... .. H6
`Sqflamn........................................ ..
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`ELECTRONIC DBSIGNIAUBIJST 31. 1995
`
`I
`
`Page 145 of 280
`
`Petitioners HTC & LG — Exhibit 1002,
`
`Petitioners HTC & LG - Exhibit 1002, p. 145
`
`

`
`FA17.1:AnIIPEG-1AucIoNIduoDoeoc_IarnlIt|BcII-Lanolll
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`Page 146 of 280
`
`Petitioners HTC & LG — Exhibit 1002, n
`
`Petitioners HTC & LG - Exhibit 1002, p. 146
`
`

`
`text color
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`_
`P"eiitioners"H”'l“C & LG — Exhibit 1002,
`
`Petitioners HTC & LG - Exhibit 1002, p. 147
`
`

`
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`
`Page 148 of 280
`
`Petitioners HTC & LG — Exhibit 1002, n
`
`Petitioners HTC & LG - Exhibit 1002, p. 148
`
`
`
`
`
`

`
`IEEE Transactions on Consumer E.‘ "---mics, Vol. 35. No.
`
`
`
`SINGLE CHIP MPEG AUDIO DECODER
`
`Greg Maturl
`LSI Logic Corporation
`Milpllas, California
`
`CD98 3063292 $03.00 '’ 1992 IEEE A
`
`ABSTRACT
`
`An IC has been designed and fabricated which
`can take an MPEG System or MPEG Audio
`stream and decode Layerl and Layer II (MUSI-
`CAM) encoded audio into 16 bit PCM data.
`Audiofvideo synchronization, cue and review is
`provided via its external channel buffer.
`
`_
`
`SUMMARY
`
`The Single Chip MPEG Audio Decoder will take
`an MPEG Layer I or H (MUSICAM) System or
`Audio stream, and provide complete decoding '
`into 16 bit serial PCM outputs. In addition. pre-
`sentation can be delayed and audio frames
`
`_
`
`30 M11: clock. no other hardware is required.
`'I'he IC is controlled by an 3 or 16 bit micropro-
`cessor, but can operate as a stand alone device
`with reduced flexibility.
`
`The [C can receive data up to a 15 Mbitsfsecond
`either serially or through microprocessor inter-
`face (selectable for 8 or 16 bits). An input fifo
`allows Ll1eIC to handle burst rates of up to ?.5
`Megabyteslsec for up to 128 bytes. The IC will
`strip out the audio streams from MPEG system
`streams and provide presentation time and para-
`rnetI'ic information to the host. The audio frames
`will then be stored in the channel buffers.
`
`
`
`Figiue 1. MPEG Audio decoder System
`
`skipped by means of the cha.nnel buffer, an exter-
`nal 256K x 4 DRAM controlled by this IC. This
`allows coarse synclironization of audio and video
`for skews up to 1 second for Layer I and 2.5 sec-
`onds for Layer II. Control over which frames are
`played or slcipped provides cue lreview features.
`Except for the charmel buffer DRAM and a 25 -
`
`The IC is divided into 4 major parts: the
`preparner, the decoder. the DRAM controller,
`and PCM interface.
`
`The preparser performs several functions: sys-
`tetnlaudio stream synchronization. stripping off
`of parametric and presentation time headers.
`syntax checking, CRC checking, and cataloging
`
`Manuscript received June 5, 1992
`
`Page 149 of 280 '
`
`
`
`Petitioners HTC & LG — Exhibit 1002,
`
`Petitioners HTC & LG - Exhibit 1002, p. 149
`
`

`
`I
`
`'._.'.,_..m:
`
`sinue Chip MPEG Audio mm
`
`
`349
`
`
`
`To uP Registers"
`
`CRC check
`
`Figure 2.Prcpa.rscr Architecmre
`
`frames. Error concealment (by repeating the last
`good frame) can be provided automatically. Since
`the frame must be partially expanded to obtain
`this informati on, the frame is stored in the chan-
`
`nel buffer in a partially expanded form. A playlist
`is generated to tell the decoder which frame to
`decode next. The microprocessor can control
`which directionto an the playlist, skip frames in '
`the playlist and which direction for the decode to
`read the playlist;'I'he decoder does most of the
`algorithmic work: It performs inverse quantiza-
`tion, scaling, and subband synthesis. It uses a 24
`- bit architecture. In addition, on Layer II it per-
`forms degrouping prior to dequantization. Filter
`coefficitents,dequantization values. scratchpad
`and vector memories are internal.
`
`The DRAM controller provides RAS,CAS,
`address and data to the DRAM. It arbinates
`
`between the preparser and the decoder. It also
`provides hidden refreshing. This controller
`requires a 256K x 4 DRAM (100 ns or faster)
`
`The PCM_interface buffers the PCM output from
`the decoder and provides 3 and 4 wire serial out-
`put compatible to most serial DACs. The serial
`clock is generated from the system clock using a
`fixed point divisor provided by the host (4 bits
`integer, 16 fractional). The decoder can also be
`bypassed, allowing serial PCM to be passed
`directly from input to output.
`
`SCALE
`FACTOR
`
`
`I ALLOCATION I
`
`
`
`Figure 3.Decoder Architecture
`
`Page 150 of 280
`
`Petitioners HTC & LG — Exhibit 1002,
`
`Petitioners HTC & LG - Exhibit 1002, p. 150
`
`

`
`IEEE Transactions on Consumer ‘""‘3ronics. Vol. 38. No. 3. AUGUST 1991'
`
`Functional Block Operation
`
`preparser rettuns the presentation time stamp
`for use in audio-video synchronization.
`
`When initialized, the decoder synchronizes
`itself by monitoring the data stream and locating
`an audio frame in the data stream.When MPEG
`
`data is input, the chip strips away all unneeded
`information, retaining only the audio and con-
`trol data. This data is then partially decom-
`pressed and stored in a channel buffer. When the
`appropriate control signals are seen, this stored
`data is played (fully decornpressed and outputin
`PCM format).
`
`These activities are accomplished in general as
`follows:
`
`Audio Synchronization
`
`If the synchronization code is the selected
`audio stream or the input stream is only audio.
`the preparser will then synchronize to the audio
`st:rea.m. It first detects the 12 bit audio sync. if
`the bitrate is not free format, the bytes remain-
`ing in the frame are calculated from the bitrate
`and sampling frequency (extracted from the
`parametric values in the bitstream) according
`to the fonnula:
`
`Input Synchronization and Buffering
`
`bytes -—- 48 * bitratelsamp1ing_frequency (1)
`
`Data in either serial or parallel form enters the
`MPEG Audio decoder through the Controller
`Interface. The data is first synchronized to the
`system clock (SYSCLK), then is sent to the
`Input Data FIFO. The FIFO buffers data and
`supplies it to the Preparser. The FIFO can
`accommodate burst rates up to (input cloc1<)l4
`byteslsec. for bursts of 128 bytes.
`
`System Preparser
`
`The Preparser performs stream parsing. For
`ISO System Stream parsing and synchroniza-
`tion, it detects the packet start code or system
`header start code and uses these to synchronize
`with packets. The parser reads the 16 bit “num-
`ber of bytes“ code in either one of these headers
`and counts down the bytes following. When
`count 0 is reached the next set-of bytes should be
`a sync word. If not. the sync word seen was
`either emulated by audio or private data or a
`system error. The preparser will not consider
`itself synchronized until 3 consecutive good
`syncs have occurred. Likewise, it will not con-
`sider itself unsynchronized until 3 false are
`detected. This hysteresis is detailed in the flow-
`chart in Figure 4. Upon syn_chroniz.ation. the
`
`bytes = 144 * bit:rate.fsan1pling__frequency(]I)
`
`This value is loaded into a byte counter. As
`with the system syncluonization, when the
`counter down counts to zero the preparser ver-
`ifies the next 12 bits are a sync code. if the pad-
`ding bit is set the counter will wait 4 bytes on
`Layer 1 and 1 byte on "layer 11 before checking
`for the sync code. The hysteresis is similar to
`that of the MPEG system synchronization. The
`audio synchronization is identical for free for-
`mat except one extra frame is required where
`the bytes in the name are counted rather than
`calculated. Figure 5 shows the audio synchro-
`nization.
`
`Storing in Channel Buffer
`
`After synchronization, allocations and scale-
`factors are separated out and stored in the
`channel buffer. In layerl there are 32 bit allo-
`cations. each allocation 4 bits representing 0 to
`15 bits per sample, 1 not allowed. In Layerll
`there are 8 to 30 allocations 1 to 4 bits in
`
`.
`
`length, representing 0 to 16 bits per sample.l
`not allowed. In Layer 1], information on
`whether the samples are grouped (three sam-
`ples combined into a single sample) is also
`stored with the allocation.
`
` +
`Page 151 of 280
`
`Petitioners HTC & LG — Exhibit 1002, n
`
`Petitioners HTC & LG - Exhibit 1002, p. 151
`
`

`
`
`
`Figure 4. Systenn Sychronlznlion Hyslerlsis
`
`& LG — Exhibit 1002,
`
`
`manna: tn nun:
`
`
`
`
`
`
`
`mm shglecmp MPEG Audi‘ Decéaér
`
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`
`
`
`Petitioners HTC & LG - Exhibit 1002, p. 152
`
`

`
`"‘.!.\.'-
`
`"— ‘
`
`'
`
`"
`
`"
`
`_
`
`_
`
`' H-_"'l_E_EE Transactions on Consumer Electronics. Vol. 33. No. 3. AAUGUST I99:
`
`I
`
`to a lookup
`Scalefactors are 6 bits indi
`table. indicating the maximum amplitude of
`the samples in a subband. In Layer 1, there is
`one scalefactor for each non-zero bit alloca-
`
`tion. In Layer 11 there is 1 to 3 scalefactors per
`“°“'w° bi‘ a“°°ati°“- The “cm” ““mb°T is
`determined by a 2 bit scalefactor select (again
`1 9” “°“‘z°‘'° aH°°au°n)' The 9739339’ uses
`this information to separate out the scalefac-
`tors. The format that the allocatlons and scaIc-
`factors are stored in the memory is shown in
`735161
`-
`
`‘
`
`Audio data cat. ..s parsed atinput clockfz bits
`per second. The limitation is the DRAM tim-
`ing.
`
`Parametric Data
`
`The 20 bits following the audio sync word are
`called Parametric data b.hs_ These bits are used
`by the decoder and presented to the host inter-
`face_ A maskable imermpt which is asserted as
`soon as these bits are read from the bitsmeam
`lets an optional microprocessor know these
`bits areavailable.Table1'[ shows the bit defini-
`
`Table 1: channel buffer format
`
`non‘
`
`Table 2: Parametric Data
`Format
`
`
`
`
`
`Protection
`
`11 B
`
`
`
`Row
`Address
`(HEX)
`
`.
`I“f§$:§°“
`
`_
`
`00O:03F
`
`allocations (channel 1)
`
`040:O'?F
`
`first scale index (channel 1)
`
`
`
`080:OBF
`
`secondscale index (channel 1)
`
`0C0:OFF
`
`third scale index (channel 1)
`
`100:13F
`
`allocations (channel 2)
`
`140: 17F
`
`firs: scale index (channel 2)
`
`180: IBF
`
`second scale index (channel 2)
`
`1C0:1FF
`
`third scale index (channel 2)
`
`
`Sampling-
`
`f
`
`
`
`11:10
`
`
`
`As allocations are being written to the chan-
`nel bufi'er a small RAM records whether the
`allocation was non-zero. It then uses this infor-
`
`mation to separate out scalefactors without
`having to reread the channel bufi'er. On Layer
`II this is also done for scalefactor select bits.
`The same RAM holds these values for later use
`
`in scalefactor decoding.
`
`Samples are left bitpacked when put into the
`channel buffer, just as received in the _bit-
`stream. They are stored immediately after the
`“u°°a“°"‘3 and scale '-“d‘°°5-
`
`,
`Angular? data
`The data immediately following the last data
`bit until the next frame sync is considered
`
`',:
`:3!‘
`__.,..
`
`Petitioners HTC & LG — Exhibit 1002, n
`
`Petitioners HTC & LG - Exhibit 1002, p. 153
`
`

`
`
`
`" I j'.Mm,;:
`
`smug Chip mac Audio Decoder
`
`'
`
`.
`
`353
`
`tors generated in the subband synthesis. All
`memory is 24 bits, a block diagram is shown in
`Figure 3.
`-
`
`The decoding process begins with a start
`command being generated from the micropro-
`cessor or external start input. At that point the
`decoder reads parameters and channel buffer
`address infonnation from the play buffer, and
`requests data from the channel buffer. The
`DRAM controller arbitrates between the
`
`preparser requesting to write data to the chan-
`nel buffer and the decoder trying to read data
`for decompression.
`
`In the first read, the decoder obtains alloca-
`tion and scalefactor-information. In the second
`read. the decoder obtains 1 to 5 nibbles con-
`
`taining the subband sample. If degrouping is
`required, the decoder implements the degroup-
`ing process:
`'
`
`For (i =0;i<3;i++)
`
`{
`
`Sample[i] = c%n1evels;
`
`-
`
`c = (int) cfnlevels;
`
`l b
`
`y using a serial divider.
`
`ancillary data. The last bit ordata is calculated
`from the decoded allocations and scale indices.
`Thisdata is stored ina l6X8 bit FIFO. An
`interrupt indicates valid data. in the FIFO,
`when the FIFO is half full, and when it has
`over-flowed. If the ancillary data-is less than 8
`bits or a sync word is detected the ancillary bits
`are left aligned and written to the FIFO.
`
`_ Play Buffer
`
`The play buffer is a FIFO indicating the loca-
`tion in the channel buffer of the next frame to
`be played as well as minimum irtforrnation the
`decoder needs to decode the samples. Usually,
`the play FIFO contains consecutive 4K block
`addresses for layer 11 and 2K block addresses
`for Layer 1. However, if errors occur, the next
`address will be the last good frame stored.
`
`The infonnation that is passed in the play
`buffer is mode and mode extension, and a bit
`indicating if the frame should be blanked or
`played. This bit is set if an error occurs and
`error concealment is not selected. Since bitrate
`
`and sampling frequency are not allowed to be
`changed without resetting the decoder; the
`frame sizes remain the same. A time equiva-
`lent to the frame in error can be silenced with
`this method.
`
`Decoder Operation
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`
`The decoder receives data for full decompres-
`sion from the channel buffer. The location of
`
`Dequantization is then performed by the fol-
`lowing equation:
`
`this information and other required parameters
`are provided by the play buffer. The decoder
`performs all of the following functions:
`degroupingdequnatization. denormalization
`and subband synthesis. Except degrouping, all
`functions are performed by use of a 2-cycle 24-
`bit multiplier -accumulator. A ROM provides
`lockup tables for scalefactors, quantization
`values. DCT and window coefficients. Two
`
`separate RAMS are provided, one for the
`dequantized c