UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.
`Patent Owner
`
`________________________
`
`Case IPR. No. Unassigned
`U.S. Patent No. 6,784,552
`Title: STRUCTURE HAVING REDUCED LATERAL SPACEER EROSION
`________________________
`
`Declaration of Dr. Richard Fair in Support of
`Petition For Inter Partes Review of U.S. Patent No. 6,784,552
`Under 35 U.S.C. §§ 311-319 and 37 C.F.R. §§ 42.1-.80, 42.100-.123
`
`Case No. IPR2016-00782
`DSS.2011.001
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`

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`
`
`
`
`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
`
`TABLE OF CONTENTS
`
`
`
`Page
`
`INTRODUCTION AND QUALIFICATIONS ............................................... 1
`I.
`II. MATERIALS RELIED UPON IN FORMING MY OPINION ..................... 4
`III. UNDERSTANDING OF THE GOVERNING LAW ..................................... 5
`A. Anticipation ........................................................................................... 5
`B.
`Invalidity by Obviousness ..................................................................... 6
`IV. LEVEL OF ORDINARY SKILL IN THE ART ............................................. 8
`V.
`TECHNOLOGY OVERVIEW AND OVERVIEW OF THE 552
`PATENT .......................................................................................................... 9
`A.
`Technology Background: Semiconductor Fabrication ......................... 9
`B.
`Technology Background: SEM Imaging ............................................ 15
`C.
`The 552 Patent ..................................................................................... 19
`552 PATENT PROSECUTION HISTORY .................................................. 25
`VI.
`VII. CLAIM CONSTRUCTIONS ........................................................................ 28
`A.
`Legal Standard ..................................................................................... 28
`B.
`“contact region/opening” (claims 1, 4, 7, 8, and 12) .......................... 28
`VIII. THE PRIOR ART .......................................................................................... 29
`A.
`“Self Aligned Bitline Contact For 4 Mbit dRAM”
`(“Kuesters”) ......................................................................................... 29
`U.S. Patent No. 5,482,894 (“Havemann”) .......................................... 38
`B.
`U.S. Patent No. 4,686,000 (“Heath”) .................................................. 41
`C.
`IX. OBVIOUSNESS COMBINATIONS – MOTIVATIONS TO
`COMBINE ..................................................................................................... 43
`A. Kuesters in Combination with Havemann .......................................... 43
`B.
`Kuesters in Combination with Heath .................................................. 46
`C.
`Kuesters in Combination with Heath and Havemann ......................... 49
`X. GROUNDS OF INVALIDITY ..................................................................... 50
`XI. DECLARATION IN LIEU OF OATH ......................................................... 50
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
`
`I, Richard B. Fair, hereby declare as follows:
`
`I.
`
`INTRODUCTION AND QUALIFICATIONS
`
`1.
`
`My name is Richard B. Fair. My findings, as set forth herein, are
`
`based on my education and background in the fields discussed below.
`
`2.
`
`I have been retained on behalf of Petitioner Samsung Electronics Co.,
`
`Ltd. (“Samsung”) to provide this Declaration concerning technical subject matter
`
`relevant to the inter partes review petition (“Petition”) concerning U.S. Patent No.
`
`6,784,552 (the “552 Patent,” SAMSUNG-1001). I reserve the right to supplement
`
`this Declaration in response to additional evidence that may come to light.
`
`3.
`
`I am over 18 years of age. I have personal knowledge of the facts
`
`stated in this Declaration and could testify competently to them if asked to do so.
`
`4.
`
`My compensation is not based on the resolution of this matter. My
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`findings are based on my education, experience, and background in the fields
`
`discussed below.
`
`5.
`
`My background and experience is summarized in my curriculum
`
`vitae, a true and correct copy of which is submitted as Exhibit SAMSUNG-1004.
`
`Some of the relevant points are described below as well.
`
`6.
`
`I received a B.S. in Electrical Engineering from Duke University in
`
`1964, an M.S. in Electrical Engineering from Pennsylvania State University in
`
`1966, and a Ph.D. in Electrical Engineering from Duke University in 1969. My
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`graduate research was on electron beam systems (scanning electron microscopy)
`
`and ion beam systems (ion beam deposition of thin metal films).
`
`7.
`
`In 1969, I joined Bell Laboratories working on the fabrication, design,
`
`and testing of numerous semiconductor devices and integrated circuits, including
`
`metal-oxide-semiconductor (MOS) dynamic memory chips. During my time at
`
`Bell Laboratories, I worked on advanced silicon process development and started
`
`an effort on mixed signal CMOS integrated circuits. I was employed at Bell
`
`Laboratories until 1981, eventually rising to Supervisor.
`
`8.
`
`I have been teaching in the Department of Electrical and Computer
`
`Engineering at Duke University since 1981. I have been a Professor from 1981 to
`
`the present. I am currently the Lord-Chandran Professor of Engineering in the
`
`Edmund T. Pratt, Jr. School of Engineering.
`
`9.
`
`I also served as the vice president of design research and technology,
`
`director of microfabrication technology, executive director, and acting president of
`
`Microelectronics Center of North Carolina (“MCNC”), a technology non-profit
`
`that builds, owns, and operates a leading-edge broadband infrastructure for North
`
`Carolina’s research, education, non-profit healthcare, and other community
`
`institutions, from 1981 to 1994.
`
`10. While at MCNC I helped setup a state-of-the-art CMOS processing
`
`facility and directed
`
`research on
`
`semiconductor processing
`
`including
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`photolithography, wafer cleaning, annealing, ion implantation, plasma-enhanced
`
`CVD of thin films, metallization, and anisotropic etching processes. We conducted
`
`research on multi-level metal interconnects, barrier metallurgy, organic and
`
`inorganic inter-metal dielectrics, anti-reflective coatings, via and trench etching
`
`processes, and selective tungsten deposition for via filling. In 1987 we designed
`
`and built the world’s first 1 million transistor chip, a parallel processor
`
`supercomputer. I also was responsible for the MCNC analytical lab, which
`
`included electron microscopy, atomic composition analysis, and sample
`
`preparation for reverse engineering studies. I have used such analytical tools to
`
`perform reverse engineering of semiconductor devices.
`
`11.
`
`In 1994, I returned to Duke University full-time. Since then I have
`
`continued to teach courses on (1) the design and analysis of analog and digital
`
`integrated circuits, (2) semiconductor devices, (3) the chemistry and physics of
`
`transistor and integrated circuit fabrication, and (4) thin-film microfluidic devices,
`
`fluid dynamics, and applications. In addition, I have an active funded research
`
`program that involves undergraduate and graduate students.
`
`12.
`
`I am a Life Fellow of the Institute of Electrical and Electronic
`
`Engineers (“IEEE”), a Fellow of the Electrochemical Society, past Editor-in-Chief
`
`of the Proceedings of the IEEE, and I have served as Associate Editor of the IEEE
`
`Transactions on Electron Devices. I am a recipient of the IEEE Third Millennium
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`Medal, and I was awarded the Solid State Science and Technology Medal of the
`
`Electrochemical Society in April 2003 (Gordon E. Moore Medal).
`
`13.
`
`I have published over 170 papers in refereed and peer-reviewed
`
`journals and conference proceedings, contributed chapters to 12 books, edited nine
`
`books or conference proceedings, given over 130 invited talks in the field of
`
`electrical engineering, and I am a named inventor on 30 granted U.S. patents and
`
`24 pending U.S. patent applications.
`
`II. MATERIALS RELIED UPON IN FORMING MY OPINION
`In addition to reviewing the 552 Patent, I also reviewed and
`14.
`
`considered the prosecution history of the 552 Patent (SAMSUNG-1002). I also
`
`reviewed and considered the prosecution history of U.S. Patent No. 6,066,555, the
`
`parent of the 552 Patent (SAMSUNG-1008). I have also reviewed the prior art
`
`Kuesters et al., “Self Aligned Bitline Contact For 4 Mbit dRAM,” Proceedings of
`
`the First International Symposium on Ultra Large Scale Integration Science and
`
`Technology, 1987, pp. 640-649 (“Kuesters,” SAMSUNG-1005), U.S. Patent No.
`
`5,482,894 (“Havemann,” SAMSUNG-1006), and U.S. Patent No. 4,686,000
`
`(“Heath,” SAMSUNG-1007). I also considered the background materials cited
`
`herein.
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`III. UNDERSTANDING OF THE GOVERNING LAW
`I understand that a patent claim is invalid if it is anticipated or obvious
`15.
`
`in view of the prior art. I further understand that invalidity of a claim requires that
`
`the claim be anticipated or obvious from the perspective of a person of ordinary
`
`skill in the relevant art at the time the invention was made.
`
`16.
`
`I have been informed that, in order to render a claimed apparatus
`
`obvious, the prior art must enable a person of ordinary skill in the art to make the
`
`apparatus. I have been further informed that a reference or combination is enabled
`
`if undue experimentation is not required to make the claimed apparatus.
`
`17.
`
`I have been informed that it is the Patent Owner’s burden to show that
`
`a reference or combination is not enabling. I reserve the right to amend or
`
`supplement this declaration if the Patent Owner introduces evidence that any
`
`references or combinations are not enabling.
`
`18.
`
`I have been informed that a person of ordinary skill in the art has
`
`ordinary creativity, and is not an automaton.
`
`A. Anticipation
`I have been informed that a patent claim is invalid as anticipated
`19.
`
`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
`
`is found either explicitly or inherently in a single prior art reference.
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`I have been informed that a claim is invalid under 35 U.S.C. § 102(b)
`
`20.
`
`if the invention was patented or published anywhere, or was in public use, on sale,
`
`or offered for sale in this country, more than one year prior to the filing date of the
`
`patent application (critical date). I further have been informed that a claim is
`
`invalid under 35 U.S.C. § 102(e) if an invention described by that claim was
`
`disclosed in a U.S. patent granted on an application for a patent by another that was
`
`filed in the U.S. before the date of invention for such a claim.
`
`B.
`21.
`
`Invalidity by Obviousness
`
`I have been informed that a patent claim is invalid as “obvious” under
`
`35 U.S.C. § 103 if it would have been obvious to one of ordinary skill in the art,
`
`taking into account (1) the scope and content of the prior art, (2) the differences
`
`between the prior art and the claims, (3) the level of ordinary skill in the art, and
`
`(4) any so called “secondary considerations” of non-obviousness if they are
`
`present. I reserve the right to amend or supplement this declaration if the Patent
`
`Owner introduces evidence of any secondary considerations of non-obviousness.
`
`22. My analysis of the prior art is made as of the time the invention was
`
`made.
`
`23.
`
`I have been informed that a claim can be obvious in light of a single
`
`prior art reference or multiple prior art references. I further understand that
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`exemplary rationales that may support a conclusion of obviousness include:
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`(A) Combining prior art elements according to known methods to yield
`
`predictable results;
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`(B) Simple substitution of one known element for another to obtain
`
`predictable results;
`
`(C) Use of known technique(s) to improve similar devices (methods, or
`
`products) in the same way;
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`(D) Applying a known technique to a known device (method, or product)
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`ready for improvement to yield predictable results;
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`(E) “Obvious to try” – choosing from a finite number of identified,
`
`predictable solutions with a reasonable expectation of success;
`
`(F) Known work in one field of endeavor may prompt variations of it for use
`
`in either the same field or a different one based on design incentives or other
`
`market forces if the variations are predictable to one of ordinary skill in the art;
`
`(G) Some teaching, suggestion, or motivation in the prior art that would
`
`have led one of ordinary skill in the art to modify the prior art reference or to
`
`combine prior art reference teachings to arrive at the claimed invention.
`
`24.
`
`I have been informed that in considering obviousness, it is important
`
`not to determine obviousness using the benefit of hindsight derived from the patent
`
`being considered.
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`IV. LEVEL OF ORDINARY SKILL IN THE ART
`In my opinion, a person of ordinary skill in the art at the time of the
`25.
`
`claimed inventions would have had a bachelor’s degree in electrical engineering,
`
`chemistry, materials science, or physics, or a closely related field, along with at
`
`least 2-3 years of experience in semiconductor fabrication. An individual with a
`
`master’s degree in a relevant field, such as electrical engineering, chemistry,
`
`materials science, or physics, would require less experience in semiconductor
`
`fabrication.
`
`26.
`
`I reserve the right to amend or supplement this declaration if the
`
`Board adopts a definition of a person of ordinary skill in the art other than that
`
`described above, which may change my conclusion or analysis. However, should
`
`the Board adopt a higher standard, it would not change my opinion that all of the
`
`claims of the 552 Patent (“claims at issue”) are invalid.
`
`27. My opinion below explains how a person of ordinary skill in the art
`
`would have understood the technology described in the references I have identified
`
`herein around the 1995 time period, which is the approximate date when the
`
`application to which the 552 Patent claims priority was filed. I was a person of at
`
`least ordinary skill in the art in 1995.
`
`
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`V. TECHNOLOGY OVERVIEW AND OVERVIEW OF THE 552
`PATENT
`
`28. The 552 Patent was filed on March 31, 2000. The 552 Patent is a
`
`division of U.S. Application No. 08/577,751, which was filed on December 22,
`
`1995. Application No. 08/577,751 issued as U.S. Patent No. 6,066,555 (“555
`
`Patent”). The 552 Patent issued on August 31, 2004.
`
`29. The 552 Patent relates generally to a structure with minimal lateral
`
`spacer erosion, providing a contact opening with a small alignment tolerance
`
`relative to a gate electrode or other structure. SAMSUNG-1001, 552 Patent at
`
`Abstract. The claims at issue relate to a structure for a transistor with a self-
`
`aligned contact. Id.
`
`30. Before discussing the details of the specification of the 552 Patent, I
`
`will provide a brief background on the technology of semiconductor fabrication. I
`
`will also provide a high-level overview of SEM imaging and the reading of SEM
`
`images.
`
`A. Technology Background: Semiconductor Fabrication
`31. The relevant aspects of the 552 Patent relate to semiconductor device
`
`processes, and more specifically to methods for etching contact openings through
`
`insulating layers and semiconductor devices with well-defined contact openings.
`
`Before discussing the specifics of the 552 Patent specification, I will discuss the
`
`manufacture and etching of semiconductor devices at a high level.
`
`
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`32. Manufacturing very large-scale integrated circuit devices involves the
`
`process of simultaneously forming microelectronic structures on a silicon wafer.
`
`The microelectronic devices are created through a series of steps which include
`
`deposition of thin films of material, patterning of these thin films, etching of these
`
`thin films, and modification of the underlying materials.
`
`33. A typical transistor to be crafted on a silicon wafer could look like the
`
`following:
`
`https://www.st-andrews.ac.uk/~www_pa/Scots_Guide/first11/part9/fig4.gif
`
`34.
`
`In this transistor, there are three “metal contacts” or “terminals,” the
`
`Gate, Source, and Drain. The Gate is a conductive layer formed on a very thin
`
`
`
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`insulating layer upon the silicon substrate. The Source and Drain contacts are
`
`conductive layers in contact with source and drain diffusion regions of the silicon
`
`substrate that have been “doped” with the implantation of ions. If a positive
`
`voltage is applied to the Gate, a layer between the source and drain called the
`
`Channel connecting the source and drain diffusion regions will become more
`
`electrically conductive.
`
`35. Diffusion regions are created by implanting ions of different dopants
`
`or impurities into the silicon substrate to create conductive regions. A highly
`
`energized stream of ions is directed at the substrate and some ions are captured by
`
`the substrate surface.
`
`http://www.globalspec.com/learnmore/manufacturing_process_equipment/vac
`uum_equipment/thin_film_equipment/semiconductor_process_systems_cluste
`r_tools
`36. Once diffusion regions have been created, structures can then be
`
`created on the silicon substrate by the deposition of thin films of material. There
`
`are multiple methods of depositing materials, including chemical vapor deposition
`
`(CVD) and physical vapor deposition (PVD). In the CVD process, a gas is heated,
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`or a plasma is created, to form or “grow” a thin film or coating. This process is
`
`typically used for the deposition of dielectric (insulating) films. PVD uses the
`
`evaporation or sputtering of atoms to form a condensed film layer on a substrate.
`
`37.
`
`For example, in our exemplar transistor, the thin insulating layer
`
`upon which the Gate sits can be formed as a thin layer of thermally-grown silicon
`
`dioxide. Next, the conductive material of the Gate, such as polysilicon, can be
`
`deposited upon the thermally-grown silicon dioxide using CVD.
`
`38. As the 552 Patent describes as admitted prior art, in order to avoid
`
`“poor quality contacts” or “a short circuit” between the conductive material of the
`
`Gate and the Source and Drain Contacts, additional thin insulative films are
`
`deposited. See 552 Patent at 2:63-3:2. An exemplar structure can be seen in
`
`admitted prior art Figure 1(B) of the 552 Patent:
`
`SAMSUNG-1001, 552 Patent at Figure 1(B)
`
`39.
`
`In Figure 1(B), region 140 is a diffusion region, 130 is a self-aligned
`
`contact region for connection to other devices, 110 is the conductive polysilicon
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`layer of the gate electrode, and 120 is an encapsulating dielectric layer. In Figure
`
`1(B), layer 120 is intended to provide electrical insulation and to avoid a short
`
`circuit.
`
`40.
`
`Insulating layer 120, as well as layer 125 and the unlabeled top layer,
`
`would be deposited on the substrate after Gate 110, as previously described.
`
`41.
`
`In order to make a connection to the diffusion region 140 once these
`
`layers have been deposited, it is necessary to etch a contact opening, 130. Etching
`
`is the process of removing material. As was well known at the time of filing of the
`
`552 Patent, etching broadly falls into two categories: wet etches, using liquid
`
`chemicals, and dry etches, using a gas.
`
`42.
`
`In a wet etch process, a liquid chemical dissolves the desired thin film,
`
`but not the photoresist used to create the etch pattern, the substrate, or a layer
`
`known as an etch stop. Wet etches are generally isotropic, meaning that the etch
`
`removes material in both the vertical and horizontal directions simultaneously.
`
`Figures depicting a semiconductor before and after a wet etch are shown below:
`
`http://www.aplusphysics.com/courses/honors/microe/processing.html
`
`43.
`
`In a dry etch process, a gaseous chemical is placed into a strong
`
`electric field, which produces gas ions, gas atoms and electrons in a glow
`
`
`
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`discharge. The gas ions can then be accelerated vertically downward away from
`
`the glow discharge toward the substrate. The acceleration of the ions physically
`
`and chemically attacks the thin film to be removed. This process is also known as
`
`reactive ion etching (RIE). A dry etch will typically create an anisotropic etch
`
`profile, meaning it removes materials in the vertical direction only. Figures
`
`depicting a dry etch are shown below:
`
`
`
`http://www.aplusphysics.com/courses/honors/microe/processing.html
`
`44. As was also well known, in addition to wet or dry etches and isotropic
`
`or anisotropic etches, etches may also be selective or non-selective for a specific
`
`thin film material. For example, as described in the admitted prior art of the 552
`
`Patent, an etch that is selective for silicon nitride compared to silicon dioxide will
`
`effectively etch silicon nitride at a higher rate than silicon dioxide. See 552 Patent
`
`at 2:11-21. In contrast, a non-selective etch will etch away both types of materials
`
`at approximately the same rate. Id.
`
`
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`45. As was well known in the art, the selectivity of an etch could be
`
`combined with specific layers of materials to create an etch stop layer (e.g., layer
`
`125 in Figure 1(B)).
`
`SAMSUNG-1001, 552 Patent at Figure 1(B)
`
`
`
`46. The etch stop layer effectively stops an etchant from further removing
`
`material beyond the etch stop layer. The “etch stop layer 125 permits subsequent
`
`etching of the substrate without risk of exposing the device structures and layers”
`
`protected by the etch stop layer. Id. at 4:13-18.
`
`Technology Background: SEM Imaging
`
`B.
`47. The Kuesters prior art reference, SAMSUNG-1005, contains scanning
`
`electron microscopy (SEM) images disclosing features of actual semiconductor
`
`devices fabricated in accordance with its teachings. In order to understand and
`
`read these images, some background is required on the SEM method and the
`
`reading of SEM images.
`
`
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`48. SEM is a method for high-resolution imaging of microscopic
`
`structures. SEM uses electrons for imaging, much as a light microscope uses
`
`visible light. SEM produces images of an object by scanning it with a focused
`
`beam of electrons. The electrons interact with atoms in the object, producing
`
`various signals that can be detected and that contain information about the object’s
`
`surface topography and composition.
`
`49. A common SEM imaging method is the detection of secondary
`
`electrons emitted by atoms excited by the electron beam. By scanning the object
`
`and collecting the secondary electrons with a detector, an image displaying the
`
`topography of the object is created. The number of secondary electrons that can be
`
`detected depends, among other things, on the angle at which the beam meets the
`
`surface of the object and the relative distances between the regions of the surface
`
`of the object and the electron detector.
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`http://www.geosci.ipfw.edu/cgi-bin/sem/techinfo.cgi?choice=secondelec
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`50. Secondary electron imaging collects low-energy secondary electrons
`
`that are ejected from the atoms of the object by inelastic scattering interactions
`
`with beam electrons. These secondary electrons are detected and converted into a
`
`two-dimensional intensity distribution that can be viewed and photographed, or
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`converted using an analog-to-digital converter and saved as a digital image.
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`DSS.2011.019
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
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`http://www.nanoscience.com/products/sem/technology-overview/sample-
`electron-interaction/
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`51. To create a SEM image, the incident electron beam is scanned in a
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`raster pattern (e.g., left-to-right, top-to-bottom) across the sample’s surface. The
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`emitted electrons are detected for each position in the scanned area by the electron
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`detector. See http://www.charfac.umn.edu/sem_primer.pdf.
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`52. SEM images produced by secondary electrons use a very narrow
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`electron beam. Due to the narrow width of the beam, the resulting SEM images
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`have a large depth of field, yielding a three-dimensional appearance in a two-
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`dimensional image.
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`53. The topography of surface features of the object influences the
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`number of electrons that reach the secondary electron detector from any point on
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`DSS.2011.020
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`the scanned surface. See http://www.mee-inc.com/hamm/scanning-electron-
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
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`microscopy-sem/. The brightness of the signal depends on the number of
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`secondary electrons reaching the detector. Regions of the object that are closer to
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`the detector will emit more electrons that will be picked up by the detector and thus
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`will appear brighter. Regions of the object further away from the detector will
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`emit fewer electrons that will be picked up by the detector and thus will appear
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`darker. In other words, if the electron beam travels into a depression or hole in the
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`object, the number of secondary electrons that can escape the sample surface is
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`reduced and the image processing places a corresponding dark spot on the image.
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`Conversely, if the electron beam scans across a projection or hill on the sample,
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`more secondary electrons can escape the sample surface and the image processing
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`places a bright spot on the image. See http://www.seallabs.com/how-sem-
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`works.html. This local variation in electron intensity creates the image contrast
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`that reveals the surface morphology.
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`C. The 552 Patent
`54. The 552 Patent relates to “semiconductor device processes, and more
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`particularly, to improved methods for etching openings in insulating layers and a
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`semiconductor device with well defined contact openings.” 552 Patent at 1:10-13.
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`55. The 552 Patent discloses the prior art process for fabricating
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`semiconductors discussed briefly above. See also Figures 2(A) and 2(B).
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
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`SAMSUNG-1001, 552 Patent at Figures 2(A) and 2(B)
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`In Figures 2(A) and 2(B), a gate oxide layer 210 is formed on the substrate 200.
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`On the gate oxide, a conductive layer 220 is formed. Over the conductive layer, an
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`insulating layer 230 is deposited. Alongside the conductive layer, the insulating
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`material forms an insulating spacer 235. This insulating spacer protects the
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`conductive layer from any conductive material later added to the contact region
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`270. Over the insulating layer, insulating spacer, and the bottom of the contact
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`region, an etch stop layer 240 is deposited, and atop the etch stop layer, a further
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`blanket layer 250. Id. at 4:48-5:17.
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`56.
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`The alleged problem that the 552 Patent purports to solve is that
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`existing semiconductor fabrication processes described in the patent causes the
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`insulating spacers alongside the Gate electrode to become sloped. Id. at 5:4-17.
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`According to the 552 Patent, when an etch is performed in the contact region 270
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
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`to remove the remaining etch stop material 240, the insulating spacer 235 on the
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`sidewall of the gate electrode 220 transforms from “substantially rectangular” to a
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`“sloping or tapered” shape. Id. at 5:4-17. The 552 Patent further claims that due to
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`ease of completely filling the contact region 270 and “good step coverage, industry
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`preference is for sloped spacers… similar to that shown in FIG. 2(B).” Id. at 5:31-
`
`34.
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`57. The 552 Patent continues by alleging that subsequent etches to clean
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`the contact region will further erode the sloped sidewall spacer, creating additional
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`risk of short circuit. This further erosion is illustrated in Figure 3:
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`SAMSUNG-1001, 552 Patent at Figure 3
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
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`58.
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`In Figure 3, the sloped sidewall spacer has been eroded from the
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`dotted line to the solid line. This can cause the gate electrode 320 to short circuit
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`to the conductive material later deposited in contact region 360. Id. at 6:13-21.
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`59. Notably, the 552 Patent discloses as existing prior art the use of
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`sidewall spacers to protect a gate electrode, the use of anisotropic etches to remove
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`material in a vertical direction, and the use of etchants generally in combination
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`with the deposition of layers on a substrate to create an integrated circuit device.
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`See id. at 1:10-7:13.
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`60.
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`The alleged inventive concept is to take care “to etch the spacers 435
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`such that the spacers 435 have a substantially rectangular profile.” Id. at 11:48-49.
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`The “invention relates to these process conditions as well as others that result in
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`the retention of a boxy spacer.” Id. at 13:14-16. The 552 Patent accomplishes this
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`through the use of an etch that is “almost completely anisotropic, meaning that the
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`etchant etches in one direction—in this case, vertically (or perpendicular relative to
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`the substrate surface) rather than horizontally.” Id. at 7:45-48. This etch “retains
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`the substantially rectangular lateral spacer portion of the first insulating layer.” Id.
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`at 7:49-51.
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`61.
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`The alleged inventive concept embodied in the independent claims is
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`clearly illustrated in Figures 4(H) and 4(J):
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
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`SAMSUNG-1001, 552 Patent at Figure 4(H)
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`
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`
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`SAMSUNG-1001, 552 Patent at Figure 4(J)
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`62. Figures 4(H) and 4(J) illustrate “a cross-sectional planar side view of
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`a series of gates encapsulated with insulating material, an etch stop layer overlying
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`the insulating material, a distinct planarized insulating blanket layer overlying the
`
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`Petition for Inter Partes Review of 6,784,552
`Ex. 1003 (“Fair Decl.”)
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`etch stop layer,” a photoresist patterning layer 455, and contact openings 460 to the
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`diffusion regions 405. Id. at 9:27-32, 9:41-45. In the figure, a conductive layer
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`corresponding to the gate electrode 415 is deposited by low pressure CVD and was
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`encapsulated by the oxide layer 420. Id. at 10:31-65. Region 405 is a conductive
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`region formed in the substrate to create the source and drain diffusion regions. Id.
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`at 10:35-36. Over the oxide layer 420 is deposited an etch stop layer of silicon
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`nitride, 440. Id. at 11:63-66. On the etch stop layer 440 is