OUI Reference: 16820.P097
`
`APPLICATION FOR UNITED STATES PATENT
`
`FOR
`
`METHOD FOR ELIMINATING LATERAL SPACER
`EROSION ON ENCLOSED CONTACT TOPOGRAPHIES
`DURING RF SPUITER CLEANING
`
`-=
`
`·:;
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`Inventors:
`
`JAMES E. NULTY
`CHRJSTOPHER J. PETTI
`
`Prepand by:
`
`BLAKELY SOKOLOFr TA Yl..OR & ZAFMAN
`12400 Wilshire Boulevard
`Seventh Floor
`Los Angeles, CA 90025
`(310} 207-3800
`
`I hereby certify that this correspondence is
`bein g deposited with the United States Posta l
`Service as Express Mai l (Label No: I~ IS' to. I'> '1 (..') 'L
`in an envelope addressa:l to: Commissioner of Patents
`~ngton, D.C 20231 o::z-/~~~~ J'l~
`
`Name
`
`Da~
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`Case No. IPR2016-00782
`DSS.2003.001
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`Fjeld of the Invention:
`
`The invention relates to semiconductor device processes, and more
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`particularly, to improved methods for etching openings in insulating layers and a
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`5
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`semiconductor device with well defined contact openings.
`
`Background of the Invention
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`In the fabrication of semiconductor devices, numerous conductive device
`
`regions and layers are formed in or on a semiconductor substrate. The conductive
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`regions and layers of the device are isolated from one another by a dielectric.
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`10
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`Examples of dielectrics include silicon dioxide, Si02, tetraethyl orthosilicate glass
`
`("TEOS"), silicon nitrides, SixNy, silicon oxynitrides, SiOxNy(Hz), and silicon
`
`dioxide/silicon nitride/silicon dioxide ("ONO"). The dielectrics may be grown, or
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`may be deposited by physical deposition (e.g., sputtering) or by a variety of chemical
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`,,:_
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`deposition methods and chemistries (e.g., chemical vapor deposition ("CVD")).
`
`15 Additionally, the dielectrics may be undoped or may be doped, for example with
`
`boron, phosphorous, or both, to form, for example, borophosphosiJicate glass
`
`("BPSG"), phosphosilicated glass ("PSG"), and borophosphosilicate tetraethyl
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`orthosilicate glass ("BPTEOS'').
`
`r 2~ moke opening' in e dide<"io to ollow fm <Onto<\ to undedying <egion> 0< loye<>.
`
`~ At sev al stages of the fabrication of semiconductor devices, it is necessary to
`
`Generally, an opening hrough a dielectric exposing a diffusion region or an
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`opening through a dielect ·c layer between polysilicon and the first metal layer is
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`called a "contact opening", w · e an opening in other oxide layers such as an
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`opening through an intermetal di ectric layer is referred to as a "via". For purposes
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`of the c~ed invention, henceforth "contact opening" or "contact region" will be
`used to:~:3~ contact openings and/or via. The opening may expose a device
`region within th\~silicon substrate, such as a sou<ee oc dcoin, oc may expose some
`other layer or stru
`re, for example, an underlying metallization layer, local
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`5
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`interconnect layer, or
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`ucture such as a gate. After the opening has been formed
`
`exposing a portion of the egion or layer to be contacted, the opening is generally
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`cleaned with a sputter etch, e.g., a Radio-Frequency ("RF") sputter etch, and then the
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`opening is filled with a cond ~ive material deposited in the opening and in
`electrical contact with the undeds_rggion or la}'.er_~
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`10
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`To form the openings a patterning layer of photoresist is first formed over the
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`dielectric layer having openings corresponding to the regions of the dielectric where
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`the dielectric layer openings are to be formed. In most modern processes a dry etch
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`is then performed wherein the wafer is exposed to a plasma, formed in a flow of one
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`or more gases. Typically, one or more halocarbons and I or o/ne or more other
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`15
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`halogenated compounds are used as the etchant gas. For example, CF4, CHF3 {Freon
`
`23), SF6, NF3, and other gases may be used as the etchant gas. Additionally, gases
`such as 02, Ar, N~ and others may be added to the gas flow. The particular gas
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`mixture used will depend on, for example, the characteristics of the dielectric being
`
`etched, the stage of processing, the etch tool being used, and the desired etch
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`20
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`characteristics, i.e., etch rate, sidewall slope, anisotropy, etc.
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`Many of the etch characteristics are generally believed to be affected by
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`polymer residues that deposit during the etch. For this reason, the fluorine to
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`carbon (F /C) ratio in the plasma is considered an important determinant in the etch.
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`In general, a plasma with a high F !C ratio will have a faster etch rate than a plasma
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`25 with a low F/C ratio. At very low rates, i.e., high carbon content, polymer
`
`deposition occurs and etching ceases. The etch rate as a function of the F /C ratio is
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`typically different for different materials. The difference is used to create a selective
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`etch, by using a gas mixture that puts the F /C ratio in the plasma at a value that
`
`leads to etching at a reasonable rate for one material, and that leads to no etching or
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`polymer deposition for another. For example, an etch.ant that has an etch rate ratio
`
`s
`
`or a selectivity ratio of two to one for silicon nitride compared to silicon dioxide is
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`an effective stripper of silicon nitride from the semiconductor substrate, because it
`
`will selectively strip silicon nitride over silicon dioxide on a substrate surface. An
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`etchant that has an etch rate ratio or a selectivity ratio of 0.85 to one for silicon
`
`nitride compared to silicon dioxide is not considered an effective stripper of silicon
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`10
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`nitride from the semiconductor substrate because the etchant will not effectively
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`strip silicon nitride to the exclusion of silicon dioxide.
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`The selectivity of the etch process is a useful parameter for monitoring the
`
`process based on the etch rate characteristic of the particular etchant. As noted
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`above, particular etchants or etchant chemistries attack different materials at
`
`15
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`different etch rates. With respect to dielectrics, for example, particular etchants
`
`attack silicon dioxide, BPTEOS, TEOS, and silicon nitride dielectrics at different rates.
`
`To make openings in a substrate comprising a contact region surrounded by
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`different dielectric layers, e.g., a dielectric layer of TEOS surrounded by a dielectric
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`layer of silicon nitride, a process will utilize different etchants to make openings
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`20
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`through the different dielectrics. Thus, the different etch rates of particular dielectric
`
`layers for an etchant may be used to monitor the creation of an opening through a
`
`dielectric layer.
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`Further, by adjusting the feed gases, the taper of the sidewall in the etched
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`opening of the dielectric can be varied. If a low sidewall angle is desired, the
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`25
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`chemistry is adjusted to try to cause some polymer buildup on the sidewall.
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`Conversely, if a steep sidewall angle is desired, the chemistry is adjusted to try to
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`/ prevent polymer buildup on the sidewall. Varying the etch gas pressure, for
`
`example, has a significant effect on the shape of the opening. This is because the
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`etchant ions generally arrive in a direction perpendicular to the substrate surface,
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`and hence strike the bottom surfaces of the urunasked substrate. The sidewalls of
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`5
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`etched openings, meanwhile, are subjected to little or no bombardment. By
`
`increasing the pressure of the etch gas, the bombardment directed toward the
`
`sidewalls is increased; by decreasing the pressure of the etch gas, the bombardment
`
`directed toward the sidewalls is decreased. The changing of the etch chemistry is
`
`also directly related to sdectivity. Etchants that provide a near 90° sidewall angle are
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`10
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`generally not highly selective while highly selective etches typically produce a
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`sloped sidewall.
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`Following the dielectric etch(es) and prior to any conductive material
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`deposition in a contact region, native oxide on top of the conducting layers in the
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`contact region is removed or cleaned through a non-chemical sputter etch, e.g., an
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`15
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`RF sputter etch. In addition to alleviating the contact region of native oxide, the
`
`sputter etch can erode any insulating dielectric layer or layers. Thus, the parameters
`
`of the sputter etch must be carefully monitored so as not to excessively erode the
`
`insulating dielectric layer(s) and expose other underlying conductive materiaL
`
`Exposing insulated conductive material adjacent to the conductive material in the
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`20
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`contact region results in poor quality contacts or a short circuit through the
`
`underlying conductive material. For a thorough discussion of oxide etching, see S.
`
`Wolf and R.N. Tauber, Silicon Processing for the VLSI Era Vol. 1, pp. 539-85 (1986).
`
`. ~ The preced'ili discussion focused on the making of openings, e.g., contact
`"}~}(
`! v ~
`Th
`.
`. 1
`.
`. d' I
`.
`. 1
`.
`d
`b
`· ope rungs, tn 1e ectn matena on a serrucon uctor su strate.
`e same pnnCip es
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`25
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`are used in constructin device regions with a dielectric layer or layers. As
`
`geometries shrink, the for
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`ing of discreet devices on a semiconductor substrate
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`Specialized deposition and etching techniques permit
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`rating speeds, and reduced production costs.
`
`A typical metal oxide semiconductor (MOS) transistor, e.g., NMOS or PMOS
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`5
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`transistor, generally includes source/ drain regions in a substrate, and a gate
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`electrode formed above the substrate between the source/drain regions and
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`separated from the substrate by a relatively thin dielectric. Contact structures can be
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`inserted to the source/drain regions and interlays can overlie the contact structures
`
`and connect neighboring contact structures. These contact structures to the
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`10
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`diffusion region are isolated from the adjacent gate by dielectric spacer or shoulder
`
`portions. The dielectric spacer or shoulder portions also isolate the gate from the
`
`diffusion region.
`
`'\;!::¥
`~,
`
`()
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`Conventional contact structures limit the area of the diffusion region, because
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`the contact hole is aligned to these regions with a separate masking step, and extra
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`15
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`area must be allocated for misalignment. Proper alignment is necessary to avoid
`
`shorting the contact structure to the gate or the diffusion well. The larger contact
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`area means a smaller density of elements on a structure. The larger contact area is
`
`also responsible for increased diffusion-to-substrate junction capacitance, which
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`limits device speed.
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`20
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`A self-aligned contact eliminates the alignment problems associated with .
`
`conventional contact structures and increases the device density of a structure. A
`
`self-aligned contact is a contact to a source or drain diffusion region. A self-aligned
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`contact is US€ful
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`in compact geometries because it can overlap a conducting area to
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`which it is not supposed to make electrical contact and can overlap the edge of a
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`25
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`diffusion region without shorting out to the well beneath. Consequently, less
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`contact area is needed and gates or conductive material lines, e.g., polysilicon lines,
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`can be moved closer together allowing more gates or lines on a given substrate than
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`traditional contacts.
`
`e 1 illustrates a self-aligned contact between two gate structures. Figure
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`anar top view of the contact. Figure l(B) is a planar cross-sectional view
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`ed contact between a pair of gates taken through line l(B) of Figure
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`l(A). Figure 1 C) is a planar cross-sectional view of a self-aligned contact between a
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`pair of gates tak
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`through line 1(C) of Figure l(A).
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`The self-align
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`contact is a contact to a source or drain diffusion region (n+
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`10
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`n overlap the edge of the diffusion region 140 without
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`shorting out to the well b eath the diffusion region 140. This can be seen most
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`illustratively through Figure C). In Figure 1(C), the contact 130 does not lie directly
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`in the diffusion region 140, but misaligned and slightly overlaps the field oxide.
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`In this illustration, the self-aligned ontact is not directly over the diffusion region
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`15
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`but extends over (i.e., overlaps) a wei
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`rtion 170. The self-aligned contact does not
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`short to the well portion 170 because th self-aligned contact is separated from the
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`well170 by the field oxide.
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`The self-aligned contact 130 is separate
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`from a conducting polysilicon layer
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`110 by an encapsulating dielectric layer 120 such
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`at the contact 130 can also overlap
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`20
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`the polysilicon layer 110 without making electrical
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`ntact to the layer 110 or gate.
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`The polysilicon layer 110 is separated from the source drain diffusion region 140 by
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`a dielectric spacer or shoulder 150 of the same or differe t dielectric material as the
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`dielectric layer 120 directly above the conducting polysilic
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`A distinct dielectric etch stop layer 125 overlies the enca sulating dielectric
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`25
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`layer 120. The etch stop layer 125 permits subsequent etching of ;he substrate
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`\
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`without cis of exposing the device structures and layers because the device
`
`structuring and
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`ers are protected from excessive etching by the etch stop layer.
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`The diffusion contac · self-aligning because the structure can be etched to the
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`substrate over the source
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`ain diffusion region 140 while the dielectric spacer 150
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`5
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`protects the polysilicon layer
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`0. Even if a photoresist that protects the polysilicon
`
`layer 110 from the etchant is misa ·~ed with respect to the polysilicon layer 110, the
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`dielectric spacer 150prevents shorts t~e polysilicon layer 110 when the contact 130
`
`is provided for the diffusion region 140.
`
`).
`
`',:
`
`Ph
`10
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`~ ;: ~ e current practice with respect to forming contact regions, particularly self-
`r.
`
`aligned c
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`tact regions, that are in electrical contact with gates, interconnect lines, or
`
`es in small feature size structures utilize etchants with high selectivity
`
`to protect uncle
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`ing regions, like the etch stop layer and the first insulating layer.
`
`Figure 2 demonstr es a typical prior art process of forming a self-aligned contact
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`region adjacent to a ga
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`. In Figure 2(A), a gate oxide layer 210 is formed on a
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`~"'-'
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`15
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`substrate 200 with a cond cting layer, for example a polysilicon layer 220, overlying
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`the gate oxide layer 210, and n insulating layer, for example a TEOS layer 230,
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`overlying the polysilicon layer
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`0. Adjacent to the polysilicon layer is a contact
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`opening regjon 270. The polysilico"\ayer 220 is separated from the contact region
`270 by an insulating spacer portion, f~~xample a TEOS spacer portion 235. A
`
`20
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`separate insulating or etch stop layer, fo>,xample a silicon nitride layer 240 overlies
`the TEOS layer 230 and the contact region 2~\ A blanket layer, for example a doped
`insulating layer like a BPTEOS layer 250, plana
`overlies the etch stop layer 240.
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`A layer of photoresist material 280 overlies t
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`planarized BPTEOS layer 250
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`to expose the contact opening 270. In Figure 2(A), a co tact opening 270 has been
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`25
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`opened through the BPTEOS layer 250. The etchant utili d to make the opening
`
`had a high selectivity toward BPTEOS relative to silicon ni {Je. When the contact
`\
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`openin was through the BPTEOS material, the etchant did not etch or did not
`
`effectively ch the silicon nitride layer 240 material. Hence the description of the
`
`silicon nitride 1 er 240 as an etch stop layer. The silicon nitride etch stop layer
`
`protected the un~-r.ing TEOS layer so that the polysilicon remains completely
`encapsulated. ~
`
`5
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`~ igure 2(A) illustrates an etch 260 to remove the silicon nitride etch stop layer
`f\}(J;Y240. In t
`
`etch illustrated in Figure 2(A), a high selectivity etch toward silicon
`
`{ v-
`
`nitride relati e to the underlying TEOS layer 230 material is practiced to efficiently
`
`etch the silicon
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`'tride layer and to protect the underlying TEOS layer 230 from the
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`~ .. ,'
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`10
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`etchant. An exam le of a high selectivity etch recipe to effectively strip silicon
`the TEOS layer is 30 scan CHF3 and 30 seem 02 at 60 mtorr
`
`nitride as compared
`
`and 100 watts of power. The result of the high selectivity etch is illustrated in Figure
`
`2(B).
`
`Figure 2(B) shows that
`
`e silicon nitride selective etch effectively removed
`
`15
`
`silicon nitride 240 from the conta opening 270. The selective etch for silicon
`
`nitride compared to TEOS material, owever, left the TEOS layer 230 with a spacer
`
`portion 235 wherein the spacer portion · sloping or tapered toward the contact
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`opening. This result follows even where
`
`substantially rectangular as in Figure 2(A).
`
`e properties of the highly selective
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`20
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`etch of the overlying etch stop layer will transf m a substantially rectangular spacer
`
`into a sloped spacer. F_igU.t:.~--~(B) presents a polys· ·con layer 220 encapsulated in a
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`TEOS layer 230 with a spacer portion 235 adjacent to
`
`e contact opening 270, the
`
`spacer portion 235 having an angle 290 that is less than 5°.
`
`In addition to providing stopping points or selectivi between materials, the
`
`25
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`use of high selectivity etches to form sloped spacer portions is
`
`e preferred practice
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`because the slo ed shape will result in good step coverage by the metal that is
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`deposited into it. The filling of contact openings or gaps (i.e., gap fill) is an
`
`important considera ·on because it relates directly to the reliability of a device. If an
`
`5
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`opening is not complet l~ filled with a insulative material, for example, and a gap is
`created, a subsequent con~\!ctive material deposit can fill the gap whlch can lead to
`shorting. Sloped contact op~gs are easier to completely fill than boxy structures
`because the transition between oped structures and openings is smooth compared
`
`to the abrupt transitions between 1:l xy structures and openings. Because of concerns
`
`for complete gap fill and good step co erage, industry preference is for sloped spacers
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`10
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`and planar deposition layers similar to t
`
`t shown in Figure 2(b).
`
`;~.. ~~~( e g, on
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`.
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`gap. The
`
`nee the contact opening is made, the opening is cleaned with a sputter etch,
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`sputter etch, before conductive material is added to fill the opening or
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`sputter etch that is used to clean the contact opening in the process
`
`described abov will attack and erode a portion of the insulating spacer surrounding
`
`the conducting po tion and adjacent to the contact region. Figure 3 presents a prior
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`te and a contact region undergoing an RF sputter etch. In
`
`Figure 3, a gate oxide 31
`
`is formed on a substrate 300 with a polysilicon layer 320
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`overlying the gate oxide 3
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`and an insulating layer, for example a TEOS layer 330
`
`overlying the polysilicon !aye 320. A distinct insulating layer, for example a silicon
`
`20
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`nitride etch stop layer 340, over! s the TEOS layer 330 and this etch stop layer 340 is
`
`covered by a third insulating layer, or example a BPTEOS blanket layer 350.
`
`Adjacent to the gate is a contact regia 360. An etch of the silicon nitride etch stop
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`Ia yer 340 with a high selectivity etch for ilicon nitride relative to the underlying
`
`TEOS layer material produced a gate with a loping or tapered spacer portion 370 of
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`25
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`TEOS material, illustrated in ghost lines.
`
`clean the contact region 360.
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`though brief and designed to clean the contact region, the RF sputter etch
`
`a portion of the insulating TEOS spacer. The dynamics of the sputter etch .
`
`are that it p
`
`eeds vertically, directing high-energy particles at the contact region
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`pered spacer portion adjacent the polysilicon and separating the
`
`s
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`polysilicon from t
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`diffusion region is struck by the high-energy particles of the RF
`
`e the spacer portion 370 is sloping or diagonal, a significant
`
`surface area portion of
`
`spacer portion 370 is directly exposed to the high-energy
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`etch 380. Further, with sloping spacers, or spacers
`
`having an angle relative to th ubstrate surface of less than 85° the vertical portion
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`10
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`of the dielectric layer ((i.e., that p
`
`tion above the polysilicon gate) decreases much
`
`less than the diagonal portion of the
`
`acer. In terms of measuring TEOS material
`
`removal during the RF sputter etch in Fi
`
`e 3, the difference between dJ and d2 is
`
`greater than the difference between VJ and
`
`. Thus, in conventional prior art self-
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`' J
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`aligned contact structures, the diagonal thickne s of the TEOS spacer, rather than the
`
`15
`
`vertical thickness of the TEOS layer, determines
`
`e minimum insulating layer
`
`thickness for the gate.
`
`For gate structures havin minimum diagonal insulative spacer portions of
`500 A or less, the result of the sput retch 380 is that the sputter etch 380 laterally
`
`erodes the diagonal portion of the TE
`
`layer 370 adjacent to the contact region to a
`
`20
`
`point where the polysilicon 320 is no Ion er isolated from the contact region 360 by
`
`an insulating layer. In that case, there is a
`
`ort circuit through the underlying
`
`conductive material when the contact openin
`
`is filled with conductive material.
`
`This result follows because the conventional RF
`utter etch utilized for cleaning
`the contact region results in an approximately 200-5 0 A loss of the spacer materiaL
`
`25
`
`Further, process margins generally require that the de · ce spacer have a final
`minimum thickness (after all etches, doping, and deposits of at least 500 A. Thus,
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`to eliminate alig
`
`ent sensitivity for conventional small feature size structures,
`
`ontact structures, requires a final (i.e., at the time of contact
`including self-aligne
`deposition) minimum ins ating spacer of more than 500 A and preferably on the
`order of 1000-1500 A or great
`
`to fulfill requirements for an adequate process
`
`5 margin, complete gap fill, and de ·ce reliability.
`
`T construct structures having a minimum insulative spacer portion of more
`than 500 R directly effects the number of structures that can be placed on a device,
`such as a chl . The construction of structures having a minimum insulative spacer
`than 500 A requires that the pre-etch-stop-etch spacer be bigger or
`
`10
`
`thicker to yield a effective spacer after the etching processes. In such cases, the
`
`structures must be parated a distance such that the contact area opening is
`
`sufficient enough for n effective contact. This spacing requirement directly limits
`
`the number of structure
`
`that can be included on a device. In small feature size
`
`structures, particularly str
`
`tures utilizing sell-aligned contacts, the width of contact
`
`15
`
`openings is approximately 0. microns at the top of the planarized layer and 0.2
`
`microns at the base of the conta t opening. Figure 3 indiCates the difference in
`
`contact opening widths for the sa e contact in prior art structures. WJ represents
`layer and wz represents the width at the base
`of the contact opening. Further, an asp ct ratio can be defined as the height of a
`
`the width at the top of the planarize
`
`20
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`structure (field oxide plus conductive lay plus first insulative layer plus etch stop
`
`layer, if any) relative to the width of the ba of a contact opening (i.e., the distance
`
`between adjacent spacers). Typical aspect ratio for self-aligned contact structures
`
`target ratios of 1.0-2.4. This prior art range is not ch.ievable with any device
`
`reliability. To achieve aspect ratios of 1.0-2.4 requir s minimum spacer portions of
`less than 1000 A and preferably on the order of 500 A.
`
`s noted above, the
`
`25
`
`minimum spacer portions required for aspect ratios of 1. -2.4 cannot withstand the
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`sputter etch an~ will result in the exposure of the underlying polysilicon ~ate and
`short circuiting ~ the contact.
`
`There is a need for cost effective structures wherein the individual devices
`
`are as close together as possible while maintaining device reliability and an adequate
`
`s
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`process margin and assuring comp~ete gap fill. There is a need for a device and for a
`
`process to manufacture such a device whereby there is provided a contact opening
`
`with no alignment sensitivity relative to a gate electrode or other structure and
`
`whereby the gate electrode does not fall within the contact opening but remains
`
`,,,
`~~
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`10
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`isolated from the contact opening by an insulating layer. The process must be
`compatible with gate electrode insulating spacers of less than 500 A.. The device
`
`resulting from the needed process should be capable of maintaining high quality
`
`contacts between the conductive material in the contact region and the adjacent
`
`;'"'
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`conductive gate or other structure.
`
`JCS / WfB / mp
`
`-12-
`
`16S20.P097
`
`Case No. IPR2016-00782
`DSS.2003.013
`
`

`
`SUMMARY OF THE INYENTION
`
`(
`
`f;9.."-> ~'e invention relates to a process for minimizing lateral spacer erosion of an
`/;;;;;ulating ~e' on an enclosed contact <egion is di'closed and a devke including a
`contact ope~with a small alignment tolerance relative to a gate electrode or
`e process provides high quality contacts between a conductive
`other structure.
`
`5
`
`material in the con act region and a device region, such as a source or drain, or some
`
`other layer or stru~e. The process comprises the well known step of forming a
`conductive layer on th~semiconductor body adjacent a contact region. This is
`
`followed by the forming\f a first insulating layer adjacent said conductive layer and
`
`10
`
`the contact region. A sele1d area is masked with photoresist and the first
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`insulating layer and the con1ctive layer are etched to form a device structure, such
`
`as a gate, adjacent the contact re ion. Next, insulating lateral spacers are added to
`
`the device structure to isolate the onductive portion of the device. The insulating
`
`spacers are etched so that the devic comprises an insulating layer overlying a
`
`15
`
`conductive layer with a lateral spacer ortion adjacent the contact region wherein
`
`the spacer portion has a substantially r~angular profile. A distinct insulating layer
`or etch stop layer is then formed adjacen~ the first insulating layer and over the
`contact region. A third insulating layer or ~nket layer is then optionally formed
`over the etch stop layer. The blanket layer ma~r may not be planarized.
`
`20
`
`If a blanket layer is included, an etchant is utilized to etch a contact opening
`
`through the exposed portion of the blanket layer to the etch stop layer. Next, a
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`second etch or etch-stop etch is performed to remove the etch stop layer material
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`from the contact region. The etch-stop etch is also almost completely anisotropic,
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`meaning that the etchant etches in one direction-in this case, vertically (or
`
`25
`
`perpendicular relative to the substrate surface) rather than horizontally. The etch
`
`)CS/WTD/mp
`
`-13-
`
`16820. P097
`
`Case No. IPR2016-00782
`DSS.2003.014
`
`

`
`removes the etch stop insulating layer and retains the substantially rectangular
`
`lateral spacer portion of the first insulating layer. The anisotropic etch etches
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`primarily the exposed etch stop material that lies normal to the direction of the etch.
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`Thus, the etch removes the etch stop material covering the area of the contact
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`5
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`region but does not significantly etch the etch stop material adjacent to the spacer(s).
`
`The etch stop layer on the spacer adds dielectric thickness between the conductive
`
`layer and any contacting conductor. In general, the etching conditions utilized for
`
`the etch-stop etch have a low selectivity for etching the etch stop layer compared to
`
`the underlying insulating material.
`
`10
`
`The etch-stop etch may be followed by a sputter etch to clean the contact
`
`region. Unlike prior art processes whereby the sputter etch erodes the underlying
`
`sloping lateral spacer portion of the first insulating layer adjacent to the conducting
`
`layer, the sputter etch does not significantly erode the substantially rectangular
`
`lateral spacer of the first insulating layer, thus allowing the conductive layer of the
`
`15
`
`device structure to remain completely isolated or insulated by a spacer comprised of
`
`the first insulating layer and some etch stop layer material.
`
`The str.ucture contemplated by the invention is an effective device for small
`
`feature size structures, particularly self-aligned contacts. The structure consists of
`
`first and second conducting layers spaced apart by a region with an area defined in
`
`20
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`the substrate; an insulating layer encapsulating each conductive layer, wherein the
`
`insulating layer includes lateral spacer portions; and an etch stop layer adjacent the
`
`insulating layer and over the first and second conducting layers. The invention
`
`contemplates that the structure region has a first width between the first and second
`
`conducting layers, and a second width between the lateral spacer portions of the
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`25
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`insulating layer adjacent to the first and second conducting layers, wherein the
`
`region has an aspect ratio of 1.0-2.4. The aspect ratio is defined as the height of the
`
`JCS/VVTB/mp
`
`-14-
`
`16820.?097
`
`Case No. IPR2016-00782
`DSS.2003.015
`
`

`
`apparatus relative to the second width of the region. Thus, the invention
`
`contemplates larger contact openings for effective contacts, reduced device feature
`
`size, and increased device density, while maintaining aspect ratios similar to larger,
`
`less dense devices in the prior art. The invention further contemplates that the
`structure has a minimum insulating layer thickness of 400 A and that this
`
`5
`
`minimum thickness is determined by the thickness of the insulating layer deposited
`
`vertically on the structure.
`
`The device is capable of maintaining high quality, reliable contacts between
`
`the conductive material in the contact region and the underlying device region,
`
`\,?
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`10
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`such as a source or drain, or some other layer or structure. The device contemplates
`
`minimum contact opening base widths of 0.2 microns and minimum contact
`
`opening widths of 0.5 microns when measured from the top of a planarized layer,
`
`and aspect ratios (i.e., height of structure including the etch stop layer relative to the
`
`width of the base of a contact opening between the spacers) on the order of 1.0-2.4.
`
`15
`
`Additional features and benefits of the invention will become apparent from
`
`the detailed description, figures, and claims set forth below.
`
`)CS/ 'v'v'TB / mp
`
`-15-
`
`16820.?097
`
`Case No. IPR2016-00782
`DSS.2003.016
`
`

`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The features, aspects, and advantages of the present invention will become
`
`more thoroughly apparent from the following detailed description, appended
`
`claims, and accompanying drawings in which:
`
`s e;q "->. Fi
`~ ~anar top vi
`
`e 1 is a planar view of a self-aligned contact to diffusion. Figure l(A) is a
`
`of a self-aligned contact. Figure l(B) is a cross-sectional planar side
`
`['
`
`view of a self-ali ed contact to diffusion through line l(B) of Figure l(A). Figure
`
`al planar side view of a self-aligned contact to diffusion
`
`~'
`
`through line l(C) of Fi ure l(A).
`
`10
`
`Figure 2 is a cross-se tiona! side view of the formation of a prior art contact
`
`opening formation. Figure 2(
`
`illustrates a high selectivity etch of an etch stop
`
`insulating layer, and Figure 2(B)
`
`ustrates the results of that etch.
`
`Figure 3 is a cross-sectional side view of the formation of a prior art contact
`
`opening formation during a sputter clea ·ng etch.
`
`15
`
`Figure 3 is a cro~ctional view of an example of a semiconductor device
`during fabrication upon~hich the invention may be practiced.
`
`Figure 4 presents a cross-sectional planar side view of the preparation of a
`
`series of gates on a semiconductor substrate surface.
`
`Figure 4(A) illustrates a cross-sectional planar side view of an iruulating layer
`
`20
`
`adjacent to a conducting layer, both layers overlying two diffusion regions.
`
`Figure 4(B) illustrates a cross-sectional planar side view of a series of gates
`
`consisting of insulating material adjacent conducting material.
`
`JCS/\-VTB/mp
`
`·16-
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`16820.PQ97
`
`Case No. IPR2016-00782
`DSS.2003.017
`
`

`
`Figure 4(C) illustrates a cross-sectional planar side view of the deposition of
`
`additional insulating material over the series of gates, the additional insulating
`
`material to be