Trials@uspto.gov
`571-272-7822
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`Paper 18
`Entered: September 20, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00782
`Patent 6,784,552 B2
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`571-272-7822
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`Paper 18
`Entered: September 20, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00782
`Patent 6,784,552 B2
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`IPR2016-00782
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`I. BACKGROUND
`A. Introduction
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`Samsung Electronics Co., Ltd. (“Petitioner”) challenges the patentability of
`claims 1–12 (the “challenged claims”) of U.S. Patent No. 6,784,552 B2
`(Ex. 1001, “the ’552 patent”), owned by DSS Technology Management, Inc.
`(“Patent Owner”). The Board has jurisdiction under 35 U.S.C. § 6. This
`Final Written Decision is entered pursuant to 35 U.S.C. § 318(a) and
`37 C.F.R. § 42.73. With respect to the grounds instituted in this trial, we
`have considered the papers submitted by the parties and the evidence cited
`therein. For the reasons discussed below, we determine Petitioner has
`shown by a preponderance of the evidence that claims 1–12 of the ’552
`patent are unpatentable.
`
`B. Procedural History
`On March 18, 2016, Petitioner filed a Petition (Paper 1, “Pet.”)
`requesting an inter partes review of claims 1–12 (the “challenged claims”)
`of U.S. Patent No. 6,784,552 B2 (Ex. 1001, “the ’552 patent”). Petitioner
`also filed the Declaration of Dr. Richard Fair (Ex. 1003, “Fair Decl.”) in
`support of the Petition. Patent Owner did not file a Preliminary Response.
`On September 23, 2016, we instituted an inter partes review of claims 1–12
`of the ’552 patent based on the following specific grounds (Paper 6, “Dec.
`on Inst.,” 27).
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`Claim(s) Challenged Statutory Basis
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`1, 2, 4–12
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`3
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`1, 2, 4–7
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`3
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`Reference(s)
`
`Kuesters1
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`Kuesters and Havemann2
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`Kuesters and Heath3
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`Kuesters, Heath, and Havemann
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`§ 102(b)
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`§ 103(a)
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`§ 103(a)
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`§ 103(a)
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`After institution, Patent Owner filed a Patent Owner Response (Paper
`10, “PO Resp.”), to which Petitioner filed a Reply (Paper 12, “Pet. Reply”).
`Petitioner also filed the Declaration of Dr. Richard Fair in Support of
`Petitioner’s Reply (Ex. 1014, “Fair Reply Decl.”). An oral hearing was held
`on June 20, 2017. A transcript of the hearing is included in the record as
`Paper 17 (“Tr.”).
`
`C. Related Proceedings
`According to the parties, the ’552 patent is the subject of the
`following patent infringement cases: DSS Tech. Mgmt., Inc. v. Samsung
`Elec. Co., Ltd., Case No. 15-cv-690 (E.D. Tex.); DSS Tech. Mgmt., Inc. v.
`Intel, Corp., Case No. 15-cv-130 (E.D. Tex.); DSS Tech. Mgmt., Inc. v. SK
`Hynix, Inc., Case No. 15-cv-691 (E.D. Tex.); and DSS Tech. Mgmt., Inc. v.
`Qualcomm, Inc., Case No. 15-cv-692 (E.D. Tex.). Pet. 2; Paper 5, 2–3.
`
`1 Kuesters et al., Self Aligned Bitline Contact For 4 Mbit dRAM,
`PROCEEDINGS OF THE FIRST INTERNATIONAL SYMPOSIUM ON ULTRA LARGE
`SCALE INTEGRATION SCIENCE AND TECHNOLOGY 640–49 (1987) (“Kuesters”)
`(Ex. 1005).
`2 U.S. Patent No. 5,482,894 (Jan. 9, 1996) (“Havemann”) (Ex. 1006).
`3 U.S. Patent No. 4,686,000 (Aug. 11, 1987) (“Heath”) (Ex. 1007).
`3
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`The ’552 patent was also the subject of instituted trial proceedings
`Intel Corp. v. DSS Tech. Mgmt., Inc., Cases IPR2016-00287 and IPR2016-
`00288, in which we have entered final written decisions finding all of the
`claims of the ’552 patent unpatentable.4 Intel Corp. v. DSS Tech. Mgmt.,
`Inc., Cases IPR2016-00287 and IPR2016-00288 (PTAB June 1, 2017)
`(Paper 25 in both cases). Patent Owner has timely filed a Notice of Appeal
`in each of Cases IPR2016-00287 and IPR2016-00288 (Paper 28 in each
`case).
`
`II. THE ’552 PATENT
`A. Described Invention
`The ’552 patent describes a process of semiconductor device
`fabrication and a structure of a semiconductor device having “substantially
`rectangular” lateral insulating spacers adjacent to gate electrodes. Ex. 1001,
`Abstract. The ’552 patent defines the term “substantially rectangular” to
`mean that “a side of the spacer has an angle relative to the substrate surface
`of more than 85°.” Id. at col. 8, ll. 40–42. Figure 4(D) of the ’552 patent is
`reproduced below.
`
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`4 Cases IPR2016-01311 and IPR2016-01314 have been joined with
`IPR2016-00287 and IPR2016-00288, respectively.
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`Figure 4(D) illustrates a cross-sectional view of a series of gates 415 (also
`called conducting layers or polysilicon layers) completely encapsulated in
`insulating material 420, e.g., TEOS (tetraethyl orthosilicate glass), where
`spacers 435 of the insulating material adjacent to the gates have substantially
`rectangular profiles. Id. at col. 9, ll. 9–13; col. 11, ll. 40–46. As shown in
`Figure 4(D), gates 415 are insulated from sources or drains 405 by insulating
`dielectric layers 410. See id. at col. 10, ll. 49–50. The ’552 patent describes
`a process of making high quality contacts to the sources or drains, such as
`“self-aligned” contacts, by etching structures over substrate 400 and sources
`or drains 405. Id. at col. 7, ll. 19–22; col. 8, ll. 4–6.
`Figure 4(I) of the ’552 patent is reproduced below.
`
`
`Figure 4(I) illustrates additional structures deposited and etched over the
`structure described in Figure 4(D), such as second dielectric layer 440
`(called etch stop layer), blanket layer 450, and photoresist mask layer 455.
`Id. at col. 9, ll. 33–39; col. 11, ll. 63–65; col. 12, ll. 34–42. According to the
`’552 patent, etch stop layer 440, e.g., silicon nitride layer 440, depicted in
`Figure 4(I) is distinct or different from the underlying TEOS insulating
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`layer. Id. at col. 12, ll. 10–11. The etch stop layer protects the underlying
`TEOS layer when blanket layer 450 made of BPTEOS5 is etched away to
`create contact openings 460 and 465 above source or drain 445. See id. at
`col. 12, ll. 36–42; col. 4, ll. 41–59.
`A second etch is then performed to remove etch stop layer 440
`covering source or drain 445 in contact openings 460 and 465. Id. at col. 12,
`ll. 48–52; col. 7, ll. 43–45. The ’552 patent describes that the second etch is
`“almost completely anisotropic,” which means that the etchant etches in the
`vertical direction, or perpendicular relative to the substrate surface. Id. at
`col. 7, ll. 45–48; col. 12, ll. 55–58. Hence, the etch removes the etch stop
`material covering the area of the contact openings or contact regions 460 and
`465, but does not significantly etch the etch stop material adjacent to the
`spacer portions 435. Id. at col. 7, ll. 53–55; col. 12, ll. 58–61.
`
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`5 BPTEOS is an acronym for borophosphosilicate tetraethyl orthosilicate
`glass. See Ex. 1001, col. 11, ll. 6–7.
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`6
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`Figures 4(J) and 4(K) of the ’552 patent are reproduced below.
`
`
`Figures 4(J) and 4(K) illustrate the structure of the semiconductor device of
`the ’552 patent after the second etch for removing the etch stop layer from
`the contact regions 460 and 465 is completed. As shown in Figures 4(J) and
`4(K), due to the anisotropic or vertical nature of the second etch, only a
`small portion, i.e., portion 475, of the TEOS spacer portion 435 is removed
`during the etch. Id. at col. 13, ll. 6–9. Of primary significance, according to
`the ’552 patent, is that the spacer portion 435 of the TEOS insulating layer
`420 retains its substantially rectangular profile, in contrast to the
`conventional prior art method which transforms a substantially rectangular
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`spacer into a sloped spacer. Id. at col. 13, ll. 9–10; col. 7, ll. 48–51; col. 5,
`ll. 4–14.
`
`B. Illustrative Claim
`Of the challenged claims, claims 1 and 8 are independent. Claims 2–7
`depend directly or indirectly from claim 1, and claims 9–12 depend directly
`or indirectly from claim 8. Claim 1 is illustrative of the challenged claims
`and is reproduced below with the key limitation (the “angle limitation”)
`emphasized in italics:
`1. A structure, comprising:
`(a) a conductive layer disposed over a substrate;
`(b) a first insulating layer on the conductive layer:
`(c) a contact region in said first insulating layer;
`(d) at least one insulating spacer in the contact region adjacent
`to the first insulating layer; and
`(e) an etch stop material over said first insulating layer and
`adjacent to the insulating spacer, the etch stop material being a
`different material from the insulating spacer,
`wherein a side of the insulating spacer has an angle relative to
`the substrate surface that is either a right angle or an acute
`angle of more than 85°.
`
`
`III. CLAIM CONSTRUCTION
`The ’552 patent has expired. PO Resp. 15; Pet. 13. Thus, we
`construe the claims in accordance with the standard set forth in Phillips v.
`AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). See In re CSB-Sys.
`Int’l, Inc., 832 F.3d 1335, 1341 (Fed. Cir. 2016) (“[W]hen an expired patent
`is subject to reexamination, the traditional Phillips construction standard
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`attaches.”) (citing In re Rambus, 694 F.3d 42, 46 (Fed. Cir. 2012)); Black &
`Decker, Inc. v. Positec USA, Inc., 646 Fed. App’x 1019, 1024 (Fed. Cir.
`2016) (unpublished) (holding that in an inter partes review, “[c]laims of an
`expired patent are given their ordinary and customary meaning in
`accordance with our opinion in [Phillips]”). “In determining the meaning of
`the disputed claim limitation, we look principally to the intrinsic evidence of
`record, examining the claim language itself, the written description, and the
`prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips,
`415 F.3d at 1312–17).
`
`“Contact Region” and “Contact Opening”
`In the Decision on Institution, applying the Phillips standard, we
`preliminarily interpreted the terms “contact region” and “contact opening” to
`mean “contact openings or via.” Dec. on Inst. 8–9. The parties do not
`dispute the meaning of these terms in their Patent Owner Response and
`Petitioner Reply. See PO Resp. 15–16. Upon considering the complete
`record, we discern no reason to deviate from our construction, which was
`adopted from the express and unambiguous definition of the terms in the
`’552 patent (see Dec. on Inst. 8–9 (citing Ex. 1001, col. 1, ll. 38–41)), and
`maintain our construction of the terms “contact region” and “contact
`opening” as “contact openings or via.”
`No other claim terms need to be construed expressly for purposes of
`this Final Written Decision. See Wellman, Inc. v. Eastman Chem. Co., 642
`F.3d 1355, 1361 (Fed. Cir. 2011) (explaining that “claim terms need only be
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`construed ‘to the extent necessary to resolve the controversy’” (quoting
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999))).
`
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`IV. ANALYSIS OF PETITIONER’S PRIOR ART CHALLENGES
`To prevail in challenging Patent Owner’s claims, Petitioner must
`demonstrate by a preponderance of the evidence that the claims are
`unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). “In an [inter partes
`review], the petitioner has the burden from the onset to show with
`particularity why the patent it challenges is unpatentable.” Harmonic Inc. v.
`Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016) (citing 35 U.S.C.
`§ 312(a)(3) (requiring inter partes review petitions to identify “with
`particularity . . . the evidence that supports the grounds for the challenge to
`each claim”)). This burden never shifts to Patent Owner. See Dynamic
`Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir.
`2015) (citing Tech. Licensing Corp. v. Videotek, Inc., 545 F.3d 1316, 1326–
`27 (Fed. Cir. 2008)) (discussing the burden of proof in inter partes review).
`
`A. Kuesters As a Printed Publication
`In all instituted grounds in this trial proceeding, Petitioner relies on
`Kuesters (Ex. 1005) as the primary prior art reference. See Pet. 3–4.
`Petitioner contends that Kuesters is prior art to the ’552 patent under
`35 U.S.C. § 102(b) because it was available to the public at Stanford
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`University Libraries no later than October 23, 1990.6 Id. at 3 (citing
`Ex. 1010). In support of its assertion, Petitioner submits a Declaration of
`Mariellen F. Calter (Ex. 1010), who is Associate University Librarian and
`Chief of Staff at the Stanford University Libraries located in Stanford,
`California. Pet. 3; Ex. 1010 ¶ 2.
`In the Decision on Institution, upon consideration of Petitioner’s
`argument and evidence, we preliminarily determined that Petitioner has
`demonstrated sufficiently that Kuesters was available to the public by
`October 23, 1990, and, therefore, constitutes prior art to the ’552 patent
`under § 102(b). Dec. on Inst. 9–11. The parties do not dispute whether
`Kuesters qualifies as prior art in their Patent Owner Response and Petitioner
`Reply. Upon considering the complete record, we are persuaded that
`Petitioner has demonstrated by a preponderance of the evidence that
`Kuesters constitutes prior art to the ’552 patent as a printed publication
`under § 102(b).
`
`B. Level of Ordinary Skill in the Art
`The person of ordinary skill in the art is a hypothetical person who is
`presumed to have known the relevant art at the time of the invention. In re
`GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). In determining the level of
`ordinary skill in the art, various factors may be considered, including the
`types of problems encountered in the art, prior art solutions to those
`problems, the sophistication of the technology, rapidity with which
`
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`6 As noted by Petitioner, the ’552 patent claims priority to a predecessor
`application filed on December 22, 1995. Pet. 5; Ex. 1001, 1 (Related U.S.
`Application Data).
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`innovations are made, and educational level of active workers in the field.
`Id. In a given case, one or more factors may predominate. Id. In addition,
`we may be guided by the level of ordinary skill in the art reflected by the
`prior art of record. See Okajima v. Bourdeau, 261 F.3d. 1350, 1355 (Fed.
`Cir. 2001).
`Relying upon the Declaration of Dr. Richard Fair, Petitioner asserts
`that, at the time of the invention claimed in the ’552 patent, a person of
`ordinary skill in the art for the technology disclosed in the ’552 patent would
`have had a Bachelor of Science degree in electrical engineering, chemistry,
`materials science, or physics, or a closely related field, along with at least 2
`to 3 years of experience in semiconductor fabrication. Pet. 15 (citing
`Ex. 1003 ¶¶ 25–27). Patent Owner does not dispute Petitioner’s definition
`of the level of ordinary skill in the art.
`Upon considering the complete record, we are persuaded by
`Petitioner’s argument and evidence, and determine that a person of ordinary
`skill in the art at the time of the invention of the ’552 patent would have had
`a Bachelor of Science degree in electrical engineering, chemistry, materials
`science, or physics, or a related field, along with 2 to 3 years of experience
`in semiconductor fabrication.
`
`C. Anticipation By Kuesters
`Petitioner asserts that claims 1, 2, and 4–12 are unpatentable under
`35 U.S.C. § 102(b) as anticipated by Kuesters. Pet. 31–52. Petitioner
`provides detailed explanations and specific citations to Kuesters indicating
`where in the reference the claimed features are disclosed. Id. In addition,
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`Petitioner relies upon the Declaration of Dr. Richard Fair (Ex. 1003) to
`support its position. Id. Upon review of all of the parties’ papers and
`supporting evidence discussed in those papers, we are persuaded that
`Petitioner has demonstrated, by a preponderance of the evidence, that claims
`1, 2, and 4–12 are unpatentable under 35 U.S.C. § 102(b) as anticipated by
`Kuesters.
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`1. Relevant Principles of Law
`A claim is unpatentable under 35 U.S.C. § 102 only if a single prior
`art reference expressly or inherently describes each and every limitation set
`forth in the claim. See Perricone v. Medicis Pharm. Corp., 432 F.3d 1368,
`1375 (Fed. Cir. 2005); Verdegaal Bros., Inc. v. Union Oil Co., 814 F.2d 628,
`631 (Fed. Cir. 1987). Further, a reference cannot anticipate “unless [it]
`discloses within the four corners of the document not only all of the
`limitations claimed[,] but also all of the limitations arranged or combined in
`the same way as recited in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359, 1371 (Fed. Cir. 2008). Although the elements must be
`arranged in the same way as in the claim, “the reference need not satisfy an
`ipsissimis verbis test,” i.e., identity of terminology is not required. In re
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`832 (Fed. Cir. 1990). Moreover, the prior art reference is read from the
`perspective of one with ordinary skill in the art. In re Graves, 69 F.3d 1147,
`1152 (Fed. Cir. 1995) (“A reference anticipates a claim if it discloses the
`claimed invention such that a skilled artisan could take its teachings in
`combination with his own knowledge of the particular art and be in
`possession of the invention.” (citation and quotation marks omitted)); In re
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`Preda, 401 F.2d 825, 826 (CCPA 1968) (“[I]n considering the disclosure of
`a reference, it is proper to take into account not only specific teachings of the
`reference but also the inferences which one skilled in the art would
`reasonably be expected to draw therefrom.”). We analyze this asserted
`ground based on anticipation with the principles identified above in mind.
`
`2. Overview of Kuesters
`Kuesters describes a process of fabricating a 4 Mbit dRAM
`semiconductor device with a 25% reduction in cell size, “achieved by a self
`aligned bitline contact.” Ex. 1005, 3.7
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`7 The page numbers for Exhibit 1005 refer to the page numbers inserted by
`Petitioner in the bottom, right-hand corner of each page.
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`Figure 2 of Kuesters is reproduced below.
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`Figure 2 depicts the process of fabricating a 4 Mbit dRAM with self-aligned,
`fully overlapping bitline contact (“FOBIC”), as disclosed in Kuesters. Id. at
`3, 4. As shown in Figure 2-1 above, the process begins with the deposition
`of a polysilicon layer over a substrate to form a gate structure. Id. at 4.
`Then, an insulating oxide layer is deposited on the gate. Id. Next, an oxide
`spacer covering the sidewalls of the polysilicon/oxide layer is formed by
`oxide deposition and RIE etching. Id. According to Kuesters, “[a] vertical
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`etch profile of [the polysilicon/oxide layer] . . . is essential” when forming
`the oxide sidewall spacers. Id.
`As illustrated in Figure 2-2, a triple layer of “thin oxide/nitride/oxide”
`is then deposited over the entire structure. Id. After patterning a contact
`hole mask on top of the structure, the top oxide is etched to create a contact
`hole using the nitride as an etch stop. Id. Subsequently, the nitride etch stop
`and the remaining thin oxide are etched anisotropically, resulting in the
`structure illustrated in Figure 2-3. Id. at 5. The contact area of the
`fabricated self-aligned contact is “defined by gate and field oxide edges.”
`Id. Figure 4a of Kuesters is reproduced below.
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`Figure 4a depicts the structure fabricated by Kuesters’s process illustrated in
`Figure 2 after the contact hole etch process is completed. Id. at 4–5.
`Following the formation of the contact hole, the dRAM structure is
`completed by adding a bitline, which is accomplished by depositing
`conductive material (TaSi2 on top of polysilicon that is doped by As or P
`implantation) in the contact hole, as illustrated in Figure 2-4. Id. at 6.
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`3. Discussion
`Petitioner asserts that Kuesters describes a process and a structure for
`a 4 Mbit dRAM cell with a 25% reduction in cell size, “achieved by a self
`aligned bitline contact.” Pet. 15–16 (citing Ex. 1005, 3). Petitioner argues
`that Kuesters is directed to the same challenges as the ’552 patent because
`Kuesters describes a “new technique for etching the dielectric underneath
`the bitline” that “ensure[s] a good insulation of bitline to polysilicon gates
`(wordline) and substrate for the overlapping contacts.” Id. at 16 (citing
`Ex. 1005, 4).
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`a. Claim 1
`As set forth above, claim 1 recites numbered elements labeled (a) to
`(e) followed by a wherein clause that recites “a side of the insulating spacer
`has an angle relative to the substrate surface that is either a right angle or an
`acute angle of more than 85°,” i.e., the “angle limitation.” The parties’
`dispute with respect to anticipation by Kuesters centers on the “angle
`limitation.” Petitioner asserts that Kuesters discloses every limitation of
`claim 1, including the “angle limitation.” Pet. 31–40. Patent Owner
`disagrees but argues it “will only address” the final element, i.e., the “angle
`limitation,” of claim 1. PO Resp. 27 (emphasis added). Patent Owner
`asserts that Kuesters does not anticipate claim 1 because the reference does
`not disclose the “angle limitation” recited in claim 1. Id. at 27–34. In what
`follows, because the “angle limitation” is claim 1’s final element that
`describes the structural relationship of earlier recited elements, we will
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`discuss the preamble and the numbered elements (a) to (e) first before
`addressing the “angle limitation” of claim 1.
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`i. Preamble and Elements (a), (b), (c), (d), and (e)
`Beginning with the preamble of claim 1, Petitioner cites Kuesters’s
`disclosure of a dRAM structure in Figures 2 and 4 as disclosing a “structure”
`recited in claim 1. Pet. 31–32 (citing Ex. 1005, 3–4, Figs. 2, 4). According
`to Petitioner, Figures 2 and 4a disclose a fully overlapping bitline contact
`(FOBIC) of a 4Mbit dRAM fabricated in accordance with the etching
`methods disclosed in Section 2.2.1(b) of Kuesters. Id. at 32.
`We agree with Petitioner that Kuesters discloses a “structure” recited
`in claim 1 because, as noted by Petitioner, Kuesters describes “a
`self[-]aligned bitline contact” in a “4 Mbit dRAM cell” (id. at 31 (citing
`Ex. 1005, 3)) and “a trench capacitor cell with self[-]aligned, fully
`overlapping bitline contact (FOBIC)” (id. at 32 (citing Ex. 1005, 3)).
`Petitioner next addresses the limitations recited in the body of claim 1.
`Claim 1 numbers from (a) to (e) the elements recited in the body of the claim
`and recites the numbered elements as follows: (a) a conductive layer
`disposed over a substrate; (b) a first insulating layer on the conductive layer;
`(c) a contact region in said first insulating layer; (d) at least one insulating
`spacer in the contact region adjacent to the first insulating layer; and (e) an
`etch stop material over said first insulating layer and adjacent to the
`insulating spacer, the etch stop material being a different material from the
`insulating spacer. Petitioner asserts that the structure depicted in Figures 2
`and 4a of Kuesters discloses each of these numbered elements. Id. at 32–39.
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`Petitioner provides annotated versions of Figures 2-3 and 4a shown
`below.
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`Annotated versions of Figures 2-3 and 4a in Petition
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`Id. at 33. According to Petitioner and Dr. Fair, Figure 4a depicts a cross-
`section scanning electron microscope (“SEM”) image of the actual structure
`fabricated in accordance with the etching methods disclosed in section
`2.2.1(b) of Kuesters. Id. at 19, 32; Ex. 1003 ¶ 90. Petitioner argues that
`Figure 2 is a drawing depicting the same 4 Mbit dRAM structure according
`to the same etching process. Id. at 32. Petitioner asserts that Figure 2-3 is a
`two-dimensional illustration that highlights the structure at the center of the
`contact hole, whereas Figure 4a depicts a three-dimensional image that
`discloses the structure both at the center and along the back plane of the
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`contact region. Id. at 33 & n.7. The contact region is annotated in light blue
`in Annotated Figures 2 and 4a. Id. at 36.
`Petitioner asserts that the polysilicon conductive gate layer formed
`over a substrate depicted in Figures 2-3 and 4a discloses “(a) a conductive
`layer disposed over a substrate,” as recited in claim 1. Id. at 32–34 (citing
`Ex. 1005, 4, Figs. 2, 4a). According to Petitioner, Annotated Figure 4a
`above shows a conductive polysilicon gate layer (annotated in purple)
`deposited over the substrate (annotated in dark green) in Kuesters’s dRAM
`structure. Id. at 33–34; Ex. 1003 ¶ 93. Petitioner further argues that
`Kuesters describes a “new technique for etching the dielectric underneath
`the bitline” that “ensure[s] a good insulation of bitline to polysilicon gates
`(wordline) and substrate for the overlapping contacts.” Id. at 16, 32
`(quoting Ex. 1005, 4) (emphases added).
`We are persuaded by Petitioner’s argument and evidence that
`Kuesters discloses “a conductive layer disposed over a substrate” as claimed
`because, as noted by Petitioner, Kuesters describes fabricating a contact
`region including a polysilicon gate layer and substrate (id. at 16, 32 (quoting
`Ex. 1005, 4)), and the structures identified by Petitioner in Figures 2-3 and
`4a show that the polysilicon conductive gate layer is formed over the
`substrate.
`Petitioner next asserts that the oxide insulating layer annotated in light
`orange in Annotated Figures 2-3 and 4a above discloses “(b) a first
`insulating layer on the conductive layer,” as recited in claim 1. Id. at 34–35.
`Petitioner notes that the oxide insulating layer is labeled “oxide” in the
`original Figure 4a of Kuesters. Id. at 35. Petitioner argues that Figures 2-3
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`and 4a show that the oxide insulating layer is formed on the polysilicon gate
`layer. Id. Petitioner further asserts Kuesters discloses a process of
`encapsulating the gate with an insulating layer and a subsequent etching
`process to form a contact hole that leaves the oxide insulating layer intact.
`Id. at 34–35 (citing Ex. 1005, 4–5).
`We are persuaded by Petitioner’s argument and evidence that
`Kuesters discloses a completed contact hole structure with an oxide
`insulating layer formed on the conductive polysilicon gate layer because, as
`noted by Petitioner, Kuesters discloses that the “gate is encapsulated by
`oxide using an oxide spacer technique” (id. at 34 (quoting Ex. 1005, 3)) and
`that “[a]fter completing the process (see fig. 3c,4b,4c) an oxide insulation of
`the gate > 120 nm is obtained” (id. at 34–35 (quoting Ex. 1005, 5)). Further,
`the structures identified by Petitioner in Figures 2-3 and 4a show that the
`oxide insulating layer (annotated in light orange) is formed on the
`polysilicon conductive gate layer (annotated in purple). Thus, Petitioner
`demonstrates sufficiently that Kuesters discloses “(b) a first insulating layer
`on the conductive layer,” as recited in claim 1.
`Next, Petitioner asserts that Kuesters’s contact hole or contact area
`extending through the oxide encapsulation discloses “(c) a contact region in
`said first insulating layer,” as recited in claim 1. Id. at 35–36. Petitioner
`identifies the area annotated in light blue in Annotated Figures 2 and 4a
`reproduced above as the claimed “contact region” disclosed in Kuesters. Id.
`at 36.
`
`We are persuaded by Petitioner’s argument and evidence that
`Kuesters discloses a contact hole, i.e., the claimed “contact region,”
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`extending through the oxide insulating layer, i.e., the claimed “first
`insulating layer,” because, as noted by Petitioner, Kuesters discloses forming
`a contact hole by etching a triple layer of top oxide, nitride, and insulating
`oxide. Id. at 35–36 (quoting Ex. 1005, 4 (the first paragraph of Kuesters’s
`Section 2.2.1 titled “Contact hole etch”)). The Petitioner-cited portion of
`Kuesters discloses that “the top oxide is etched using the nitride as an etch
`stop” and, subsequently, “the underlying nitride/oxide is etched
`anisotropically” to form a contact hole without “significantly affect[ing] the
`oxide insulation of the gate.” Id. (quoting Ex. 1005, 4, 5). As noted by
`Petitioner, Kuesters also discloses that “[t]he contact area of the FOBIC
`contact is defined by gate and field oxide edges” (id. at 36 (quoting
`Ex. 1005, 5)), that is, the contact area is delineated by the oxide insulating
`layer. Thus, Petitioner demonstrates sufficiently that Kuesters discloses
`“(c) a contact region in said first insulating layer,” as recited in claim 1.
`Petitioner next asserts that the oxide spacer of Kuesters encapsulating
`the polysilicon gate layer discloses “(d) at least one insulating spacer in the
`contact region adjacent to the first insulating layer,” as recited in claim 1.
`Id. at 37–38. Petitioner identifies the oxide spacer annotated in bright green
`in Annotated Figures 2-3 and 4a above as the claimed “insulating spacer in
`the contact region adjacent to the first insulating layer.” Id. at 38.
`We are persuaded by Petitioner’s argument and evidence that
`Kuesters discloses an insulating oxide spacer encapsulating the polysilicon
`gate layer because, as noted by Petitioner, Kuesters describes that “[a]fter
`patterning a double layer of poly Si/oxide . . . an oxide spacer is formed by
`oxide deposition (TEOS) and RIE etching . . . [and] [t]he poly gate is
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`insulated by at least 0.15 μm oxide.” Id. at 37 (emphases added) (quoting
`Ex. 1005, 4 (the first paragraph of Kuesters’s Section 2.1 titled “Oxide
`encapsulation of the gate”)). We are persuaded that the insulating oxide
`spacer of Kuesters is adjacent to the oxide insulating layer, i.e., the claimed
`“first insulating layer,” because the Petitioner-cited portion of Kuesters
`quoted above describes that the polysilicon gate layer is encapsulated by the
`oxide insulating layer and the insulating oxide spacer. As noted by
`Petitioner, Kuesters also discloses that “gate is encapsulated by oxide using
`an oxide spacer technique.” Id. (quoting Ex. 1005, 3). Further, Annotated
`Figures 2-3 and 4a reproduced above show that the oxide spacer identified
`by Petitioner (annotated in bright green) is adjacent to the oxide insulating
`layer (annotated in light orange and labeled “Oxide” in Figure 4a), i.e., the
`claimed “first insulating layer,” and in the contact area (annotated in light
`blue), the claimed “contact region.” Thus, Petitioner demonstrates
`sufficiently that Kuesters discloses “(d) at least one insulating spacer in the
`contact region adjacent to the first insulating layer,” as recited in claim 1.
`Petitioner further asserts that the nitride layer of Kuesters discloses
`“(e) an etch stop material over said first insulating layer and adjacent to the
`insulating spacer, the etch stop material being a different material from the
`insulating spacer,” as recited in claim 1. Id. at 38–39. Petitioner asserts that
`the nitride layer of Kuesters is an etch stop material and is deposited over the
`oxide insulating layer and adjacent to the oxide spacer of Kuesters. Id.
`(citing Ex. 1005, 3, 4, 5). Petitioner identifies the nitride layer annotated in
`red in Annotated Figures 2-3 and 4a above as the claimed “etch stop material
`over said first insulating layer and adjacent to the insulating spacer.” Id. at
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`39. Petitioner further contends that ni
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