Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 1 of 8 PageID #: 1905
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`Parties’ Proposed Claim Constructions for Claim Terms in U.S. Patent 6,784,552
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`EXHIBIT A
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`“an etch stop
`material over
`said first
`insulating
`layer”
`
`(claim 1)
`
`“an etch stop material around or above said first
`insulating layer”
`
`Generally, an etch stop material has an etch rate that
`is relatively higher than an adjacent or underlying
`material exposed to a specific etch process and may
`prevent etching of the adjacent or underlying
`material.
`
`Abstract; 4:12-17; 12:54-13:20; 13:58-52; 14:10-17;
`Fig. 4K; Fig. 4L; Claims
`
`US 6,004,875
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`Merriam Webster’s Collegiate Dictionary (10th Ed.
`1994) (“over”)
`
`
`
`“a material overlying the first insulating layer that is not
`effectively etched by the etchant used to create the contact
`region”
`
`Specification:
`
`“A distinct dielectric etch stop layer 125 overlies the
`encapsulating dielectric layer 120. The etch stop layer 125
`permits subsequent etching of the substrate without risk of
`exposing the device structures and layers because the
`device structuring and layers are protected from excessive
`etching by the etch stop layer 125.” (’552 patent at 4:13-
`18.)
`
`“The etchant utilized to make the opening had a high
`selectivity toward BPTEOS relative to silicon nitride.
`When the contact opening 270 was formed through the
`BPTEOS material, the etchant did not etch or did not
`effectively etch the silicon nitride layer 240 material.
`Hence, the description of the silicon nitride layer 240 is
`described as an etch stop layer. The silicon nitride etch
`stop layer 240 protected the underlying TEOS layer 230
`and spacer portion 235 so that the polysiclicon layer 220
`completely encapsulated.” (’552 patent at 4:51-60.)
`
`“A distinct insulating layer, for example a silicon nitride
`etch stop layer 340, overlies the TEOS layer 330 and this
`etch stop layer 340 is covered by a third insulating layer,
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`1
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`SAMSUNG-1009.001
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`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 2 of 8 PageID #: 1906
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`for example a BPTEOS blanket layer 350.” (’552 patent at
`5:46-50.)
`
`“FIG. 4(F) illustrates a cross-sectional planar side view of
`a series of gates encapsulated with insulating material and
`an insulating etch stop layer overlying the insulating
`material. FIG. 4(G) illustrates a cross-sectional planar side
`view of a series of gates encapsulated with insulating
`material, an etch stop layer overlying the insulating
`material, and a distinct planarized insulating layer
`overlying the etch stop layer. FIG. 4(H) illustrates a cross-
`sectional planar side view of a series of gates encapsulated
`with insulating material, an etch stop layer overlying the
`insulating material. . . . FIG. 4(I) illustrates a cross-
`sectional planar side view of a series of gates encapsulated
`with insulating material, an etch stop layer overlying the
`insulating material. . . . FIG. 4(L) …” (’552 patent at
`9:19-56.)
`
`“Referring to FIG. 4(F), overlying the TEOS layer 420 is
`deposited a second distinct dielectric or etch stop layer
`440, in this example, a silicon nitride (SixNy) layer 440,
`with a total thickness of 700 angstroms.” (‘552 patent at
`11:63-66.)
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`“a side of the insulating spacer has an angle relative to the
`horizontal substrate surface that is greater than 85° and less
`than or equal to 90°”
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`Specification:
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`SAMSUNG-1009.002
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`“a side of the
`insulating
`spacer has an
`angle relative
`to the substrate
`surface that is
`either a right
`
`
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`Plain and ordinary meaning.
`
`Abstract; 12:66-13:18; 13:29-35; 14:10-17; Figs. 4D,
`4K, 4L; Claims
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`3/3/03 Amendment and Request for Reconsideration
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`2
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`

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`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 3 of 8 PageID #: 1907
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`angle or an
`acute angle of
`more than 85°”
`
`
`
`(claim 1)
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`Fig. 2(A)
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`Fig. 2(B)
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`Fig. 4(K)
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`“FIG. 2(B) shows that the silicon nitride selective etch
`effectively removed silicon nitride layer 240 from the
`contact opening 270. The selective etch for silicon nitride
`compared to TEOS material, however, left the TEOS layer
`230 with a spacer portion 235 wherein the spacer portion
`235 is sloping or tapered toward the contact opening 270.
`This result follows even where the spacer portion is
`originally substantially rectangular as in FIG. 2(A). The
`properties of the highly selective etch of the overlying etch
`stop layer 240 will transform a substantially rectangular
`spacer into a sloped spacer. FIG. 2(B) presents a
`polysilicon layer 220 encapsulated in a TEOS layer 230
`with a spacer portion 235 adjacent to the contact opening
`270, the spacer portion 235 having an angle 290 that is less
`than 85°.” (’552 patent at 5:4-17.)
`
`“The use of an etchant with a low selectivity for silicon
`nitride relative to TEOS does not significantly destroy the
`TEOS layer spacer portion 435. The low selectivity etch
`yields a TEOS layer spacer portion 435 that retains a
`rectangular or “boxy” profile. FIG. 4(K) illustrates that
`only a small portion 475 (illustrated in ghost lines) of the
`TEOS layer spacer portion 435 is removed during the etch.
`Of primary significance, the spacer portion 435 of the
`TEOS layer 420 retains its substantially rectangular
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`3
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`SAMSUNG-1009.003
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`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 4 of 8 PageID #: 1908
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`profile.” (’552 patent at 13:2-10.)
`
`“The phrase ‘substantially rectangular’ means that a side of
`the spacer has an angle relative to the substrate surface of
`more than 85°.” (’552 patent at 8:41-43).
`
`“Etchants that provide a near 90° sidewall angle are
`generally not highly selective while highly selective etches
`typically produce a sloped sidewall.” (’552 patent at 2:54-
`56.)
`
`File History:
`
`“Dennison, et al. describes a method of forming a bit line
`over a capacitor array of memory cells. Element 18 in
`Figure 2 shows a spacer. This portion of the figure is
`reproduced below. As illustrated, the spacer has a sloping
`portion, and is not substantially rectangular.” (’552 File
`History, Amendment, Feb. 6, 2004 at 5.)
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`DSS’s Infringement Contentions:
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`4
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`SAMSUNG-1009.004
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`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 5 of 8 PageID #: 1909
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`
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`(DSS’ Infringement Contentions, Exhibit B at p. 7; see
`also id. at 6 (“The sidewall spacer is steeper than the
`shown reference angle of 85°, shown in black on the
`insulating spacer below.”).)
`
`“lateral spacer that electrically isolates the conductive layer
`from the contact region”
`
`Specification:
`
`Fig. 4(B)-(D)
`
`“The invention contemplates that the insulating layer has
`spacer portions between the conductive layers and the
`contact opening.” (’552 patent at 13:51-53.)
`
`“insulating
`spacer”
`
`(claim 1)
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`Plain and ordinary meaning.
`
`Abstract; 4:34-56; 13:51-65; 14:10-17; Figs. 4D, 4K,
`4L; Claims
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`5
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`SAMSUNG-1009.005
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`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 6 of 8 PageID #: 1910
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`“Next, the insulating spacers are added to the device
`structure to isolate the conductive portion of the device.
`The insulating spacers are etched so that the device
`comprises an insulating layer overlying a conductive layer
`with a lateral spacer portion adjacent the contact region
`wherein the spacer portion has a substantially rectangular
`profile.” (’552 patent at 7:30-36.)
`
`“Referring to FIGS. 4(C) and 4(D), spacers are formed
`between the polysilicon layer 415 of the gates and the
`contact openings by depositing an additional of conformal
`layer of TEOS material 430 over the structure and etching
`spacer portions extending into the contact openings and
`adjacent to the polysilicon layer. . . . The spacer portions
`435 of the TEOS layer 430 are demarked by ghost lines in
`FIG. 4(D). . . . As shown in FIG. 4(C), care is taken to etch
`the spacers 435 such that the spacers 435 have a
`substantially rectangular profile.” (’552 patent at 11:35-
`49.)
`
`“Thus, the remaining etch stop material adjacent to the
`spacer portion 435 of the TEOS layer 420 serves as
`additional spacer material to insulate the polysilicon layer
`415 from a conductive contact that will subsequently be
`added to the contact opening 460.” (’552 patent at 12:61-
`65.)
`
`“The invention relates to a process for minimizing lateral
`spacer erosion of an insulating layer on an enclosed contact
`region, and a device including a contact opening with a
`small alignment tolerance relative to a gate electrode or
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`SAMSUNG-1009.006
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`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 7 of 8 PageID #: 1911
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`“contact
`region”
`
`(claim 1)
`
`other structure.” (’552 patent at 7:15-20.)
`
`“Even if a photoresist that protects the polysilicon layer
`110 from the etchant is misaligned with respect to the
`polysilicon layer 110, the dielectric spacer 150 prevents
`shorts to the polysilicon layer 110 when the contact 130 is
`provided for the diffusion region 140.” (’552 patent at
`4:20-25.)
`
`“The polysilicon layer 220 is separated from the contact
`region 270 by an insulating spacer portion, for example a
`TEOS spacer portion 235.” (’552 patent at 4:39-42.)
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`PARTIES’ AGREED CONSTRUCTION:
`
`PARTIES’ AGREED CONSTRUCTION:
`
`“contact openings and/or vias”
`
`“contact openings and/or vias”
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`Specification:
`
`“Generally, an opening through a dielectric exposing a
`diffusion region or an opening through a dielectric layer
`between polysilicon and a first metal layer is called a
`‘contact opening’, while an opening in other oxide layers
`such as an opening through an intermetal dielectric layer is
`referred to as a ‘via’. For purposes of the claimed
`invention, henceforth ‘contact opening’ or ‘contact region’
`will be used to refer to contact openings and/or via. The
`opening may expose a device region within the silicon
`substrate, such as a source or drain, or may expose some
`other layer or structure, for example, an underlying
`metallization layer, local interconnect layer, or structure
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`7
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`SAMSUNG-1009.007
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`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 8 of 8 PageID #: 1912
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`Claim Term
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`Plaintiff’s Proposed Construction and Support
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`Defendants’ Proposed Construction and Support
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`such as a gate.” (’552 patent at 1:33-45.)
`
`“Adjacent to the polysilicon layer 220 is a contact opening
`region 270.” (’552 patent at 4:38-40.)
`
`“In FIG. 2(A), a contact opening 270 has been opened
`through the BPTEOS layer 250.” (’552 patent at 4:49-51.)
`
`“FIG. 3 illustrates a prior art substrate with a gate and a
`contact region undergoing an RF sputter etch 380 . . . .
`Adjacent to the gate is a contact region 360.” (’552 patent
`at 5:41-51.)
`
`“FIG. 3 indicates the difference in contact opening widths
`for the same contact in prior art structures. w1 represents
`the width at the top of the planarized layer and w2
`represents the width at the base of the contact region 360.”
`(’552 patent at 6:48-52.)
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`SAMSUNG-1009.008