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`UTILITY
`SERIAL no 57!"""1/ .1 ~ 1
`1 ~' 4
`NUMBERUO
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`PATENT DATE
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`FILING DATE
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`EXAMINER
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`ING 0ATA~*~****************~*
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`APP(ICATIONS***********k
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`PARTS OF APPLICATION
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`PAT. & TM-PT0-436L
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`ISSUE
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`Examiner NUMBER
`
`Label
`Area
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`WARNING: The information disclosed herein may be restricted. Unauthorized disclosu~e may
`by the United States Code Title 35, Sections 12~, 181 and 368. Possession
`Patent & Trademark Office is restricted to authonzed employees and contractors
`
`(FACE}
`
`SAMSUNG-1008.001
`
`

`
`PATENT APPL~CATION
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`POSITION
`CLASSIFIER
`EXAMINER
`TYPIST
`VERIFIER
`CORPSCORR.
`SPEC. HAND
`FILE MAINT.
`DRAFTING
`
`INDEX OF CLAIMS
`
`Claim
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`c
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`../ ................................. Rejected
`= ................................. Allowed
`• (Through numberal). Canceled
`+ ................................. Restricted
`N ................................. Non-elected
`I ................................. Interference
`A ................................. Appeal
`0 ................................. Objected
`
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`~s 39 /
`llt.o 40
`\.1 41
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`1 43
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`45
`46
`47
`48
`49
`50
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`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`100
`
`SAMSUNG-1008.005
`
`

`
`PATENT APPLICATION SERIAL NO. 88/577751
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`230 PS 01/22/96 08577751
`1
`
`PT0-1556
`(5/87)
`
`SAMSUNG-1008.006
`
`

`
`[-oo
`~tAl
`
`THE HONORABLE COtv1MISSIONER OF PATENTS AND TRADeMARKS
`Washington, D.C.
`20231
`
`Sir:
`
`Transmitted herewith for filing is the patent application of:
`
`Inventor(s): James E. Nulty, Christopher J. Petti
`
`For: METHOD FOR ELIMINATING LATERAL SPACER EROSION ON
`ENCLOSED CONTACT TOPOGRAPHIES DURING RF SPUTTER CLEANING
`
`Enclosed are:
`XXX
`
`sheet(s) of Formal/Informal Drawing(s) including __12_ figures.
`8
`An Assignment of the invention to : - - - - - - - - - - - - - -
`
`A Declaration and Power of Attorney.
`A Verified Statement to establish Small Entity Status under 37 CFR 1.9 and
`37 CFR 1.27.
`
`The Filing Fee has been calculated as shown below:
`
`(Col. 1)
`No. Filed
`
`-
`
`(Col.2)
`No. Extra
`-
`
`SMALL ENTITY
`RATE
`FEE
`
`-
`
`OTHER THAN A·
`SMALL ENTITY
`RATE
`FEE
`
`-
`
`$375.00
`
`$750.00
`
`26
`
`6
`
`X $11.00
`
`X $22.00
`
`132.00
`
`For:
`
`Basic Fee:
`Total
`Claims:
`Indep.
`Claims:
`
`3
`
`0
`
`D Multiple Dep. Claim(s) Presented
`* If the difference in (Col. 1) is less than
`zero, enter "0" in (Col. 2)
`
`X $39.00
`
`+ $125.00
`
`X $78.00
`
`0
`
`+ $250.00
`
`Total:
`
`$
`
`Total:
`
`$882.00
`
`A check in the amount of$ 882.00 to cover the filing fee is enclosed.
`A check for $40.00 covering Recordation of the Assignment is enclosed, along
`with the Assignment Cover Sheet.
`The Commissioner is hereby authorized to charge payment of the following fees
`associated with this communication or credit any overpayment tq our Deposit
`Account No. 02-2666. A duplicate copy of this sheet is enclosed.
`XXX Any additional filing fees required under 37 CFR 1.16.
`XXX Any patent application processing fees under 37 CFR 1.16.
`The Commissioner is hereby authorized to charge payment of the following fees
`during the pendency of this application or credit any overpayment to our .
`Deposit Account No. 02-2666. A duplicate copy of this sheet is enclosed.
`XXX Any extension or petition fees under 37 CFR 1.17.
`XX,X Any filing fees under 37 CFR 1.16 for presentation of extra claims.
`'
`
`Respectfully submitted,
`
`12400 Wilshire Boulevard
`Seventh Floor
`Los Angeles, Califomia 90025
`(310) 207-3800
`
`BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN
`
`,~~
`
`William Thomas Bab 1tt
`Reg. No. P39,591
`
`CERTIFICATE OF MAILING:
`I hereby certify that this correspondence is being deposited with
`the United States Postal Service as Express Mail No.
`TB756154652
`in an envelope addressed to: Commissioner of Patents and
`~~·~~.C. 20231 on December 22.
`1995.
`1
`.
`--
`·/ ;.
`'
`-·-·-······-·- ______ ._ ------------------ ---·-------------~-- .. ·-----··
`·~
`
`/
`
`SAMSUNG-1008.007
`
`

`
`U8/577751
`
`16820.P097
`
`THE HONORABLE COMMISSIONER OF PATENTS AND TRADEMARKS
`20231
`Washington, D.C.
`
`Sir:
`
`Tr~~mitted herewith for filing is the patent application of:
`
`"Inventor(s): James E. Nulty, Christopher J. Petti
`
`For: METHOD FOR ELIMINATING LATERAL SPACER EROSION ON
`ENCLOSED CONTACT TOPOGRAPHIES DURING RF SPUTTER CLEANING
`
`Enclosed are:
`XXX
`
`sheet(s) of Formal/Informal Drawing(s) including ___12_ figures.
`8
`An Assignment of the invention to: - - - - - - - - - - - - - -
`
`A Declaration and Power of Attorney.
`A Verified Statement to establish Small Entity Status under 37 CFR 1.9 and
`37 CFR 1.27.
`
`The Filing Fee has been calculated as shown below:
`
`_(Col. 11
`No. Filed
`-
`
`(Col.2)
`No. Extra
`-
`
`SMALL ENTITY
`RATE
`FEE
`-
`
`$375.00
`
`OTHER THANA
`SMALL ENTITY
`RATE
`FEE
`-
`
`$750.00
`
`26
`
`6
`
`X $11.00
`
`X $22.00
`
`132.00
`
`For:
`
`Basic Fee:
`Total
`Claims:
`Indep.
`Claims:
`
`3
`
`0
`
`D Multi_ple Dep. Claim(s) Presented
`* If the difference in (Col. 1) is less than
`zero, enter "0" in (Col. 2)
`
`X $39.00
`
`+ $125.00
`
`X $78.00
`
`0
`
`+ $250.00
`
`Total:
`
`$
`
`Total:
`
`$882.00
`
`A check in the amount of$ 882.00 to cover the filing fee is enclosed.
`A check for $40.00 covering Recordation of the Assignment is enclosed, along
`with the Assignment Cover Sheet.
`The Commissioner is hereby authorized to charge payment of the following fees
`associated with this communication or credit any overpayment to our Deposit
`Account No. 02-2666. A duplicate copy of this sheet is enclosed ..
`XXX Any additional filing fees required under 37 CFR 1.16.
`XXX Any patent application processing fees under 37 CFR 1.16.
`The Commissioner is hereby authorized to charge payment of the following fees
`during the pendency of this application or credit any overpayment to our
`Deposit Account No. 02-2666. A duplicate copy of this sheet is enclosed.
`XXX Any extension or petition fees under 37 CFR 1.17.
`XXX Any filing fees under 37 CFR 1.16 for presentation of extra claims.
`
`12400 Wilshire Boulevard
`Seventh Floor
`Los Angeles, California 90025
`(310) 207-3800
`
`Respectfully submitted,
`
`BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN
`
`~v~
`
`William Thomas Babbitt
`Reg. No. P39,591
`
`CERTIFICATE OF MAILING:
`I hereby certify that this correspondence is being deposited with
`the United States Postal Service as Express Mail No.
`TB756154652
`in an envelope addressed to: Commissioner of Patents and
`.C. 20231 on December 22, 1995.
`, Washin
`Tra
`;t/tl/f~
`Date
`
`SAMSUNG-1008.008
`
`

`
`Our Reference: 16820.P097
`
`APPLICATION FO~ UNITED STATES PATENT
`
`FOR
`
`METHOD FOR ELIMINATING LATERAL SPACER
`EROSION ON ENCLOSED CONTACT TOPOGRAPHIES
`DURING RF SPUTTER CLEANING
`
`Inventors:
`
`JAMES E. NULTY
`CHRISTOPHER J. PETTI
`
`Prepared by:
`
`BLAKELY SOKOLOFF TAYLOR & ZAFMAN
`12400 Wilshire Boulevard
`.
`Seventh Floor
`Los Angeles, CA 90025
`(310) 207--3800
`
`I hereby certify that this correspondence is
`being deposited with the United States Postal
`Service as Express Mail (Label No: T~ '"'lS'C'ol~"1 '=>51..
`in an envelope addressed to: Commissioner of Patents
`
`~gton, D.C. 20231 ~~ -::;r.v;:; U. I '191"'
`
`Name
`
`Date
`
`SAMSUNG-1008.009
`
`

`
`~8/57~
`
`BACKGROUND OF THE INVENTION
`
`Field of the Invention;
`
`The invention relates to semiconductor device processes, and more
`
`particularly, to improved methods for etching openings in insulating layers and a
`
`5
`
`semiconductor device with well defined contact openings.
`
`Backf,;round of the Invention
`
`In the fabrication of semiconductor devices, numerous conductive device
`
`regions and layers are formed in or on a semiconductor substrate. The conductive
`
`regions and layers of the device are isolated from one another by a dielectric.
`
`10
`
`Examples of dielectrics include silicon dioxide, Si02, tetraethyl orthosilicate glass
`
`("TEOS"), silicon nitrides, SixNy, silicon oxyrutrides, SiOxNy(Hz), and silicon
`
`dioxide/silicon nitride/silicon dioxide ("ONO"). ·The dielectrics may be gr~wn, or
`
`may be deposited by physical deposition (e.g., sputtering) or by a variety of chemical
`
`deposition methods and chemistries (e.g., chemical vapor deposition ("CVD")).
`
`15 Additionally, the dielectrics may be undoped or may be doped, for example with
`
`boron, phosphorous, or both, to form, for example, borophosphosil~cate glass
`
`("BPSG"), phosphosilicated glass ("PSG"), and borophosphosilicate tetraethyl
`
`orthosilicate glass ("BPTEOS").
`
`At several stages of the fabrication of semiconductor devices, it is necessary to
`
`20 make openings in the dielectric to allow for contact to underlying regions or layers.
`
`Generally, an opening through a dielectric exposing a diffusion region or an
`a-
`opening through a dielectric layer between polysilicon and;ke first metal layer is
`
`called a "contact opening", while an opening in other oxide layers such as an
`
`opening through an intermetal dielectric layer is referred to as a "via". For purposes
`
`JCS/WTB/mp
`
`-1-
`
`16820.P097
`
`SAMSUNG-1008.010
`
`

`
`of the claimed invention, henceforth "contact opening" or "contact region" will be
`
`used to refer to contact openings and/ or via. The opening may expose a device
`
`region within the silicon substrate, such as a source or drain, or may expose some
`
`other layer or structure, for example, an underlying metallization layer, local
`
`5
`
`interconnect layer, or structure such as a gate. After the opening has been formed
`
`exposing a portion of the region or layer to be contacted, the opening is generally
`
`cleaned with a sputter etch, e.g., a Radio-Frequency ("RF") sputter etch, and then the
`
`opening is filled with a conductive material deposited in the opening and in
`
`electrical contact with the underlying region or layer.
`
`10
`
`To form the openings a patterning layer of photoresist is first formed over the
`
`dielectric layer having openings corresponding to the regions of the dielectric where
`
`the dielectric layer openings are to be formed. In most modern processes a dry etch
`
`is then performed wherein the wafer is exposed to a plasma, formed in a flow of one
`
`or more gases. Typically, one or more halocarbons and/or one or more other
`
`15
`
`halogenated compounds a.re used as the etchant gas. For example, CF4, CHF3 (Freon
`
`23), SF6, NF3, and other gases may be used as the etchant gas. Additionally, gases
`
`such as 02, Ar, N2, and others may be added to the gas flow. The particular gas
`
`mixture used will depend on, for example, the characteristics of the dielectric being
`
`etched, the stage of processing, the etch tool being used, and the desired etch
`
`20
`
`characteristics, i.e., etch rate, sidewall slope, anisotropy, etc.
`
`Many of the etch characteristics are generally believed to be affected by
`
`polymer residues that deposit during the etch. For this reason, the fluorine to
`
`carbon (F /C) ratio in the plasma is considered an important determinant in the etch.
`
`In general, a plasma with a high F /C ratio will have a faster etch rate than a plasma
`
`25 with a low F /C ratio. At very low rates, i.e., high carbon content, polymer
`
`deposition occurs and etching ceases. The etch rate as a function of the F /C ratio is
`
`JCS/WTB/mp
`
`-2-
`
`16820.P097
`
`SAMSUNG-1008.011
`
`

`
`typically different for different materials. The difference is used to create a selective
`
`etch, by using a gas mixture that puts the F /C ratio in the plasma at a value that
`
`leads to etching at a reasonable rate for one material, and that leads to no etching or
`
`polymer deposition for another. For example, an etchant that has an etch rate ratio
`
`5
`
`or a selectivity ratio of two to one for silicon nitride compared to silicon dioxide is
`
`an effective stripper of silicon nitride from. the semiconductor substrate, because it
`
`will selectively strip silicon nitride over silicon dioxide on a substrate surface. An
`
`etchant that has an etch rate ratio or a selectivity ratio of 0.85 to one for silicon
`
`nitride compared to silicon dioxide is not considered an effective stripper of silicon
`
`10
`
`nitride from the semiconductor substrate because the etchant will not effectively
`
`strip silicon nitride to the exclusion of silicon dioxide.
`
`The selectivity of the etch process is a useful parameter for monitoring the
`
`process based on the etch rate characteristic of the particular etchant. As noted
`
`above, particular etchants or etchant chemistries attack different materials,at
`
`15
`
`different etch rates. With respect to dielectrics, for example, particular etchants
`
`attack silicon dioxide, BPTEOS, TEOS, and silicon nitride dielectrics at different rates.
`
`To make openings in a substrate comprising a contact region surrounded by
`
`different dielectric layers, e.g., a dielectric layer of TEOS surrounded ·by a dielectric
`
`layer of silicon nitride, a process will utilize different etchants to make openings
`
`20
`
`through the different dielectrics. Thus, the different etch rates of particular dielectric
`
`layers for an etchant may be used to monitor the creation of an opening through a
`
`dielectric layer.
`
`Further, by adjusting the feed gases, the taper of the sidewall in the etched
`
`opening of the dielectric can be varied. If a low sidewall angle is desired, the
`
`25
`
`chemistry is adjusted to try to cause some polymer buildup on the sidewall.
`
`Conversely, if a steep sidewall angle is desired, the chemistry is adjusted to try to
`
`JCS/WTB/mp
`
`-3-
`
`16820.P097
`
`SAMSUNG-1008.012
`
`

`
`prevent polymer buildup on the sidewall. Varying the etch gas pressure, for
`
`example, has a significant effect on the shape of the opening. This is because the
`
`etchant ions generally arrive in a direction perpendicular to the substrate surface,
`
`and hence strike the bottom surfaces of the unmasked substrate. The sidewalls of
`
`5
`
`etched openings, meanwhile, are subjected to little or no borr:t-bardment. By
`
`increasing the pressure of the etch gas, the bombardment directed toward the
`
`sidewalls is increased; by decreasing the pressure of the etch gas, the bombardment
`
`directed toward the sidewalls is decreased. The changing of the etch chemistry is
`
`,
`
`also directly related to selectivity. Etchants that provide a near 90° sidewall angle are
`
`10
`
`generally not highly selective while highly selective etches typically produce a
`
`sloped sidewall.
`
`Following the dielectric etch(es) and prior to any conductive material
`
`deposition in a contact region, native oxide on top of the conducting layer$ in the
`
`contact region is removed or cleaned through a non-chemical sputter etch, e.g., an
`
`15 RF sputter etch. In addition to alleviating the contact region of native oxide, the
`
`sputter etch can erode any insulating dielectric layer or layers. Thus, the parameters
`
`of the sputter etch must be carefully monitored so as not to excessiv.ely erode the
`
`insulating dielectric layer(s) and expose other underlying conductive. material.
`
`Exposing insulated conductive material adjacent to the conductive material in the
`
`20
`
`contact region results in poor quality contacts or a short circuit through the
`
`underlying conductive material. For a thorough discussion of oxide etching, seeS.
`
`Wolf and R.N. Tauber, Silicon Processing for the YLSI Era. Vol. 1, pp. 539-85 (1986).
`
`The preceding discussion focused on the making of openings, e.g., contact
`
`openings, in dielectric material on a semiconductor substrate. The same principles
`
`25
`
`are used in constructing device regions with a dielectric layer or layers. As
`
`geometries shrink, the forming of discretf' devices on a semiconductor substrate
`
`JCS/WTB/mp
`
`-4-
`
`16820.P097
`
`SAMSUNG-1008.013
`
`

`
`becomes more specialized. Specialized deposition and etching techniques permit
`
`the density of semiconductor elements on a single chip to greatly increase, which
`
`translates into larger memory, faster operating speeds, and reduced production costs.
`
`A typical metal oxide semiconductor (MOS) transistor, e.g., NMOS or PMOS
`
`5
`
`transistor, generally includes source/ drain regions in a substrate, and a gate
`
`electrode formed above the substrate between the source/ drain regions and
`
`separated from the substrate by a relatively thin dielectric. Contact structures can be
`
`inserted to the source/ drain regions and interlays can overlie the contact structures
`
`and connect neighboring contact structures. These contact structures to the
`
`10
`
`diffusion region are isolated from the adjacent gate by dielectric spacer or shoulder
`
`portions. The dielectric spacer or shoulder portions also isolate the gate from the
`
`diffusion region.
`
`Conventional contact structures limit the area of the diffusion region, because
`
`the contact hole is aligned to these regions with a separate masking step, and extra
`
`15
`
`area must be allocated for misalignment. Proper alignment is necessary to avoid
`
`shorting the contact structure to the gate or the diffusion well. The larger contact
`
`area means a smaller density of elements on a structure. The larger contact area is
`
`also responsible for increased diffusion-to-substrate junction capacitance, which
`
`limits device speed.
`
`20
`
`A self-aligned contact eliminates the alignment problems associated with
`
`conventional contact structures and increases the. device density of a structure. A
`
`self-aligned contact is a contact to a source or drain diffusion region. A self-aligned
`
`contact is useful in compact geometnes because it can overlap a conducting area to
`
`which it is not supposed to make electrical contact and can overlap the edge of a
`
`25
`
`diffusion region without shorting out to the well beneath. Consequently, less
`
`JCS/WTB/mp
`
`-5-
`
`16820.P097
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`SAMSUNG-1008.014
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`contact area is needed and gates or conductive material lines, e.g., polysilicon lines,
`
`can be moved closer together allowing more gates or lines on a given substrate than
`
`traditional contacts.
`
`130
`Figure 1 illustrates a self-aligned contact between two gate structures. Figure
`l(A) is a planar top view of the contac,r13~igur: l(B) is a planar cross-sectional view
`l:h<
`130
`of )l'self-aligned contact between a pair of gates taken through line 1(B) of Figure
`M4
`~P
`1
`1(A). Figure 1(C) is a planar cross-sectional view of 1- self-aligned contact between a
`.4
`
`pair of gates taken through line 1(C) of Figure 1(A).
`
`I:!JD
`The self-aligned contact is a contact to a source or drain diffusion region (n+
`1
`(J..
`or p+ silicon) 140 that can overlap~ edge of the diffusion region 140 without
`a.
`shorting out to t};le well beneath the diffusion region 140. This can be seen most
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`5
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`10
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`illustratively through Figure 1(C). In Figure 1(C), the contact 130 does not li~ dire~tly
`(deliJ""'I'I JY {'t)J. in F1Z;, fit.
`in the diffusion region 140, but is misaligned and slightly overlaps the fiel~ oxidx
`..-
`' ·
`/.J ()
`In this illustration, the self-aligned contact is not directly over the diffusion region
`~
`M~
`but extends over (i.e., overlaps) a well portion 170. The self-aligned contact does not
`I ,{1
`-1
`short to the well portion 170 because the self-aligned contact is separated from the
`/(
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`(jv
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`15
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`well170 by the field oxide.
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`The self-aligned contact 130 is separated from a conducting polysilicon layer
`
`110 by an encapsulating dielectric layer 120 such that the contact 130 can also overlap
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`20
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`the polysilicon layer 110 without making electrical contact to the layer 110 or gate.
`
`The polysilicon layer 110 is separated from the source/ drain diffusion region 140 by
`
`a dielectric spacer or shoulder 150 of the same or different dielectric material as the
`dielectric layer 120 directly a~ove the conducting polysilico{c':!:l~r- ///)
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`A distinct dielectric etch stop layer 125 overlies the encapsulating dielectric
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`25
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`layer 120. The etch stop layer 125 permits subsequent etching of the substrate
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`JCS/WTB/mp
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`-6-
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`16820.P097
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`SAMSUNG-1008.015
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`without risk of exposing the device structures and layers because the device
`
`structuring and layers are protected from excessive etching by the etch stop layer.IZ!>
`A
`The diffusion contact is self-aligning because the structure can be etched to the
`
`substrate over the source/ drain diffusion region 140 while the dielectric spacer 150
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`5
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`protects the polysilicon layer 110. Even if a photoresist that protects the polysilicon
`
`layer 110 from the etchant is misaligned with respect to the polysilicon layer 110, the
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`dielectric spacer 150 prevents shorts to the polysilicon layer 110 when the contact 130
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`is provided for the diffusion region 140.
`
`The current practice with respect to forming contact regions, particularly self-
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`10
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`<t-
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`aligned contact regions, that are in electrical COI~tact with gates, interconnect lines, or
`/.jh
`other structures in small feature size structures utilize etchants with high selectivity
`A
`to protect underlying regions, like the etch stop layer and the first insulating layer .
`..<II "-'tn .. l-eJ'
`Figure 2 aemenstnW& a typical prior art process of forming a self-aligned contact
`
`region adjacent to a gate. In Figure 2(A), a gate oxide layer 210 is formed on a
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`15
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`substrate 200 with a conducting layer, for example a polysilicon layer 220, overlying
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`the gate oxide layer 210, and an insulating layer, for example a TEOS layer 230,
`.:JRP
`overlying the polysilicon layer 220. Adjacent to the polysilicon layer is a contact
`1
`opening region 270. The polysilicon layer 220 is separated from the contact region
`
`270 by an insulating spacer portion, for example a TEOS spacer portion 235. A
`
`20
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`separate insulating or etch stop layer, for example a silicon nitride layer 240 overlies
`t:J?O
`.
`the TEOS layer 230 and the contact regionzse. A blanket layer, for example a doped
`tl,'1CI
`insulating layer like a BPTEOS layer ..zse-, planarly overlies the etch stop layer 240.
`
`A layer of photoresist material280 overlies the planarized BPTEOS layer 250
`
`to expose the contact opening 270. In Figure 2(A), a contact opening 270 has been
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`25
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`opened through the BPTEOS layer 250. The etchant utilized to make the opening
`
`had a high selectivity toward BPTEOS relative to silicon nitride. When the contact
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`JCS/WTB/mp
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`-7-
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`16820.P097
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`SAMSUNG-1008.016
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`

`
`.for Mt- d
`.270
`opening was through the BPTEOS material, the etchant did not etch or did not
`1
`II
`effectively etch the silicon nitride layer 240 material. Henc~ the tiQeeripHeR ef the
`I> de.:v:;ed
`silicon nitride layer 240 as an etch stop layer. The silicon nitride etch stop layer .24!)
`llf&fl ~Jl() re,n.l"4.il)-e d
`.I?.JP~d :Sf?ftCe'"" ?f;Jr.JiiiJ 1-~
`protected the underlying TEOS laye~ so that the pdlysilicon rema:~ completely
`
`5
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`encapsulated.
`
`Figure 2(A) illustrates an etch 260 to remove the silicon nitride etch stop layer
`;? IJ(}
`240. In the etch illustrated in Figure 2(A), a high selectivity etch toward silicon
`1
`nitride relative to the underlying TEOS layer 230 material is practiced to efficiently
`~~,
`.
`etch the silicon nitride layer.., and to protect the underlying TEOS layer 230 from the
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`10
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`etchant. An example of a high selectivity etch recipe to effectively strip silicon
`
`nitride as compared to the TEOS layer is 30 seem CHF3 and 30 seem 02 at 60 mtorr
`
`and 100 watts of power. The result of the high selectivity etch is illustrated in Figure
`
`2(B).
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`£..-
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`15
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`Figure 2(B) shows that the silicon nitride selective etch effectively removed
`laz~r
`silicon nitride 240 from the contact opening 270. The selective etch for silicon
`4
`nitride compared to TEOS material, however, left the TEOS layer 230 with a spacer
`:l${'
`portion 235 wherein the spacer portion is sloping or tapered toward the contact
`.,
`~7C
`openin~ This result follows even where the spacer portion 235 is or~ginally
`
`w
`
`20
`
`substantially rectangular as in Figure 2(A). The properties of the highly selective
`t24V
`etch of the overlying etch stop layer will transform a substantially rectangular spacer
`'1
`into a sloped spacer. Figure 2(B) presents a polysilicon layer 220 encapsulated in a
`
`TEOS layer 230 with a spacer portion 235 adjacent to the contact opening 270, the
`
`spacer portion 235 having an angle 290 that is less than 85°.
`
`In addition to providing stopping points or selectivity between materials, the
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`25
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`use of high selectivity etches to form sloped spacer portions is the preferred practice
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`JCS/WTB/mp
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`16820.P097
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`SAMSUNG-1008.017
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`because the sloped shape will result in good step coverage by the metal that is
`
`deposited into it. The filling of contact openings or gaps (i.e., gap fill) is an
`
`important consideration because it relates directly to the reliability of a device. If an
`WI
`opening is not completely filled with p insulative material, for example, and a gap is
`created, a subsequent conductive material deposit can fill the gap which can lead to
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`5
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`shorting. Sloped contact openings are easier to completely fill than boxy structures
`
`because the transition between sloped structures and openings is smooth compared
`
`to the abrupt transitions between boxy structures and openings. Because of concerns
`
`for complete gap fill and good step coverage, industry preference is for sloped spacers
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`10
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`and planar deposition layers similar to that shown in Figure 2(b ).
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`Once the contact opening is made, the opening is cleaned with a sputter etch,
`
`e.g., an RF sputter etch, before conductive material is added to fill the opening or
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`gap. The RF sputter etch that is used to clean the contact opening in the process
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`CJ..-
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`15
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`
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`described above will attack and erode a portion of the insulating spacer surrounding
`3J4.)/wh-Je.f
`·
`·
`·
`d d'
`h
`·
`F'
`h t e con uctmg portion an a Jacent to t e contact regwn. 1gure presen~ a pnor
`d
`1
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`art substrate with a gate and a contact region undergoing an RF sputter etc9f In
`
`Figure 3, a gate oxide 310 is formed on a substrate 300 with a polysilicon layer 320
`
`overlying the gate oxide 310 and an insulating layer, for example a TEOS layer 330
`
`overlying the polysilicon layer 320. A distinct insulating layer, for e~ample a silicon
`
`20
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`nitride etch stop layer 340, overlies the TEOS layer 330 and this etch stop layer 340 is
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`covered by a third insulating layer, for example a BPTEOS blanket layer 350.
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`Adjacent to the gate is a contact region 360. An etch of the silicon nitride etch stop
`
`layer 340 with a high selectivity etch for silicon nitride relative to the underlying
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`TEOS layer material produced a gate with a sloping or tapered spacer portion 370 of
`3fV
`TEOS material, illustrated in ghost lines. A subsequent RF sputter etc~is utilized to
`
`(3../ 25
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`clean the contact region 360.
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`JCS/WTB/mp
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`16820.P097
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`SAMSUNG-1008.018
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`

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`Although brief and designed to clean the contact region, the RF sputter etch 3 i'O
`"j)orti t>, .J 1 fl
`will erode a portion of the insulating TEOS space?f' The dynamics of the sputter etch 3H'
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`5
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`are that it proceeds vertically, directing high-energy particles at the contact region .
`l6.re.~ .;.;. fl
`..; 111
`The sloping or tapered spacer portion adjacent the polysilicon and separating the
`/l.jt r ~-v C~t~fl.c ...J-
`1~~
`1
`polysilicon from the EiiftusieR region 1s struck by the high-energy particles of the RF
`'
`sputter etch 380. Because the spacer portion 370 is sloping or diagonal, a significant
`surface area portion of the spacer portion 370 is directly exposed to the high-energy
`
`particles from the RF sputter etch 380. Further, with sloping spacers, or spacers
`
`having an angle relative to the substrate surface of less than 85° the vertical portion
`/e-yt~' ~.20
`of the dielectric layer J(i.e., that portion above the polysilicon g.a.te7 decreases much
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`eo....--
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`10
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`less than the diagonal portion of the spacer. In terms of measuring TEOS material
`f/¥P
`removal during the RF sputter etch in Figure 3, the difference between d1 and d2 is
`.,
`greater than the difference between Vl and v2. Thus, in conventional prior art self-
`.
`?orlt/1) .}11)
`aligned contact structures, the diagonal thickness of the TEOS spacer, rather than the
`3Jo
`1
`vertical thickness of the TEOS layef determines the minimum insulating layer
`
`15
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`thickness for the gate.
`
`~
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`For gate structures having minimum diagonal insulative spacer portions of
`500 A or less, the result of the sputter etch 380 is that the sputter etch 380 laterally
`$-pactr f'C~"-hm
`·
`erodes the diagonal portion of the TEOS J,a.yef 370 adjacent to the contact region to a
`1~-t¥"
`-1
`.
`point where the polysilicon 320 is no longer isolated from the contact region 360 by
`.
`an insulating layer. In that case, there is a short circuit through the underlying
`ryivn ,5/,P
`conductive material when the contact OfJCf'ting is filled with conductive material.
`.J¥"D
`1
`.,
`This result follows because the conventional RF sputter etch utilized for cleaning
`,,o
`the contact region results in an approximately 200-500 A loss of the spacer material.
`•
`Further, process margins generally require that the device spacer have a final
`minimum thickness (after all etches, doping, and deposits) of at least 500 A. Thus,
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`0
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`CIV' 20
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`16820.P097
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`SAMSUNG-1008.019
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`

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`c.-
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`to eliminat?alignment sensitivity for conventional small feature size structures,
`
`including self-aligned contact structures, requires a final (i.e., at the time of contact
`deposition) minimum insulating spacer of more than 500 A and preferably on the
`order of 1000-1500 A or greater to fulfill requirements for an adequate process
`5 margin, complete gap fill, and device reliability.
`
`To construct structures having a minimum insulative spacer portion of more
`than 500 A directly effects the number of structures that can be placed on a device,
`such as a chip. The construction of structures having a minimum insulative spacer
`portion of more than 500 A requires that the pre-etch-stop-etch spacer be bigger or
`
`10
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`thicker to yield an effective spacer after the etching processes. In such cases, the
`
`structures must be separated a distance such that the contact area opening is
`
`sufficient enough for an effective contact. This spacing requirement directly limits
`
`the number of structures that can be included on a device. In small feature size
`
`structures, particularly structures utilizing self-aligned contacts, the width,of contact
`
`15
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`openings is approximately 0.6 microns at the top of the planarized layer and 0.2
`
`microns at the base of the contact opening. Figure 3 indicates the difference in
`
`contact opening widths for the same contact in prior art structures. Wl represents
`
`the width at the top of the planarized layer and W2 represents the width at the base
`(~'i6, !ItO
`of the contact_,opewng. Further, an aspect ratio can be defined as the ~eight of a
`
`20
`
`structure (field oxide plus conductive layer plus firs