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`U.S. UTILITY Patent Application
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`PATENT DATE
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`D TERMINAL
`
`DISCLAIMER
`
`D The term of this patent
`subsequent to _____ (date)
`has been disclaimed.
`
`[] The term of this patent shall
`not extend b~yond the expiration date
`of U.S Patent. No. _____ _
`
`D Continued on Issue Slip Inside File Jacket
`
`DRAWINGS
`
`CLAIMS ALLOWED
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`· Sheets Drwg.
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`Print Claim for O.G.
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`I
`
`ISSUE FEE
`
`Amount Due
`
`ISSUE BATCH NUMBER
`
`[] The terminal __ montbs of
`this patent have been disclaimed.
`
`(Date)
`
`WARNING:
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`FILED WITH: D DISK (CRF) D FICHE D CD-ROM
`
`Form PT0-436A
`(Rev. 6i99)
`
`FEf IN
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`

`
`ISSUE SLIP STAPLE AREA (for additional cross references)
`
`POSITION
`
`INITIALS
`
`IDNO.
`
`DATE
`
`l=EE DETERMINATION
`0.1.P.E. CLASSIFIER
`FORMALITY REVIEW
`RESPONSE FORMALITY REVIEW
`
`'"':..:
`
`... ~ ...
`
`INDEX OF CLAIMS
`v ................................. Rejected
`· N ................................. Non-elected
`= ................................. Allowed
`I ................................. Interference
`A ................................. Appeal
`(Through numeral) ... Canceled
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`If more than 150 claims or 10 actions
`staple additional sheet here
`
`(LEFT INSIDE)
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`SAMSUNG-1002.004
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`

`
`PATENT APPLICATION SERIAL NO.
`
`.
`
`~~~~~~~~~
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`04/07/2000 JARTIS
`01 FC:101
`
`00000006 09540610
`690.00 OP
`
`PT0-1556
`(5/87)
`
`'U.S. GPO: 1999-459-082/19144
`
`. ~ :·,
`
`'.\
`I
`
`•
`
`SAMSUNG-1002.005
`
`

`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Vuginia 22313·1450
`www.uspto.gov
`
`CONFIRMATION NO. 2171
`
`CLASS
`257
`
`GROUP ART UNIT
`2815
`
`ATTORNEY DOCKET
`NO.
`16820.P097
`
`1111111111111111111111111111111111111111111111111111111111111111111111
`Bib Data Sheet
`
`FILING DATE
`03/31/2000
`
`RULE
`
`SERIAL NUMBER
`09/540,610
`
`APPLICANTS
`
`James E. N.,ulty, San Jose, CA;
`
`Christopher J. Petti, Mountain View, CA;
`
`**CONTINUING DATA*************************
`This application is a DIV of 08/577,751 12/22/1995 PAT 6,066,555
`
`"''FOREIGN APPLICATIONS********************
`
`IF REQUIRED, FOREIGN FILING LICENSE GRANTED
`** 06/02/2000
`
`0 yes 0 no
`Foreign Priority claimo3d
`35 USC 119 (a-d) conditions met 0 yes 0 no 0 Met after Allowance
`Verified and Acknowledged Examiner's Signature
`
`ADDRESS
`43320
`EVAN u;w CiROUP LLC
`566 WEST ADAMS, SUITE 350
`CHICAGO, IL
`60661
`
`ST A TE OR
`
`SHEETS
`
`TOTAL
`
`INDEPENDENT
`
`COUNTRY
`CA
`
`DRAWING
`8
`
`CLAIMS
`13
`
`CLAIMS
`2
`
`TITLE
`STRUCTU'~E HAVING REDUCED LATERAL SPACER EROSION
`
`FILING FEE
`
`RECl::IVED
`990
`
`FEES: Authority has been given in Paper
`to charge/credit DEPOSIT ACCOUNT
`No.
`No.
`for following:
`
`lo All Fees
`I 0 1. 16 Fees ( Filing )
`0 1.17 Fees ( Processing Ext. of
`time)
`I 0 1.18 Fees ( Issue )
`lo Other
`
`I !
`
`•
`
`SAMSUNG-1002.006
`
`

`
`I'
`1'
`
`UNITED STATES PATENT AND ThADEMARK OFFIGE
`
`UNI'l'ED STATES DEPARTM:g:,iT OF COMMERCE
`Unitad Stt1tHM Putant and 'l'rad~marlc. Offim~
`Addrcao: COMMISSIO:-IBR FOR PATENTS
`P.O. Dox 1450
`Al•xan<lria. Vu!PJU. 22313-1450
`www.wq.ilo.gt.>v
`
`CONFIRMATION NO. 2171
`
`CLASS
`257
`
`GROUP ART UNIT
`2815
`
`ATIORNEY DOCKET
`NO.
`16820.P097
`
`I lllllll lllll lllll lllll lllll llllll llll 11111111111111111111111111111111
`Bib Data Sheet
`
`FILING DATE
`03/31/2000
`
`RULE
`
`SERIAL NUMBER
`09/540,610
`
`~A.PPLICANTS
`
`James E. Nulty, San Jose, CA;
`
`Christopher J. Petti, Mountain View, CA;
`
`**CONTINUING DATA*************************
`This application is a DIV of 08/577,751 12/22/1995 PAT 6,066,555
`
`**FOREIGN APPLICATIONS********************
`
`IF REQUIRED, FOREIGN FILING LICENSE GRANTED
`** 06/02/2000
`
`Foreign Priority claimed
`
`Q yes rJi' ,/
`35 USC 119 (a-d) conditions met Q yes ~ Q Met after Allowance
`~erified and Acknowledged Examiner's Signature
`
`STATE OR
`
`SHEETS
`
`TOTAL
`
`INDEPENDENT
`
`COUNTRY
`CA
`
`DRAWING
`8
`
`CLAIMS
`13
`
`CLAIMS
`2
`
`lnltials
`
`ADDRESS
`26263
`SONNENSCHEIN NATH & ROSENTHAL LLP
`P.O. BOX 061080
`WACKER DRIVE STATION, SEARS TOWER
`CHICAGO, IL
`60606-1080
`
`TITLE
`STRUCTURE HAVING REDUCED LATERAL SPACER EROSION
`
`FILING FEE
`
`RECEIVED
`690
`
`FEES: Authority has been given in Paper
`No.
`to charge/credit DEPOSIT ACCOUNT
`No.
`for following:
`
`ICJ All Fees
`
`I
`
`I
`
`ICJ1.16·Fees(Filing)
`
`jc:J 1.17 Fees (Processing Ext. of time )I
`I
`jc:J 1.18Fees(lssue)
`I
`jc:J Other
`I
`jc:J Credit
`
`•
`
`SAMSUNG-1002.007
`
`

`
`Page I of I
`
`c<>tn~ls$""n•"''f.,.; Pt.l&t\ts.
`· wasnlogwr" ·O'e .:zo;t:~M
`· ·· .www..:~s;plOlgov
`
`CONFIRMATION NO. 2171
`
`CLASS
`257
`
`GROUP ART UNIT
`2815
`
`ATTORNEY
`DOCKET NO.
`16820.P097
`
`1111111111111111111111111111111111111111111111111111111111111111111111
`Bib Data Sheet
`
`SERIAL NUMBER
`09/540,610
`
`FILING DATE
`03/31/2000
`RULE
`
`~PPLICANTS
`James E. Nulty, San Jose, CA;
`Christopher J. Petti, Mountain View, CA;
`**CONTINUING DATA************************* '(~';, At pl iLA.ti-"""
`
`** FOREIGN APPLICATIONS ******************** 11on e
`
`( Y\•"3
`
`IF REQUIRED, FOREIGN FILING LICENSE GRANTED
`** 06/02/2000
`
`~
`
`t-lo. oJ£11 ?~( (Vee. l-l., l~<f!>) Ct:..
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`~ :t 1~31~ (' -('.
`~ x~iner's SiQnature
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`Verified and
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`~\DDRESS
`26263
`
`STATE OR
`COUNTRY
`CA
`
`SHEETS
`. DRAWING
`8
`
`TOTAL
`CLAIMS
`1-3-i.~
`
`INDEPENDENT
`CLAIMS
`2
`
`TITLE
`
`STRUCTURE HAVING REDUCED LATERAL SPACER EROSION
`
`FILING FEE FEES: Authority has been given in Paper
`to charge/credit DEPOSIT ACCOUNT
`'RECEIVED No.
`for following:
`No.
`690
`
`0 All Fees
`0 1.1.6 Fees (Filing)
`0 1.17 Fees (Processing Ext. of
`time)
`lo 1.18Fees(lssue)
`lo Other
`lo Credit
`
`I
`I.
`I
`
`•
`
`SAMSUNG-1002.008
`
`

`
`I
`I
`
`ii
`
`I lllllll lllll lllll lllll lllll lllili'illl11~lllll.~\l l\!ll ll'.~,;;;11111111
`
`Bib Data Sheet
`
`UNITED STATES DEPARTMENT OF COMMERCE
`Patent and Trademark Office
`·
`Address: COMMISSIONER OF PA TENTS AND TRADEMARKS
`Washington, D.C. 20231
`
`SERIAL NUMBER
`09/540,610
`
`FILING DATE
`03/31/2000
`RULE
`-
`
`CLASS
`438
`
`GROUP ART UNIT
`2812
`
`ATTORNEY
`DOCKET NO.
`1B820.P097
`
`Al-'1-'Lll;AN I~
`James E. Nulty, San Jose, CA;
`Christopher J. Petti, Mountain View, CA;
`
`**CONTINUING DATA*************************
`
`)'e5
`
`"*FOREIGN APPLICATIONS********************
`(.. C.
`fH one.
`IF REQUIRED, FOREIGN FILING LICENSE GRANTED
`-
`** 0610212000
`CJ yes C3' no
`Foreign Priority claimed
`35 use 119 (a-d) conditions CJ yes [!(no CJ Met after
`met
`~-AIJ.L,_~h=
`C (
`.
`Verified and
`_Jg~
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`Examiner's Signature
`Initials
`!Acknowledged
`AUUKESS
`
`I-lo. 08 ~717.S-/
`App/,·c"'iiav-
`1'5$ut>.f. h1«j 2-3_. ;i.ooo)
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`(_ ('_
`
`SHEETS
`STATE OR
`COUNTRY DRAWING
`8
`CA
`
`TOTAL
`CLAIMS
`13
`
`INDEPENDENT
`CLAIMS
`2
`
`Blakely Sokoloff Taylor & Zafman
`12400 Wilshire Boulevard
`!Seventh Floor
`-OS Angeles ,CA 90025
`
`TITLE
`
`-
`
`STRUCTURE HAVING REDUCED LATERAL SPACER EROSION
`
`FILING FEE FEES: Authority has been given in Paper
`RECEIVED No.
`to charge/credit DEPOSIT ACCOUNT
`690
`No.
`for following:
`
`I
`I
`
`ICJ All Fees
`ICJ 1.16 Fees (Filing)
`CJ 1.17 Fees ( Processing Ext. of
`time)
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`. ··--·--
`I CJ 1.18 Fees ( Issue ) ~
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`SAMSUNG-1002.009
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`

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`"Express Mail" mailing label number EL3.
`Date of Deposit MARCH 31. 2000
`
`4742US.
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`00/\£/£0.
`\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~\\\\\\\\\
`PATENT APPLICATION TRANSMITTAL LETTER
`To the Asi>ii9ri~m~~~~~ner for Patents:
`Transmitted herewith for filing is the patent application of: NULTY. et al. for: METHOD FOR ELIMINATING LATERAL SPACER
`
`Case No. 10200/12
`
`EROSION ON ENCLOSED CONTACT TOPOGRAPHIES DURING RF SPUTIER CLEANING. Enclosed are:
`
`!8J
`D
`!8J
`D
`D
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`~ sheet(s) of drawings, 34 pages of application (including title page), and the following Appendices : __ .
`
`Declaration.
`
`Power of Attorney.
`
`Verified statement to establish small entity status under 37 CFR §§ 1.9 and 1.27.
`
`Assignment transmittal letter and Assignment of the invention to : __ .
`
`COPY OF DECLARATION FROM PARENT APPLICATION (08/577,751); PRELIMINARY AMENDMENT.
`
`Claims as Filed
`(:Jar
`
`Col. 1
`No. Filed
`
`Col. 2
`No. Extra
`
`Small Entit
`Rate
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`14-20
`2-3
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`0
`0
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`;;::it the difference in col. 1 is less than zero,
`')enter "O" in col. 2.
`
`x$9=
`x$39=
`+$130=
`
`Total
`
`$
`
`Fee
`$ 345
`$
`$
`$
`
`or
`or
`or
`or
`or
`or
`
`Other Than
`Small Entit
`
`x$18=
`x$78=
`+$260=
`
`Total
`
`Fee
`$ 690
`$
`$
`$
`
`$690
`
`,o
`t~
`:J8J
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`D
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`Please charge my Deposit Account No. 23-1925 in the amount of$: __ . A duplicate copy of this sheet is enclosed.
`
`A check in the amount of$: 690.00 to cover the filing fee is enclosed.
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`The Assistant Commissioner is hereby authorized to charge payment of the following fees associated with this communication
`or credit any overpayment to Deposit Account No. 23-1925. A duplicate copy of this sheet is enclosed.
`l8J
`l8J
`The Assistant Commissioner is hereby authorized to charge payment of the following fees during the pendency of this
`application or credit any overpayment to Deposit Account No. 23-1925. A duplicate copy of this sheet is enclosed.
`D
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`Any filing fees under 37 CFR § 1.16 for presentation of extra claims.
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`Any patent application processing fees under 37 CFR § 1.17.
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`The issue fee set in 37 CFR § 1.18 at or before mailing of the Notice of Allowance, pursuant to 37 CFR § 1.311 (b).
`
`Paul E. Rauch, Ph.D.
`BRINKS HOFER GILSON & LIONE
`Registration No. 38,591
`
`Rev. Nov-98
`X:\PER\ 10200-12 Transmittal letter 000331.doc
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`SAMSUNG-1002.010
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`

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`Our Reference: 16820.P097
`
`APPLICATION FOR UNITED STATES PATENT
`
`FOR
`
`METIIOD FOR ELIMlNATING LATERAL SPACER
`EROSION ON ENCLOSED CONTACT TOPOGRAPIBES
`DURING RF SPUITER CLEANING
`
`Inventors:
`
`JAMES E. NULTY
`CHRISTOPHERJ.PETTI
`
`Prepared by:
`
`BLAKELY SOKOLOFF TAYLOR & ZAFMAN
`12400 Wilshire Boulevard
`Seventh Floor
`Los Angeles, CA 90025
`(310) 207-3800
`
`I hereby certify that this correspondence is
`being deposited with the United States Postal
`Service as Express Mail (Label No: TS IS"C'ot~'-1 <..')l..
`in an envelope addressed to: Commissioner of Patents
`~gton, D.C 20231 o
`/ ~w;:-"33, I 'l'l>
`
`
`
`1:
`
`Name
`
`Dare
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`SAMSUNG-1002.011
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`Field of the Invention:
`
`The invention relates to semiconductor device processes, and more
`
`particularly, to improved methods for etching openings in insulating layers and a
`
`5
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`semiconductor device with well defined contact openings.
`
`Background of the Invention
`
`In the fabrication of semiconductor devices, numerous conductive device
`
`regions and layers are formed in or on a semiconductor substrate. The conductive
`
`regions and layers of the device are isolated from one another by a dielectric.
`
`10
`
`Examples of dielectrics include silicon dioxide, Si02, tetraethyl orthosilicate glass
`
`("TEOS"), silicon nitrides, SixNy, silicon oxynitrides, SiOxNy(Hz), and silicon
`
`dioxide/ silicon nitride/ silicon dioxide ("ONO"). The dielectrics may be grown, or
`
`may be deposited by physical deposition (e.g., sputtering) or by a variety of chemical
`
`deposition methods and chemistries (e.g., chemical vapor deposition ("CVD")).
`
`15 Additionally, the dielectrics may be undoped or may be doped, for example with
`
`boron, phosphorous, or both, to form, for example, borophosphosilicate glass
`
`("BPSG"), phosphosilicated glass ("PSG"), and borophosphosilicate tetraethyl
`
`orthosilicate glass ("BPTEOS").
`
`~ At sev al stages of the fabrication of semiconductor devices, it is necessary to
`
`e dielectric to allow for contact to underlying regions or layers.
`
`rvfo 2~ make openings in
`l
`
`Generally, an opening hrough a dielectric exposing a diffusion region or an
`
`opening through a dielect · c layer between polysilicon and the first metal layer is
`
`called a "contact opening", w · e an opening in other oxide layers such as an
`
`opening through an intermetal di ectric layer is referred to as a "via". For purposes
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`of the c~~ ed invention, henceforth "contact opening" or "contact region" will be
`
`used to::::>: contact openings and/or via. The opening may expose a device
`
`other layer or stru
`
`e, for example, an underlying metallization layer, local
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`5
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`interconnect layer, or
`
`ucture such as a gate. After the opening has been formed
`
`egion or layer to be contacted, the opening is generally
`
`cleaned with a sputter etch, e.g., a Radio-Frequency ("RF") sputter etch, and then the
`
`opening is filled with a cond '\tive material deposited in the opening and in
`electrical contact with the underl')Qgg_region ~r lscy..er__.
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`10
`
`To form the openings a patterning layer of photoresist is first formed over the
`
`dielectric layer having openings corresponding to the regions of the dielectric where
`
`the dielectric layer openings are to be formed. In most modern processes a dry etch
`
`is then performed wherein the wafer is exposed to a plasma, formed in a flow of one
`
`or more gases. Typically, one or more halocarbons and/or one or more other
`
`IS
`
`halogenated compounds are used as the etchant gas. For example, CF4, CHF3 (Freon
`
`23), SF6, NF3, and other gases may be used as the etchant gas. Additionally, gases
`
`such as 02, Ar, Ni, and others may be added to the gas flow. The particular gas
`
`mixture used will depend on, for example, the characteristics of the dielectric being
`
`etched, the stage of processing, the etch tool being used, and the desired etch
`
`20
`
`characteristics, i.e., etch rate, sidewall slope, anisotropy, etc.
`
`Many of the etch characteristics are generally believed to be affected by
`
`polymer residues that deposit during the etch. For this reason, the fluorine to
`
`carbon (F IC) ratio in the plasma is considered an important determinant in the etch.
`
`In general, a plasma with a high F IC ratio will have a faster etch rate than a plasma
`
`25 with a low F /C ratio. At very low rates, i.e., high carbon content, polymer
`deposition occurs and etching ceases. The etch rate as a function of the F /C ratio is
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`typically different for different materials. The difference is used to create a selective
`
`etch, by using a gas mixture that puts the F /C ratio in the plasma at a value that
`
`leads to etching at a reasonable rate for one material, and that leads to no etching or
`
`polymer deposition for another. For example, an etchant that has an etch rate ratio
`
`5
`
`or a selectivity ratio of two to one for silicon nitride compared to silicon dioxide is
`
`an effective stripper of silicon nitride from the semiconductor substrate, because it
`
`will selectively strip silicon nitride over silicon dioxide on a substrate surface. An
`
`etchant that has an etch rate ratio or a selectivity ratio of 0.85 to one for silicon
`
`nitride compared to silicon dioxide is not considered an effective stripper of silicon
`
`10
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`nitride from the semiconductor substrate because the etchant will not effectively
`
`strip silicon nitride to the exclusion of silicon dioxide.
`
`The selectivity of the etch process is a useful parameter for monitoring the
`
`process based on the etch rate characteristic of the particular etchant. As noted
`
`above, particular etchants or etchant chemistries attack different materials at
`
`15
`
`different etch rates. With respect to dielectrics, for example, particular etchants
`
`attack silicon dioxide, BPTEOS, TEOS, and silicon nitride dielectrics at different rates.
`
`To make op€nings
`
`in a substrate comprising a contact region surrounded by
`
`different dielectric layers, e.g., a dielectric layer of TEOS surrounded by a dielectric
`
`layer of silicon nitride, a process will utilize different etchants to make openings
`
`20
`
`through the different dielectrics. Thus, the different etch rates of particular dielectric
`
`layers for an etchant may be used to monitor the creation of an opening through a
`
`dielectric layer.
`
`Further, by adjusting the feed gases, the taper of the sidewall in the etched
`
`opening of the dielectric can be varied. If a low sidewall angle is desired, the
`
`25
`
`chemistry is adjusted to try to cause some polymer buildup on the sidewall.
`
`Conversely, if a steep sidewall angle is desired, the chemistry is adjusted to·try to
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`prevent polymer buildup on the sidewall. Varying the etch gas pressure, for
`
`example, has a significant effect on the shape of the opening. This is because the
`
`etchant ions generally arrive in a direction perpendicular to the substrate surface,
`
`and hence strike the bottom surfaces of the unmasked substrate. The sidewalls of
`
`s
`
`etched openings, meanwhile, are subjected to little or no bombardment. By
`
`increasing the pressure of the etch gas, the bombardment directed toward the
`
`sidewalls is increased; by decreasing the pressure of the etch gas, the bombardment
`
`directed toward the sidewalls is decreased. The changing of the etch chemistry is
`
`also directly related to selectivity. Etchants that provide a near 90° sidewall angle are
`
`10
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`generally not highly selective while highly selective etches typically produce a
`
`sloped sidewall.
`
`Following the dielectric etch(es) and prior to any conductive material
`
`deposition in a contact region, native oxide on top of the conducting layers in the
`
`contact region is removed or cleaned through a non-chemical sputter etch, e.g., an
`
`15
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`RF sputter etch. In addition to alleviating the contact region of native oxide, the
`
`sputter etch can erode any insulating dielectric layer or layers. Thus, the parameters
`
`of the sputter etch must be carefully monitored so as not to excessively erode the
`
`insulating dielectric layer(s) and expose other underlying conductive material.
`
`Exposing insulated conductive material adjacent to the conductive material in the
`
`20
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`contact region results in poor quality contacts or a short circuit through the
`
`underlying conductive material. For a thorough discussion of oxide etching, see S.
`
`Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, Vol. 1, pp. 539-85 (1986) .
`
`.....__
`
`The prece~ discussion focused on the making of openings, e.g., contact
`/\} f)g, ~penings, in dielectri material on a semiconductor substrate. The same principles
`
`{ v· 25
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`are used in constructin device regions with a dielectric layer or layers. As
`
`geometries shrink, the for
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`ing of discreet devices on a semiconductor substrate
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`becomes more sp
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`·alized. Specialized deposition and etching techniques permit
`
`the density of semicondu ~ents on a single chip to greatly increase, which
`
`translates into larger memory, fas~rating speeds, and reduced production costs.
`
`A typical metal oxide semiconductor (MOS) transistor, e.g., NMOS or PMOS
`
`5
`
`transistor, generally includes source/drain regions in a substrate, and a gate
`
`electrode formed above the substrate between the source/ drain regions and
`
`separated from the substrate by a relatively thin dielectric. Contact structures can be
`
`inserted to the source/ drain regions and interlays can overlie the contact structures
`
`and connect neighboring contact structures. These contact structures to the
`
`10
`
`diffusion region are isolated from the adjacent gate by dielectric spacer or shoulder
`
`portions. The dielectric spacer or shoulder portions also isolate the gate from the
`
`diffusion region.
`
`Conventional contact structures limit the area of the diffusion region, because
`
`the contact hole is aligned to these regions with a separate masking step, and extra
`
`15
`
`area must be allocated for misalignment. Proper alignment is necessary to avoid
`
`shorting the contact structure to the gate or the diffusion well. The larger contact
`
`area means a smaller density of elements on a structure. The larger contact area is
`
`also responsible for increased diffusion-to-substrate junction capacitance, which
`
`limits device speed.
`
`20
`
`A self-aligned contact eliminates the alignment problems associated with
`
`conventional contact structures and increases the. device density of a structure. A
`
`self-aligned contact is a contact to a source or drain diffusion region. A self-aligned
`
`contact is useful in compact geometries because it can overlap a conducting area to
`
`which it is not supposed to make electrical contact and can overlap the edge of a
`
`25
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`diffusion region without shorting out to the well beneath. Consequently, less
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`contact area is needed and gates or conductive material lines, e.g., polysilicon lines,
`
`can be moved closer together allowing more gates or lines on a given substrate than
`
`traditional contacts.
`
`· gure 1 illustrates a self-aligned contact between two gate structures. Figure
`
`anar top view of the contact. Figure l(B) is a planar cross-sectional view
`
`of a self-all ed contact between a pair of gates taken through line l{B) of Figure
`
`l(A). Figure 1 C) is a planar cross-sectional view of a self-aligned contact between a
`
`through line l(C) of Figure l{A).
`
`10
`
`or p+ silicon) 140 that n overlap the edge of the diffusion region 140 without
`
`contact is a contact to a source or drain diffusion region (n+
`
`shorting out to the well b eath the diffusion region 140. This can be seen most
`
`illustratively through Figure C). In Figure l(C), the contact 130 does not lie directly
`
`in the diffusion region 140, but misaligned and slightly overlaps the field oxide.
`
`In this illustration, the self-aligned ontact is not directly over the diffusion region
`
`15
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`but extends over (i.e., overlaps) a wel portion 170. The self-aligned contact does not
`
`short to the well portion 170 because th self-aligned contact is separated from the
`
`well 170 by the field oxide.
`
`The self-aligned contact 130 is separate from a conducting polysilicon layer
`
`110 by an encapsulating dielectric layer 120 such
`
`at the contact 130 can also overlap
`
`20
`
`the polysilicon layer 110 without making electrical ontact to the layer 110 or gate.
`
`The polysilicon layer 110 is separated from the source drain diffusion region 140 by
`
`a dielectric spacer or shoulder 150 of the same or cliffere t dielectric material as the
`
`dielectric layer 120 directly above the conducting polysilic
`
`A distinct dielectric etch stop layer 125 overlies the enca
`
`25
`
`layer 120. The etch stop layer 125 permits subsequent etching of \substrate
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`without ris of exposing the device structures and layers because the device
`
`structuring and
`
`ers are protected from excessive etching by the etch stop layer.
`
`The diffusion contact · self-aligning because the structure can be etched to the
`
`substrate over the source
`
`rain diffusion region 140 while the dielectric spacer 150
`
`s
`
`protects the polysilicon layer
`
`0. Even if a photoresist that protects the polysilicon
`
`·layer 110 from the etchant is misa ·~ed-with respect to the polysilicon layer 110, the
`
`dielectric spacer 150 prevents shorts t~ polysilicon layer 110 when the contact 130
`
`is provided for the diffusion region 140. -
`
`/\.Ji Plj ~ e current practice with respect to forming contact regions, particularly self-
`laiigned c
`tact regions, that are in electrical contact with gates, interconnect lines, or
`( V" 10
`
`es in small feature size structures utilize etchants with high selectivity
`
`ing regions, like the etch stop layer and the first insulating layer.
`
`Figure 2 demonstr es a typical prior art process of forming a self-aligned contact
`
`region adjacent to a ga e. In Figure 2(A), a gate oxide layer 210 is formed on a
`
`15
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`substrate 200 with a cond cting layer, for example a polysilicon layer 220, overlying
`
`the gate oxide layer 210, and n insulating layer, for example a TEOS layer 230,
`
`overlying the polysilicon layer
`
`Adjacent to the polysilicon layer is a contact
`
`opening region 270. The polysilico
`
`layer 220 is separated from the contact region
`
`270 by an insulating spacer portion, fo example a TEOS spacer portion 235. A
`
`20
`
`separate insulating or etch stop layer, for' xample a silicon nitride layer 240 overlies
`
`the TEOS layer 230 and the contact region 2
`
`. A blanket layer, for example a doped
`
`insulating layer like a BPTEOS layer 250, plana
`
`overlies the etch stop layer 240.
`
`A layer of photoresist material 280 overlies t
`
`planarized BPTEOS layer 250
`
`to expose the contact opening 270. In Figure 2(A), a co tact opening 270 has been
`
`25
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`opened through the BPTEOS layer 250. The etchant utili d to make the opening
`
`had a high selectivity toward BPTEOS relative to silicon ni
`
`· e. When the contact
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`was through the BPTEOS material, the etchant did not etch or did not
`
`effectively ch the silicon nitride layer 240 material. Hence the description of the
`
`silicon nitride 1 er 240 as an etch stop layer. The silicon nitride etch stop layer
`
`protected the un~r.ing TEOS layer so that the polysilicon remains completely
`encapsulated. ~
`
`5
`
`~ igure 2(A) illustrates an etch 260 to remove the silicon nitride etch stop layer
`
`etch illustrated.in Figure 2(A), a high selectivity etch toward silicon
`
`l'l}(Jl~//240. Int
`l u
`
`nitride relati e to the underlying TEOS layer 230 material is practiced to efficiently
`
`etch the silicon
`
`'tride layer and to protect the underlying TEOS layer 230 from the
`
`10
`
`etchant. An exam le of a high selectivity etch recipe to effectively strip silicon
`the TEOS layer is 30 seem CHF3 and 30 seem 02 at 60 mtorr
`
`nitride as compared
`
`and 100 watts of power. The result of the high selectivity etch is illustrated in Figure
`
`2(B).
`
`e silicon nitride selective etch effectively removed
`
`15
`
`silicon nitride 240 from the conta opening 270. The selective etch for silicon
`
`nitride compared to TEOS material, owever, left the TEOS layer 230 with a spacer
`
`portion 235 wherein the spacer portion · sloping or tapered toward the contact
`
`opening. This result follows even where
`
`e spacer portion 235 is originally
`
`substantially rectangular as in Figure 2(A).
`
`e properties of the highly selective
`
`20
`
`etch of the overlying etch stop layer will transf ma. substanti~!JY_!~<:_t_angcl.ar_spacer ___ _
`
`into a sloped spacer. Fig1JI~?.(B) presents a polys· 'con layer 220 encapsulated in a
`
`TEOS layer 230 with a spacer portion 235 adjacent to
`
`e contact opening 270, the
`
`spacer portion 235 having an angle 290 that is less than 5°.
`
`In addition to providing stopping points or selectivi between materials, the
`
`25
`
`use of high selectivity etches to form sloped spacer portions is
`
`e preferred practice
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`i'
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`because the slo ed shape will result in good step coverage by the metal that is
`
`deposited into it. The filling of. contact openings or gaps (i.e., gap fill) is an
`
`important considera ·on because it relates directly to the reliability of a device. If an
`
`opening is not comp!~ filled with a insulative material, for example, and a gap is
`
`5
`
`created, a subsequent cond\ctive material deposit can fill the gap which can lead to
`shorting. Sloped contact op~gs are easier to completely fill than boxy structures
`because the transition between oped structures and openings is smooth compared
`
`to the abrupt transitions between l:l xy structures and openings. Be