`
`United States Patent (1)
`Tokeet al.
`
`[11]
`[45]
`
`4,138,718
`Feb. 6, 1979
`
`[54] NUMERICAL CONTROL SYSTEM WITH
`DOWNLOADING CAPABILITY
`
`(75]
`
`Inventors: Ronald J. Toke, Bratenahl Village;
`William A. Donze, Mentor, both of
`Ohio
`
`Bensaude et al.-“Host Processor Contro! of Satellite
`Disk Storage”.
`
`Primary Examiner—Harvey E. Springborn
`Altorney, Agent, or Firm—Quarles & Brady
`
`[73] Assignee: Allen-Bradley Company, Milwaukee,
`Wis.
`
`[21] Appl. No.: 850,927
`[22] Filed:
`Nov. 14, 1977
`[ST],
`Tints CU? ccstsiccsveiscvaciseiss GO6F 3/02; GO6F 13/00
`[52] WS OU,
`esssssscnnsssosnetsonsnseresascseswosnsesansmaases 364/200
`[58] Field of Search ... 364/200 MS File, 900 MS File
`[56]
`References Cited
`U.S. PATENT DOCUMENTS
`
`ABSTRACT
`[57]
`A numerical control system which employs a pro-
`grammed numerical control processor to perform the
`numerical control functions is coupled to a bulk storage
`device by a host computer. The bulk storage device
`stores a download library which includes not only part
`programs, but also system software programs and diag-
`nostic programs which may be downloaded to the nu-
`merical control system upon request. By downloading a
`system software program the numerical control capabil-
`3,626,385
`12/1971 Bouman... cceesseeessseenene 364/200
`ities of the system can be completely reconfigured to, in
`3,744,031
`lve
`7/1973 Averyetal..
`
`essence, provide a new machine.
`
`3,810,104 5/1974=Markley .........cccccsesseecens 364/200
`OTHER PUBLICATIONS
`
`IBM TDB-vol. 14, No. 11, Apr. 1972, pp. 3418-3419
`
`9 Claims, 22 Drawing Figures
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 1
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 1
`
`

`

`Sheet 1 of 21
`
`4,138,718
`
`U.S. Patent
`
`Feb. 6, 1979
`
`
`
`PMC Exhibit 2075
`Apple v. P
`IPR2016-00753
`Page 2
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 2
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 2 of 21
`
`4,138,718
`
`‘Sig, 2
`
`i1
`
`PMC Exhibit 2075
`Apple v. P
`IPR2016-00753
`Page 3
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 3
`
`

`

`
`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 3 of 21
`
`4,138,718
`
`NUMERICAL
`
`CONTROL
`
`MEMORY
`
`al
`uJ
`
`=<
`
`WY
`
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`IS
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`
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`
`Na<u
`
`wx
`
`a
`Hil a
`Lara
`— —
`
`
`PROCESSOR
`NUMERICAL
`CONTROL
`
`WwW =
`WW ALM
`STORAGE
`MEMORY
`
`Mi]\ fil R A CcK
`
`1 NHiil\ R A G K 2 TW N
`
`20
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`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 4
`
`W
`
`1
`
`\ f
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 4
`
`

`

`U.S. Patent
`
` Feb..6, 1979
`
`Sheet 4 of 21
`
`4,138,718
`
`wh
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`===261={|eST---S-=>--=---==—SBW==eeae|3YWvM140S
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`aesa1ev.
`
`¥3LS1938
`
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`
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`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 5
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 5
`
`
`
`
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 5 of 21
`
`4,138,718
`
`JILSWHLINY
`
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`
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`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 6
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 6
`
`
`
`
`
`
`
`
`
`

`

`US.
`
`Patent
`
`Feb. 6, 1979
`
`Sheet 6 of 21
`
`4,138,718
`
`nq
`
`
`
` +\|mnLL,4300030&—pag177SS
`
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`
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`
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`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 7
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 7
`
`
`
`
`
`
`
`
`

`

`Feb. 6, 1979
`
`Sheet 7 of 21
`
`ADDRESS
`
`U.S. Patent
`
`REGISTER
`
`4,138,718
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 8
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 8
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 8 of21
`
`4,138,718
`
`BINARY
`
`TO
`
`OCTAL
`
`DECODER
`
`129
`
`140,
`
`ig.7
`
`
`
`30
`
`~Vbndr nn - 9
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 9
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 9
`
`

`

`
`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 9 of 21
`
`4,138,718
`
`FROM
`
`FROM
`
`START
`
`Sig. 6A
`
`DISABLE
`INTERRUPTS ¢
`TURN-OFF
`OUTPUTS
`
`
`
`FETCH DOWN-
`LOAD REQUEST
`WORD & JUMP
`TO TRANSMIT
`SUBROUTINE
`
`5I1
`
`525
`
`526
`
`527
`
`529
`
`530
`
`
`
`
`FETCH VERSION
`1.0. CHARACTER&
`JUMP TO
`TRANSMIT
`SUBROUTINE
`
`
`
`
`
`
`
`JUMP TO
`RECEIVE
`SUBROUTINE
`
`NEGATE ¢@
`STORE RECORD
`SIZE AT
`
`“COUNT”
` INITIALIZE
`CHECKSUM IN
`
`B REGISTER
`
`528
`
`JUMP TO
`RECEIVE
`SUBROUTINE
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 10
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 10
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 10 of 21
`
`4,138,718
`
`‘Sig. &B
`
`ADDRESS OF
`DOWNLOADED
`RECORD AT
`
`“ADDR"™
`
` STORE STARTING
`
`
`
`
` CHECK “ADDR”
`
`
`TO DETERMINE
`
`IF WITHIN
`
`COMMUNICATIONS
`PROGRAM
`
`
`“ADDRESS ERROR’
`ON CRT 9
`
`_
`
`
`
`
` JUMP TO
`RECEIVE
`
`SUBROUTINE
`
` INDICATE
`
`
` STORE
`INSTRUCTION IN
`
`MEMORY 30
`
`AT LOCATION
`INDICATED BY
`
`
`"ADDR"
`
` 535
`INCRE ME NT
`
`“A DDR" €“COUNT"™
`
`& UPDATE
`CHECKSUM
`
`ACCUMMULATOR 536
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 11
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 11
`
`

`

`
`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 11 of 21
`
`4,138,718
`
` JUMP TO
`
`RECEIVE
`SUBROUTINE
`
`
`
`COMPARE
`
`CHECKSUM WORD
`WITH
`CHECKSUM
`ACCUMMULATOR
`
`
`
`INDICATE
`“CHECKSUM
`
`
`ERROR"
`
`
`ON CRT 9
`
`
`Sig. &C
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 12
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 12
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 12 of 21
`
`4,138,718
`
`idNyy3.Nni
`
`NOILYOd
`
`30
`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
`Sl
`
`ONNOYONOVSG
`
`S3NILNOY
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 13
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 13
`
`
`
`
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 13 of 21
`
`4,138,718
`
`Sig. 10
`
`
`
`INITIALIZE
`FOR NEW
`
`
`
`
`KEY BOARD
`
`
`
`
`
`ROUTINE
`
`
`UPDATE
`
`
`MANUAL
`
`
`
`PROGRAM
`ROUTINE
`
`
`CRT
`
`DISPLAY
`
`
`
`INITIALIZE
`
`
`CALL BLOCK
`TAPE
`
`
`EXECUTE
`
`
`READER
`ROUTINE
`
`
`FILL UP
`
`
`DECODE
`FROM TAPE
`
`
`
`AND SET UP
`READER
`
`1ST BLOCK
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 14
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 14
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 14 of 21
`
`4,138,718
`
`
` BLOCK
`
`EXECUTE
`
`ROUTINE
`
`‘Sic, A
`
`BUFFERS
`
`
`INITIALIZ
`
`ASC IE DATA
`
`
`SET UP
`BLOCK
`EXECUTION
`FLAGS
`
`YES
`
`BLOCK
`‘DELETE
`
`?
`
`
`
`
`EXCHANGE
`RESET
`
`STATE OF
`ACTIVE AND
`
`PREVIOUS
`TEMPORARY
`
`
`
`BUFFER POINTER
`BLOCK
`
`
`
`EXECUTE
`PRELUDE
`
`
`
`UPDATE
`FUNCTIONS AND
`
`MAKE BLOCK
`POINTERS
`
`
`
`TO NEXT
`ACTIVE
`
`
`BLOCK
`
`
`
`
`ENABLE
`INTERPOLATION
`
`
`
`SET UP
`
`NEXT
`
`BLOCK
`
`
` INITIATE
`
`
`TAPE READER
`
`
`IF STORAGE
`AVAILABLE
`
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 15
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 15
`
`

`

`
`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 15 of 21
`
`4,138,718
`
`Sis. 1B
`
`UPDATE
`
`UPDATE
`
`
`
`
`
`
`
`CRT
`CRT
`
`
`
`DISPLAY
`DISPLAY
`
`
`
`
`
`POSTLUDE
`
`
`FUNCTIONS
`
`
`
`
`“ee OF BLOCK
`
`END
`
` EXECUTE
`
`
`=\OYFORCE
`
`UPDATE
`
`CRT
`DISPLAY
`
`CYCLE
`
`sTOP
`
`NO
`
`OFFSETS
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 16
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 16
`
`

`

`
`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 16 of 21
`
`4,138,718
`
`Sig, 120
`
`YES
`
`sie
`
`REGISTERS
`
`
` 10 MSE
`
`INTERRUPT
`
`
`FLAGS
`
`PRELUDE @
`POST LUDE
`
`
`SERVO-
`MECHANISM
`
`
`SERVICE
`
`
`ROUTINE
`
`
`M CODE
`
`
`STATUS OF
`SENSING
`
`
`
`
`
`DEVICES EXECUTE
`ROUTINE
`
`187
`
`194
`
`MACHINE
`DEPENDANT
`SOFTWARE
`
` OUTPUT
`
`
`STATUS OF
`OPERATING
`DEVICES
`
`
`
`INHIBIT
`
`INTERPOLATION
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 17
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 17
`
`

`

`
`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 17 of 21
`
`4,138,718
`
`(R
`
`.
`
`“Sig. 12B
`
`END
`OF BLOCK
`
`NO
`
`RESET
`POSTLUDE
`FLAG
`
`OR
`
`YES
`
`ANY
`STOP
`
`“ages
`YES
`
`REQUEST
`
`CYCLE
`
`EMERGENCY\,YES
` TURN ON
`STOP
`
`PROGRAM
`STOP FLAG
`
`
`
`
`
`
`
` SET END
`
`OF
`PROGRAM
`FLAGS
`
`EOB
`sToP
`?
`
` REQUEST
`
`
`
`cYCLE
`
`STOP
`
`SUBROUTINE
`
`EXIT
`
`RESTORE
`
`NOT BUSY REGISTERS
`
`SET TIMED
`INTERRUPT
`FLAG TO
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 18
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 18
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 18 of 21
`
`4,138,718
`
`Sis. 138A
`
`518
`
`
`
`DISSABLE
`INTERRUPTS
`S)
`
`
`TURN OF
`OUTPUT DEVICES
`
`513
`
`5)4
`
`FROM
`i368
`
` RECEIVE
`REPLY FROM
`HOST COMPUTER
`AND DISPLAY ON
`CRT 9
`
`
`
`
`
`DISPLAY
`“READY”
`
`ON CRT 9
`
`
`
`
`INPUT COMMAND
`
`TRANSMIT
`FROM
`
`COMMAND
`
`
`
`KEYBOARD 7
`TO HOST
`
`
`COMPUTER
`
`
`“SIGN ON”
`COMMAND?
`
`SI7
`
`
`
`
`
`DISPLAY
`am
`n
`
`
`
`
`DOW NLOAD
`
`aK
`COMMAND ?
`
`
`ON CRT 9
`
`YES
`
`S2l
`
`TRANSMIT
`DOWNLOAD
`COMMAND TO
`HOST COMPUTER
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 19
`
`

`

`
`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 19 of 21
`
`4,138,718
`
` 522.
`
`REPLY FROM
`
`HOST COMPUTER
`AND DISPLAY
`
`IT ON CRT9
`
`
`
` RECEIVE
`
`
`
`
`
`523
`
`
`
`TYPE 1"
`
`
`CODE
`
`REPLY
`?
`
`
`JUMP
`TO
`
`“LOAD 2” OF
`RESIDENT
`
`COMMUNICATIONS
`PROGRAM
`
`
`
`"Sis. 13B
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 20
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 20
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 20 of 21
`
`4,138,718
`
`START
`
` Sig, 14
`
`
`
`TRANSMIT
`
`
`
`ERROR
`SECURITY
`2
`
`
`MESSAGE TO
`NC MACHINE
`
`
`RECEIVE AND
`
`STORE MACHINE
`
`IDENTIFICATION
`
`
`TRANSMIT
`’
`n
`
`“BUSY
`RECEIVE AND
`Coae
`STORE FILE
`
`
`
`
`NAME AND TYPE
`
`
`MACHINE
`e
`
`
`
`
`
`
`READ DATA
`
`
`DATA RECORD
`
`RECORD FROM
`
`TO NC
`DOWNLOAD
`
`
`
`MACHINE
`LIBRARY
`
`
`TRANSMIT
`
`
`
`
`
`CONVERT
`DATA RECORD
`TO ASCII
`
`CHARACTERS
`
`554
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 21
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 21
`
`

`

`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 21 of 21
`
`4,138,718
`
`RESIDENT
`COMMUNICATIONS
`PROGRAM (i28 LINES)
`
`HIGHEST 4K MEMORY ADDRESS
`
`Sig, 15
`MEMORY
`
`§5]
`
`READ/WRITE
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 22
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00753
`Page 22
`
`

`

`
`
`4,138,718
`
`2
`library. A manual data entry means such as a keyboard
`is associated with the numerical control processor and
`the download commandis selected by the operator to
`identify a specific program in the download library. In
`this manner different system programs may be down-
`loaded to alter the capabilities of the numerical control
`system to meet the requirements of the machinetool to
`which it is attached and the part being machined.
`The foregoing and other objects and advantages of
`the invention will appear from the following descrip-
`tion. In the description reference is made to the accom-
`panying drawings which form a part hereof, and in
`which there is shown by wayofillustration a preferred
`embodiment of the invention. Such embodiment does
`not necessarily representthe full scope of the invention,
`however, and reference is made to the claims herein for
`interpreting the breadth of the invention.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`1
`
`NUMERICAL CONTROL SYSTEM WITH
`DOWNLOADING CAPABILITY
`
`BACKGROUND OF THE INVENTION
`
`The field of the invention is numerical control sys-
`tems, and particularly, numerical control systems of the
`type which employ programmed processors as the
`means for carrying out the numerical control functions.
`Such a numerical control system is known in the art
`as a computer numerical control or “CNC” and they
`are characterized generally by their use of a pro-
`grammed minicomputer or microprocessor in lieu of
`hardwired logic circuitry. Such a system which em-
`ploys a programmed processoris disclosed in U.S. Pat.
`No. 4,038,533 which issued on July 26, 1977 and is
`entitled “Industrial Control Processor System.” Al-
`though CNC systems are programmable and do there-
`fore offer a certain amount offlexibility, as a practical
`matter the system program which determines the basic
`operational characteristics of the system is seldom al-
`tered once the system is attached to a specific machine
`tool. For example,
`the CNC system may be pro-
`grammed to provide full contouring for a three-axis
`milling machine without automatic tool changer and
`with certain “canned cycles.” That software system is
`usually not altered during the life of the machine despite
`the fact that for much ofthe time the machine tool may
`not require contouring capability and could make better
`use of the memory space occupied by the circular and
`linear interpolation programs.
`The flexibility afforded by the use of a programmable
`processor in a numerical control system has thus never
`been fully realized in prior systems.
`SUMMARYOF THE INVENTION
`
`The present invention relates to a numerical control
`system in which a system program may be readily
`downloaded from a library stored in a bulk storage
`device. More specifically, the invented numerical con-
`trol system includes a main memory, a processor, a
`read-only memory which stores a resident communica-
`tion program, means for transferring the resident com-
`munications program from the read-only memory to the
`main memory and for initiating the execution of said
`program by the numerical control system processor, a
`storage device for storing a plurality of programs in-
`cluding a system program for the numerical control
`system, and a host processor coupled to said storage
`device and said numerical control system processor and
`being responsive to a download command generated by
`said numerical control system processor during its exe-
`cution of the resident communications program to
`download said system program to the main memory,
`wherein the numerical control system processor jumps
`from the resident communications program to said
`downloaded system program after the download has
`been completed.
`A general object of the invention is to download a
`system program to the memory of a CNCsystem. If the
`main memoryis completely empty, as for example, after
`a prolonged power failure or a malfunction which
`erases part or all of the system program, a new system
`program can be downloaded from the download library
`in the storage device byinitiating the execution of the
`resident communications program.
`Another object of the invention is to enable the oper-
`ator to select a system program from the download
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`FIG. 1 is a perspective view of the system of the
`present invention connected to a machine tool;
`FIG. 2 is a perspective view of the numerical control
`system which forms part of the system of FIG. 1 with
`the enclosure door open;
`FIG. 3 is a block diagram of the system of FIG.1,
`FIGS. 4a and 48 are a block diagram ofthe industrial
`control processor which forms part of the system of
`FIG. 3;
`FIG. 5 is a block diagram ofthe arithmetic and logic
`processor which forms part of the industrial control
`processor of FIG. 45;
`FIG. 6 is a block diagram of the input/outputcir-
`cuitry which forms a part of the industrial control pro-
`cessor of FIG. 4b;
`FIG.7 is a schematic diagram of the priority encoder
`circuit which forms part of the industrial control pro-
`cessor of FIG, 4a;
`FIGS. 8a-< are a flow chart of the resident communi-
`cations program which forms part of the industrial con-
`trol processor of FIG.4;
`FIG. 9 is a flow chart of a system program which
`maybe stored in the numerical control processor mem-
`ory;
`FIG.10 is a flow chart of the main controller routine
`which forms part of the software system of FIG. 9;
`FIGS. 11a and 110 is a flow chart of the block exe-
`cute routine which forms part of the software system of
`FIG.9;
`FIGS.12a and 126 is a flow chart of the ten millisec-
`ond timed interrupt routine which forms part of the
`software system of FIG. 9;
`FIGS. 13a and 130 is a flow chart of a program called
`COMPACwhichis stored in the download library;
`FIG. 14 is a flow chart of the download program
`(DNLDNC)stored in the host computer memory of
`FIG.3;
`FIG. 15 is a representation of the contents of the
`numerical control system memory at one stage of the
`download procedure; and
`FIG. 16 is a block diagram of the host computer of
`FIG.1.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`Referring to FIG. 1, a numerical control system is
`housed in a cabinet 1 and connected througha cable 2 to
`a multi-function machine tool with automatic tool
`changer 3. The numerical control system controls the
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`Apple v. PMC
`IPR2016-00753
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`IPR2016-00753
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`cable 2 that leads to the machine tool 3 and mayinclude
`motion of a cutting tool 4 along two or more axes of
`inputcircuits for sensing the status of limit, selector and
`motion in response to a part program which is read
`pushbutton switches such as that disclosed in U.S. Pat.
`from a tape reader 5. In addition, the numerical control
`No. 3,643,115 entitled “Interface Circuit for Industrial
`system operates in response to commands read from the
`Control Systems,” and outputcircuits for driving sole-
`tape reader 5 to control auxiliary functions on the ma-
`noids and motors such as that disclosed in U.S. Pat. No.
`chine tool3, such as automatic tool selection and chang-
`3,745,546 entitled “Controller Output Circuit.” The
`ing from a tool magazine 6, pallet selection and chang-
`ing, spindle speed and coolant operation. The imple-
`input circuits also include position feedback accumula-
`tors which receive feedback data from the position
`mentation of such auxiliary functions involves the sens-
`transducers on the machine tool 3 and the outputcir-
`ing of one-bit signals generated by numerous input de-
`vices such as limit switches, selector switches, and
`cuits include registers for providing axis motion com-
`mand words to the machine tool servo mechanisms.
`photo-electric cells, which are mounted to the machine
`tool 3, and the operation of numerous output devices
`Referring particularly to FIGS. 1-3, the numerical
`control system 1 is connected to a host computer 500
`such as solenoids, lights, relays and motor starters. The
`numbers and types of such input and output devices, as
`through a cable 501 in what is known in the art as a
`well as the manner in which they are operated, will
`DNCconfiguration. The cable 501 connects to a uni-
`versal asynchronous receiver/transmitter (UAR/T) 8
`vary considerably from machine to machine.
`which is mounted within the numerical control proces-
`The numerical control system includes a programma-
`sor housing 13 and it in turn is connected to the numeri-
`ble interface whichallowsit to be easily interfaced with
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`cal control processor 13 through the wire harness 19.
`machine tools of any make and model. This interface is
`The UAR/T8is treated as another input/output device
`accomplished by entering a control program comprised
`of programmable controller-type instructions through a
`by the processor 13 as will be described in more detail
`hereinafter.
`keyboard 7. When this control program is executed the
`The host computer 500 is a general purpose digital
`system operates as a programmable controllerto selec-
`tively sense the status of the particular input devices on
`computer such as the Model 7/32 manufactured by
`Interdata, Inc. As will be described in more detail here-
`the machine tool to be controlled and to selectively
`operate the output devices thereon to provide the de-
`inafter, it is coupled to the cable 501 by a UAR/T 502
`which connects to an I/O port on a computer processor
`sired manner ofoperation.
`Mounted to the door of the cabinet 1 immediately
`550. The processor 550 is coupled to a read/write mem-
`ory 551 through a bus 552 and a bulk storage device 507
`above the keyboard 7 is an associated cathode ray tube
`(CRT) display 9. Mounted to the right of the keyboard
`in the form of a disc couples to the memory 551 andit
`serves to store not only a large number ofpart pro-
`7 and CRTdisplay 9 is a main control panel 10 which
`includes a variety of pushbuttons and selector switches
`grams, but also, a variety of numerical control system
`software packages which may be downloaded to the
`for providing standard operator controls such as mode
`numerical control system 1. Programs stored in the host
`selection, feedrate override, spindle speed override, jog
`select, axis select, etc. One of the pushbuttons enables
`computer memory 551 enable the computer to commu-
`nicate with the numerical control system 1 and to man-
`the keyboard 7 to enter data.
`Referring particularly to FIGS.2 and 3, the elements
`age the library of programs stored in the bulk storage
`507.
`of the numerical control system are mounted within the
`As will be described in more detail hereinafter, an
`cabinet 1 to allow easy access for inspection, testing and
`maintenance. The keyboard 7 is mounted to the cabinet
`operator at the numerical control system 1 can call up a
`particular part program ora particular numerical con-
`door11 along with the tape reader 5, CRT display 9 and
`trol software system by generating commands through
`main control panel 10. A secondary control panel 12
`the keyboard 7. Referring particularly to FIG. 3, a
`mounts immediately above the tape reader 5 andall of
`communications package stored in a numerical control
`these system I/O devices are connected to a numerical
`system memory 34 couples these commands to the host
`control processor 13 which is housed at the bottom of
`the cabinet 1. More specifically, the tape reader 5 con-
`computer 500, which in turn reads the selected part
`program or numerical control system software package
`nects through a cable 14, the secondary control panel 12
`out of the bulk storage 507 and downloads it to the
`connects through a cable 15, the keyboard 7 connects
`numerical contro] system 1. The downloaded program
`through a cable 25, the CRT display 9 connects through
`is stored in the memory 34 at a location determined by
`a cable 17, and the main control panel 10 connects
`the communications package. To better understand the
`through a cable 18 to a wire harness 19 which leads to
`nature of a numerical control software system package
`the processor 13. A processor front panel 26 provides a
`number of manually operable pushbuttons and visual
`which can be downloaded from the bulk storage 507 to
`the memory 34, a description of a preferred numerical
`indicators whichrelate to the operation of the processor
`13 and which are connected thereto through a bus 27.
`control system — both hardware and software — will
`now be made. This preferred numerical control system
`Twoinput/output (I/O)interface racks 20 and 21 are
`is sold commercially by the Allen-Bradley Company as
`mounted in the cabinet 1 above the processor 13 and are
`the Model 7300 B and it is described in detail in U.S.
`connected thereto by a wiring harness 22 which extends
`Pat. No. 4,038,533.
`upward alongtheir left-hand side. A main power supply
`23 mounts above the I/O interface rack 21 and a mem-
`Referring particularly to FIGS.4a and 4, the numer-
`ory powersupply 24 mounts ontheleft side wall of the
`ical control processor 13 is organized arounda sixteen-
`cabinet1.
`bit bidirectional processor data bus 30. Data is moved
`from one element of the processor to another through
`The I/Ointerface racks 20 and 21 mounta variety of
`this data bus 30 in response to the execution of a micro-
`input circuits and output circuits on closely spaced,
`instruction which is held in a 24-bit micro-instruction
`vertically disposed printed circuit boards (not shownin
`register 31. Each such micro-instruction indicates the
`the drawings). These input and outputcircuits serve to
`source of the data to be applied to the data bus 0, the
`couple the industrial control processor 13 with the
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`destination of the data, and any operations that are to be
`performed on that data. The micro-instructions are
`stored in a micro-program read-only memory 32, and
`oneis read out every 200 nano-seconds through a bus 33
`to the micro-instruction register 31. The read-only
`memory 32 stores a large numberofseparately address-
`able, or selectable, micro-routines, each of which is
`comprised of a set of micro-instructions. To enable the
`processor 13 to perform a desired function, the appro-
`priate micro-routine is stored in the read-only memory
`32 and it is selected for execution by a 16-bit macro-
`instruction which is stored in a read/write main mem-
`ory 34.
`The main memory 34 is comprised of 4K by 1 dy-
`namic MOS RAMswhichare organized to store up to
`32,000 16-bit words. Macro-instructions and data are
`read out of and written into the main memory 34
`through a 16-bit memory data register 35 which con-
`nects to the processor data bus 30. The memory words
`are selected, or addressed, through a 15-bit memory
`address register 36 which also connects to the processor
`data bus 30. To write into the main memory 34, an
`addressis first loaded into the memory address register
`36 by applying a logic high voltage to its clock lead 29.
`The data to be loaded appears on the processor data bus
`30 and is gated through the memory data register by
`applying a logic high voltageto its data in clock lead 27.
`A logic high voltage is then applied to a read/write
`controlline 34’ on the memory 34 to complete the load-
`ing operation. Data or a macro-instruction is read out of
`an addressed line of the main memory 34 when a
`READ micro-instruction is executed. A logic low volt-
`age is applied to the read/write control line 34’ and a
`logic high voltage is applied to a data out enable line 28
`on the memorydata register 35. The data word is mo-
`mentarily stored in the register 35 and is subsequently
`transferred through the processor data bus 30 to the
`desired destination.
`In response to the execution of a micro-routine called
`FETCH,which includes the READ micro-instruction,
`a macro-instruction is read from the main memory 34
`and coupled to a 16-bit macro-instruction register 37
`through the data bus 30. The macro-instruction is stored
`in the register 37 by a logic high voltage which is ap-
`plied to a macro-instruction register clock line 37’. Cer-
`tain of the macro-instructions include operation codes
`which are coupled through an instruction register bus
`39 to a macro-decodercircuit 38, and other instructions
`also include a bit pointer code which is coupled through
`the same instruction register bus 39 to a bit pointer
`circuit 40. The bit pointer circuit 40 is a binary decoder
`having four inputs connected to the least significant
`digit outputs of the macro-instruction register 37 and
`having a set of 16 outputs connected to respective leads
`in the processor data bus 30. In response to the execu-
`tion of a selected micro-instruction (MASK), a logic
`high voltage is applied to a terminal 41, and the bit
`pointer circuit 40 drives a selected one of the sixteen
`leads in the processor data bus 30 to a logic low voltage.
`The bit pointer circuit 40 facilitates the execution of
`certain programmable controller type macro-instruc-
`tions.
`In response to an operation code in a macro-instruc-
`tion stored in the register 37, one of the micro-routines
`in the read-only memory 32is selected. The operation
`code is applied to the macro-decodercircuit 38 which
`enables one of four mapper proms 42-45 and addresses
`a selected line in the enabled mapper prom. Eachline of
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`the mapper proms 42-45 stores a twelve-bit micro-rou-
`tine starting address, which when read out, is coupled
`through a micro-program address bus 46 to preset a
`twelve-bit micro-program sequencer 47. The sequencer
`47 is a presettable counter which includes a load termi-
`nal 52, an increment terminal 53 and a clock terminal 54.
`The clock terminal 54 is driven by a five-megahertz
`clock signal which is generated by a processor clock
`circuit 85 that is coupled to the sequencer 47 through an
`AND gate 86. Each time a logic high clock pulse is
`applied to the terminal 54 on the micro-program se-
`quencer 47, it is either preset to an address which ap-
`pears on the bus 46 orit is incremented one count. Con-
`currently, the micro-instruction register 31 is clocked
`through a line 88 and AND gate 88' to read and store
`the micro-instruction which is addressed by the micro-
`program sequencer 47. The AND gates 86 and 88 can
`be disabled in response to selected codes in a micro-
`instruction to decouple the 5 mHz clock. Such decou-
`pling of the clock 85 from the sequencer 47 occurs, for
`example, during input and output operations to allow
`data one micro-second to propagate.
`Each micro-second which is read out of the read-only
`memory 32 to the micro-instruction register 31 is cou-
`pled through a micro-instruction bus 31a to a micro-
`instruction decoder circuit 48 which is also coupled to
`the clock line 88. The micro-instructions are decoded
`and executed before the next clock pulse is applied to
`the terminal 54 on the micro-program sequencer 47.
`Each micro-instruction is comprised of a plurality of
`separate codes called micro-orders which are each sepa-
`rately decoded to enable one of the processor elements.
`Each micro-routine stored in the micro-program
`read-only memory 32 is terminated with a special mi-
`cro-instruction which includes a code, or micro-order,
`identified hereinafter by the mnemonic EOX or EOXS.
`When coupled to the micro-instruction decodercircuit
`48, this code causes a logic high voltage to be generated
`on an EOXline 49 to a priority mapper prom 50.If the
`industrial control processor 13 is in the RUN mode, the
`starting address of the FETCH micro-routine is read
`from the priority mapper prom 50 and is applied to the
`micro-sequencer 47 through the bus 46. The micro-
`instruction decoder circuit 48 also generates a logic
`high voltage on a preset line 51 which connects to the
`load terminal 52 on the micro-program sequencer 47 to
`preset the sequencer 47 to the starting address of the
`FETCH micro-routine.
`As indicated above, the FETCH micro-routine func-
`tions to read the next macro-instruction to be executed
`from the main memory 34, couple it to the macro-
`instruction register 37, and initiate the execution of that
`macro-instruction. The last micro-instruction in the
`FETCH micro-routine includes a code which is identi-
`fied hereinafter by the mnemonic MAP. This micro-
`instruction code causes the micro-instruction decoder
`circuit 48 to generate a logic high voltage to the macro-
`decoder circuit 38 through a MAP line 52 and to
`thereby initiate decoding of
`the macro-instruction
`which is stored in the macro-instruction register 37. A
`logic high voltageis also generated on the preset line 51
`to load the micro-program sequencer 47 with thestart-
`ing address of the micro-routine called for by the de-
`coded macro-instruction.
`As shown in FIG. 4%, mathematical and logical oper-
`ations are performed bythe industrial control processor
`13 in an arithmetic and logic processor 55 which con-
`nects to the processor data bus 30 and to the micro-
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`instruction decodercircuit 48 through a bus 56. Refer-
`register 68 connectto the “B” inputs on the multiplexer
`ring particularly to FIG. 5, the arithmetic and logic
`72. Sixteen outputs on the multiplexer 72 connectto the
`processor 55 includes a 16-bit “L” register 57 which has
`leads in the processor data bus 30, and whenalogic
`inputs that connectto the leads in the processor data bus
`high voltage is applied to an enable lead 73 thereon, the
`30 and a corresponding set of outputs which connect
`contents ofeither the A register 67 or the B register 68
`through a bus 58 to the “B”inputs of a 16-bit arithmetic
`are coupled to the processor data bus 30. Theselection
`and logic unit (ALU) 59. Data on the bus 30 is clocked
`is made througha select lead 74 which, along with the
`enable lead 73, connect to the micro-instruction de-
`into the L register 57 whena logic high is applied to a
`lead 60 and the L register 57 is cleared when a logic
`codercircuit 48. In response to the execution ofselected
`high is applied to a lead 61. The leads 60 and 61 connect
`micro-instructions, therefore, the A register 67 or the B
`to the micro-instruction decodercircuit 48 through the
`register 68 may provide the source of data to the pro-
`bus 56 and are thus controlled by selected micro-
`cessor data bus 30 through the multiplexer 72, or they
`instructions.
`may be designated by selected micro-instructions as the
`The ALU 59 is comprised of four commercially
`destination of data on the processor bus 30