throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Bendik, et al.
`In re Patent of:
`U.S. Patent No.: 5,591,678
`Issue Date:
`January 7, 1997
`Appl. Serial No.: 482,172
`Filing Date:
`June 7, 1995
`Title:
`PROCESS OF MANUFACTURING A MICROELECTRIC
`DEVICE USING A REMOVABLE SUPPORT SUBSTRATE
`AND ETCH-STOP
`
`
`
`
`DECLARATION OF LEONARD W. SCHAPER
`
`I, Leonard W. Schaper, of Naples, Florida, declare that:
`
`1.
`
`I have been retained by counsel for Petitioner Samsung Electronics,
`
`Co., Ltd., Samsung Electronics America, Inc., and Samsung Semiconductor, Inc.
`
`(collectively, “Samsung” or “Petitioner”) to provide my independent analysis of
`
`the issues raised in the Petition for inter partes review of U.S. Patent No.
`
`5,591,678 (“the ʼ678 Patent”).
`
`2.
`
`I am not currently and have not at any time in the past been an
`
`employee of Samsung Electronics, Co., Ltd., Samsung Electronics America, Inc.,
`
`or Samsung Semiconductor, Inc.
`
`3.
`
`I am being compensated for my time expended in connection with this
`
`matter at the rate of $500.00 per hour, plus reimbursement of any expenses I incur.
`
`I have no financial stake in this matter, and my compensation is not contingent
`
`upon the outcome of this inter partes review of the ʼ678 Patent.
`
`1
`
`Petitioner Samsung - SAM1004
`
`

`
`I.
`
`QUALIFICATIONS AND PROFESSIONAL EXPERIENCE
`4.
`
`I am an expert in the fields of semiconductor design, semiconductor
`
`fabrication, electronic packaging, and interconnect, among other fields.
`
`5.
`
`I have 36 years of experience in the field of electronic packaging,
`
`including 12 years at AT&T Bell Laboratories from 1978-1990, where I was co-
`
`inventor of the silicon substrate multichip module technology known as Advanced
`
`VLSI Packaging (“AVP”). During the 1980s I served in various technology
`
`planning functions that required me to have extensive knowledge of the electronic
`
`packaging and interconnect fields.
`
`6.
`
`I am Professor Emeritus of Electrical Engineering at the University of
`
`Arkansas where I also served as Director of the High Density Electronics Center.
`
`In that capacity, I have been responsible for over $30 million in research grants and
`
`contracts
`
`covering many
`
`aspects of
`
`electronic packaging,
`
`including
`
`thermomechanical reliability of chip packaging.
`
`7.
`
`I have taught graduate courses in electronic packaging, and I am a
`
`chapter author in Advanced Packaging with Emphasis on Multichip Modules
`
`(William D. Brown ed., Wiley-IEEE Press 1999), and Advanced Packaging, R.K.
`
`Ulrich and W.D. Brown, Eds., Wiley-IEEE Press, 2006.
`
`8.
`
`I am a Fellow of the Institute of Electrical and Electronic Engineers
`
`(“IEEE”). I am the winner of the IEEE-CPMT (“Components, Packaging, and
`
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`

`
`Manufacturing Technology”) Society
`
`“Outstanding Sustained Technical
`
`Contributions” Award, as well as an ECTC (“Electronic Components and
`
`Technology Conference”) Outstanding Paper Award.
`
`9.
`
`I am a Fellow and Life Member of the International Microelectronics
`
`and Packaging Society (“IMAPS”), and a past president of the International
`
`Electronics Packaging Society (“IEPS”), one of the societies that merged to form
`
`IMAPS. I am the 2002 winner of the IMAPS William D. Ashman Memorial
`
`Award “for outstanding contributions to the field of electronic packaging,
`
`particularly advanced in broad, module, and chip package power distribution and
`
`decoupling capacitor design, leading to higher performance system designs.”
`
`10.
`
`I am an inventor of co-inventor of 21 U.S. patents and several foreign
`
`patents, all in the field of electronic packaging or optical communications.
`
`11. Additional details regarding my qualifications and a listing of my
`
`publications are provided in my curriculum vitae, which is attached as Exhibit
`
`SAM1015 to this Petition. (“Schaper Curriculum Vitae”).
`
`II. MATERIALS CONSIDERED
`12.
`In writing this Declaration I have considered the following: my own
`
`knowledge and experience, including my work experience in the field of
`
`semiconductor design and fabrication, my industry experience in semiconductor
`
`3
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`

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`design and fabrication, and my experience in working with others involved in the
`
`field. In addition, I have analyzed the following publications and materials:
`
` U.S. Patent No. 5,591,678 and its accompanying prosecution file history
`
`(Ex. SAM1001 and Ex. SAM1011);
`
` U.S. Patent No. 5,347,154 (“Takahashi”) (Ex. SAM1005);
`
` U.S. Patent No. 4,599,792 (“Cade”) (Ex. SAM1006);
`
` U.S. Patent No. 5,002,818 (“Licari”) (Ex. SAM1008);
`
` U.S. Patent No. 4,601,779 (“Abernathey”) (Ex.SAM1007);
`
` U.S. Patent No. 4,975,126 (“Margail”) (Ex.SAM1014);
`
` R.B. Soper (Mechanical Damage – Its Role in Silicon Surface Preparation,
`
`Silicon Device Processing, Vol. 13 (Nov. 1970) (“Soper”) (Ex. SAM1009);
`
` Kurt E. Petersen (Silicon as a Mechanical Material, Proceedings of the
`
`IEEE, Vol. 70, No. 5 (May 1982) (“Petersen”) (Ex. SAM1010);
`
` H. Seidel, Anisotropic Etching of Crystalline Silicon in Alkaline Solutions -
`
`I. Orientation Dependence and Behavior of Passivation Layers, J.
`
`Electrochem. Soc., Vol. 137, No. 11 (1990) (“Seidel”) (Ex. SAM1012); and
`
` Ruzyllo, Semiconductor Glossary, (2004) (“Ruzyllo”) (Ex. SAM1013).
`
`13. Although for the sake of brevity this Declaration refers to selected
`
`portions of the cited references, it should be understood that one of ordinary skill in
`
`the art would view the references cited herein in their entirety, and in combination
`
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`

`
`with other references cited herein or cited within the references themselves. The
`
`references used in this Declaration, therefore, should be viewed as being
`
`incorporated herein in their entirety.
`
`III. PERSON OF ORDINARY SKILL IN THE ART
`14.
`I am familiar with the content of the ʼ678 Patent, which, I have been
`
`informed by counsel, has an earliest possible filing date of January 19, 1993
`
`(hereinafter “the Priority Date”).
`
`15. Additionally, I have reviewed the other references cited above in this
`
`Declaration. Counsel has informed me that I should consider these materials
`
`through the lens of one of ordinary skill in the art related to the ’678 Patent at the
`
`time of the invention. I believe one of ordinary skill around January 19, 1993
`
`would have had either a (i) Bachelor of Science in Electrical Engineering with 5
`
`years of experience in semiconductor design and manufacture, (ii) or a masters or
`
`Ph.D. degree
`
`in Electrical Engineering with equivalent experience
`
`in
`
`semiconductor design and manufacture.
`
`A. Grounds for Invalidating Patent Claims in an Inter Partes
`Review: 35 U.S.C. § 102 and/or 35 U.S.C. § 103
`
`16.
`
`I understand that the following restriction—which is set forth in 35
`
`U.S.C. § 311(b)—limits an IPR petition to anticipation and obviousness grounds,
`
`using only prior art consisting of patents or printed publications. In other words,
`
`an IPR petitioner can only discuss whether another published prior art reference
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`5
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`anticipates under 35 U.S.C. § 102 or renders the challenged patent claims obvious
`
`under 35 U.S.C. § 103.
`
`17.
`
`I understand that an IPR petitioner is prohibited from challenging a
`
`patent on other grounds such as the on-sale bar, non-patentable subject matter, or
`
`invalidity under 35 U.S.C. § 112 for unsupported claims or indefiniteness.
`
`B. Anticipation
`18.
`I understand that the following standards—which are taken from 35
`
`U.S.C. § 102—govern the determination of whether a claim in a patent is invalid as
`
`“anticipated.”
`
`19.
`
`In general, a patent claim is invalid as “anticipated” if each and every
`
`feature of the claim is found, expressly or inherently, in a single item of prior art.
`
`In determining whether the single item of prior art anticipates the claim, one
`
`considers not only what is expressly disclosed in the particular item of prior art, but
`
`also what is inherently present or disclosed in that prior art or what inherently
`
`results from its practice. Claim limitations that are not expressly found in a prior
`
`art reference are inherent if the prior art necessarily functions in accordance with,
`
`or includes, the claim limitations, or if the missing element or feature would be the
`
`natural result of following what the prior art teaches to persons of ordinary skill in
`
`the art. It is acceptable to examine evidence outside the prior art reference
`
`(extrinsic evidence), including experimental testing, in determining whether a
`
`6
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`

`
`feature, while not expressly discussed in the reference, is necessarily present in it.
`
`Mere probabilities are not enough, but it is not required that persons of ordinary
`
`skill actually recognized the inherent disclosure at the time the prior art was first
`
`known or used.
`
`20.
`
`I understand that there are a number of different ways that anticipation
`
`can occur. First, if the claimed invention was “known or used by others” in this
`
`country before the asserted date of invention, then the claim is anticipated. A
`
`demonstration or oral presentation could suffice; printed publications are not
`
`required. Second, if the claimed invention was “in public use” in this country more
`
`than one year prior to the date of the application for the patent in the United States,
`
`then the claim is anticipated. Public knowledge of the invention or an enabling
`
`disclosure is not required; only public use is required. Third, if the claimed
`
`invention was “described in a printed publication” anywhere in the world prior to
`
`the alleged invention or more than one year prior to the date of the application for
`
`the patent in the United States, then the claim is anticipated. To anticipate,
`
`however, the printed publication must also enable one skilled in the art to make
`
`and use the claimed invention. Fourth, if the claimed invention was made in this
`
`country by another inventor before the asserted date of invention, and not
`
`abandoned, suppressed, or concealed, then the claim is anticipated. It is normally
`
`the first inventor to conceive, rather than the first to reduce to practice, who is
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`7
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`

`
`entitled to priority, assuming that the first to conceive was reasonably diligent in
`
`reducing the invention to practice from a time prior to conception by the other.
`
`C. Obviousness
`21.
`I understand that the following standards govern the determination of
`
`whether a claim in a patent is obvious: Under 35 U.S.C. § 103, a claim in a patent
`
`is obvious when the differences between the subject matter sought to be patented
`
`and the prior art are such that the subject matter as a whole would have been
`
`obvious at the time the invention was made to a person having ordinary skill in the
`
`art to which said subject matter pertains.
`
`22. The relevant inquiry requires consideration of four factors (although
`
`not necessarily in the following order):
`
` The scope and content of the prior art,
`
` The differences between the prior art and the claims at issue,
`
` The level of ordinary skill in the pertinent art at the time of the invention,
`
`and
`
` Objective factors indicating obviousness or non-obviousness.
`
`23. A prior art reference may be considered if it discloses information
`
`designed to solve any problem or need addressed by the patent or if the reference
`
`discloses information that has obvious uses beyond its main purpose that a person
`
`having ordinary skill in the art would reasonably examine to solve any problem or
`
`8
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`need addressed by the patent. The combination of familiar elements according to
`
`known methods is likely to be obvious when it does no more than yield predictable
`
`results.
`
`24. When a work is available in one field of endeavor, design incentives
`
`and other market forces can prompt variations of it, either in the same field or a
`
`different one. If a person of ordinary skill can implement a predictable variation,
`
`§103 likely bars its patentability. For the same reason, if a technique has been used
`
`to improve one device, and a person of ordinary skill in the art would recognize
`
`that it would improve similar devices in the same way, using the technique is
`
`obvious unless its actual application is beyond his or her skill.
`
`25. The obviousness analysis need not seek out precise teachings directed
`
`to the specific subject matter of the challenged claim, for a court can take account
`
`of the inferences and creative steps that a person of ordinary skill in the art would
`
`employ at the time of the invention. Indeed, often, it will be necessary to look to
`
`interrelated teachings of multiple patents; the effects of demands known to the
`
`design community or present in the marketplace; and the background knowledge
`
`possessed by a person having ordinary skill in the art, all in order to determine
`
`whether there was an apparent reason to combine the known elements in the
`
`fashion claimed by the patent at issue. Importantly, the question is not whether the
`
`combination was obvious to the patentee but whether the combination was obvious
`
`9
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`

`
`to a person with ordinary skill in the art. Under the correct analysis, any need or
`
`problem known in the field of endeavor at the time of invention and addressed by
`
`the patent can provide a reason for combining the elements in the manner claimed.
`
`26. The obviousness analysis cannot be confined by a formalistic
`
`conception of
`
`the words “teaching, suggestion, and motivation,” or by
`
`overemphasis on the importance of published articles and the explicit content of
`
`issued patents.
`
`27.
`
`In determining whether the subject matter of a patent claim is obvious,
`
`neither the particular motivation nor the avowed purpose of the patentee controls.
`
`What matters is the objective reach of the claim. If the claim extends to what is
`
`obvious, it is invalid. One of the ways in which a patent's subject matter can be
`
`proved obvious is by noting that there existed at the time of invention a known
`
`problem for which there was an obvious solution encompassed by the patent's
`
`claims.
`
`28. A person of ordinary skill attempting to solve a problem will not be
`
`led only to those elements of prior art designed to solve the same problem.
`
`Common sense teaches that familiar items may have obvious uses beyond their
`
`primary purposes, and in many cases a person of ordinary skill will be able to fit
`
`the teachings of multiple patents together like pieces of a puzzle. A person of
`
`ordinary skill is also a person of ordinary creativity, not an automaton.
`
`10
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`29. When there is a design need or market pressure to solve a problem
`
`and there are a finite number of identified, predictable solutions, a person of
`
`ordinary skill has good reason to pursue the known options within his or her
`
`technical grasp. If this leads to the anticipated success, it is likely the product not
`
`of innovation but of ordinary skill and common sense. In that instance the fact that
`
`a combination was obvious to try might show that it was obvious.
`
`30. One should be aware of the potential for distortion caused by
`
`hindsight bias and must be cautious of arguments reliant upon ex post reasoning.
`
`IV. OVERVIEW OF THE ʼ678 PATENT
`31. The ’678 Patent
`is directed
`
`to manufacturing
`
`techniques for
`
`semiconductor devices. Specifically, it describes a manufacturing technique that
`
`stacks two-dimensional microelectronic circuits in a third dimension. ʼ678
`
`Patent,1:66-2:2.
`
`32. The ʼ678 Patent proposes manufacturing circuit elements on a first
`
`substrate with a three-layer structure, which purportedly allows circuit elements to
`
`be transferred from the first substrate to a second substrate to achieve three-
`
`dimensional stacking. ʼ678 Patent, 2:59-3:5, 2:5-10.
`
`33.
`
`Importantly,
`
`the
`
`three-dimensional microelectronic devices are
`
`prepared using well-established, inexpensive processing techniques for two-
`
`11
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`
`dimensional circuits. ʼ678 Patent, 2:5-10. The ʼ678 Patent proposes a
`
`manufacturing process as illustrated in FIG. 1 (annotated):
`
`
`
`34. The first step in the process, labeled 20, furnishes a three-layer
`
`substrate 40, which includes an etchable layer 42 (blue), an etch-stop layer 44
`
`(green) and a wafer layer 46 (yellow).
`
`35. The second step, labeled 22, forms a microelectronic circuit element
`
`50 (purple) in the wafer layer 46. As shown, the microelectronic circuit element 50
`
`12
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`

`
`is formed in the exposed side of the wafer layer 46, the surface that faces away
`
`from the etch-stop layer 44. ʼ678 Patent, 4:37-52. The microelectronic circuit
`
`element 50 may be of any type and may include many layers of metals,
`
`semiconductors, insulators and the like; it may include active devices or passive
`
`structure. Id.
`
`36. The third step, labeled 24, attaches a second substrate 58 (orange) to
`
`the microelectronic circuit element 50 and the first substrate 40. The second
`
`substrate 58 covers the exposed surface of the wafer layer 46 and the circuit
`
`element 50. The second substrate 58 can be attached in any manner so long as it
`
`does not damage the pre-existing circuit element 50. ʼ678 Patent, 5:30-33.
`
`Optionally, the second substrate 58 may include its own circuit elements, and
`
`electrical connections may be created between the microelectronic circuit elements
`
`of the first substrate 40 and second substrate 58 when the second substrate 58 is
`
`attached to the first substrate 40. ʼ678 Patent, 3:6-12.
`
`37. Once the circuit element 50 is supported by the second substrate 58,
`
`the etchable layer 42 of the first substrate 40 may be removed, as shown in step 26
`
`(the fourth step in the process). ʼ678 Patent, 3:12-14. The etchable layer 42 is
`
`etched away down to the etch-stop layer 44, thereby exposing the etch-stop layer
`
`44. ʼ678 Patent, 6:4-5. An etchant is chosen that attacks the etch-stop layer 44 at a
`
`much lower rate than the etchable layer 42, thereby stopping the etching process.
`
`13
`
`

`
`ʼ678 Patent, 3:15-18. In other words, when the etchant is applied to the etchable
`
`layer, the etchable layer etches away quickly. When applied to the etch-stop layer,
`
`the etch-stop layer barely etches away, if at all.
`
`38.
`
`In step 28, backside electrical connections 56’ (red) may be formed
`
`through the etch-stop layer 44. ʼ678 Patent, 6:10-14. To form backside electrical
`
`connections 56’, the etch-stop layer 44 is then patterned and material is removed
`
`from these locations of the etch-stop layer 44 by any appropriate method. ʼ678
`
`Patent, 6:14-19. The backside electrical connections 56’ connect to the wafer layer
`
`46 from a different side than the exposed side in which the microelectronic circuit
`
`element 50 was formed, in step 22. ʼ678 Patent, 6:10-43. In step 30, the device is
`
`completed.
`
`V. TAKAHASHI (“ʼ154 PATENT”)
`39.
`I have been asked by counsel for Petitioner to review the Challenged
`
`Claims of the ʼ678 Patent in view of Takahashi. I have performed that analysis and
`
`it is my opinion that Takahashi anticipates claims 1-8, 11-16, and 18 of the ʼ678
`
`Patent.
`
`A. Overview of Takahashi
`40. Like the ʼ678 Patent, Takahashi discloses a method of fabricating a
`
`microelectronic device.
`
`14
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`

`
`41. Takahashi discloses “a semiconductor substrate having a structure
`
`composed of a thin film laminated layer intensively formed with transistor
`
`elements and a light valve device having said semiconductor substrate, a liquid
`
`crystal layer and an opposed substrate integrated with one another.” ʼ154 Patent,
`
`1:9-14.
`
`42. Annotated Figures 11-14 of Takahashi below illustrates the basic
`
`manufacturing steps of Takahashi’s semiconductor device. Annotated Figure 1 of
`
`Takahashi below shows the completed semiconductor device.
`
`
`
`43. Takahashi discloses a three-layer SOI (silicon on substrate) substrate
`
`(81) having a substrate (82) shown in blue, an insulating film (3) shown in green
`
`overlying the substrate (82), and a thin film (4) shown in light blue overlying the
`
`insulating film (3). ʼ154 Patent, 5:46-56, 14:7-13.
`
`15
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`

`
`44. The vertical lines through the thin film (4) are drawn such that it may
`
`appear that thin film (4) in Figures 12-13 is no longer continuous through the
`
`structure as shown in Figure 11.
`
`45. A person of skill in the art would have readily understood the thin
`
`film (4) as being continuous across the structure as drawn in Figure 11. Thus, the
`
`figures of Takahashi have been annotated to show that the thin film (4) (colored in
`
`light blue) is continuous across the structure, overlying the etch-stop layer.
`
`46. Takahashi also discloses a support substrate (15) shown in orange.
`
`ʼ154 Patent, 16:13-33. And Takahashi discloses a channel forming region (5),
`
`source and drain regions (6), (7), gate electrode (9), and source and drain
`
`electrodes (11) and (12). ʼ154 Patent, 5:56-6:6. Gate electrode (9), and drain
`
`electrodes (11) and (12) are shown in purple.
`
`Claim 1
`
`47.
`
`It is my opinion that Takahashi anticipates claim 1 of the ʼ678 Patent.
`
`[1.0] “A method of fabricating a microelectronic device, comprising the steps
`of:”
`
`
`48. Takahashi discloses a method of fabricating a microelectronic device
`
`in the form of a semiconductor device with a substrate. For example, Takahashi
`
`discloses a process for manufacturing “a semiconductor substrate having a
`
`structure composed of a thin film laminated layer intensively formed with
`
`transistor elements….” ʼ154 Patent, 1:9-11.
`
`16
`
`

`
`[1.1] “furnishing a first substrate having an etchable layer, an etch stop layer
`overlying the etchable layer, and a wafer overlying the etch-stop layer;”1
`
`
`49. Takahashi discloses furnishing a first substrate (SOI substrate (81))
`
`having an etchable layer (substrate 82)), an etch-stop layer overlying the etchable
`
`layer (insulating film (3)), and a wafer overlying the etch-stop layer (thin film (4)).
`
`50. Takahashi particularly discloses that “an SOI substrate 81 is prepared
`
`at first.” ʼ154 Patent, 14:9-10. Then, below the insulating film (3), “there is
`
`arranged a single crystal semiconductor Thin[sic] film 4.” ʼ154 Patent, 5:54-55.
`
`51. Takahashi further discloses that “[f]or forming the insulating film, a
`
`silicon nitride film may be deposited at first as a surfacing treatment on the
`
`
`1 Claims 1-5 and 10-17 of the ʼ678 Patent recite “etch-stop layer” while claims 1,
`
`5, 10-13, and 17 of the ʼ678 Patent recite “etchable layer.” In performing my
`
`analysis herein, I have used the following constructions for “etch-stop layer”: a
`
`layer of the first substrate, distinct from the etchable layer and the wafer, which
`
`stops the etching process by virtue of having a lower etch rate than the etchable
`
`layer” and “etchable layer”: “a layer of the first substrate, distinct from the etch-
`
`stop layer and the wafer, having an etch rate much higher than that for the etch-
`
`stop
`
`layer.” In my opinion,
`
`these constructions are consistent with the
`
`understanding of these terms to a person of skill in the art in view of the
`
`specification of the ʼ678 Patent.
`
`17
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`

`
`tentative silicon substrate, and then the silicon dioxide layer may be deposited by
`
`the CVD.” ʼ154 Patent, 7:35-38.Takahashi also discloses that the silicon nitride
`
`layer acts as an etching stopper. ʼ154 Patent, 7:42-43 (“The silicon nitride layer
`
`thus deposited as the surfacing treatment performs as an etching stopper at a later
`
`step.”).
`
`52. Takahashi also discloses that etchable layer 82 is etched away: “This
`
`removal is carried out by etching the tentative substrate 82 of silicon, for example.”
`
`ʼ154 Patent, 16:37-38. Figure 11 of Takahashi illustrates this configuration:
`
`53. Thus, it is my opinion that Takahashi discloses the claim limitations
`
`
`
`recited in [1.1].
`
`[1.2] “forming a microelectronic circuit element in the exposed side of the
`wafer of the first substrate opposite to the side overlying the etch-stop layer;”
`
`
`54. Takahashi discloses forming a microelectronic circuit element in the
`
`exposed side of the wafer of the first substrate opposite to the side overlying the
`
`etch-stop layer.
`
`18
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`

`
`55. Takahashi discloses that the “single crystal semiconductor thin film 4
`
`is formed not only with channel forming region 5 for each transistor element but
`
`also with a source region 6 and a drain region 7 which merge into the channel
`
`forming region 5. Below the single crystal semiconductor thin film, there is
`
`arranged through a gate oxide layer 8 an intermediate electrode film which forms a
`
`gate electrode 9 of the transistor element.” ʼ154 Patent, 5:56-63.
`
`56. Takahashi further discloses a back layer film 10 that is formed with
`
`contact holes that extend to the source region 6 and drain region 7 “so that a source
`
`electrode 11 and a drain electrode 12 are arranged therethrough.” ʼ154 Patent,
`
`5:65-68.
`
`57. Figure 12 of Takahashi illustrates the microelectronic circuit element
`
`in the exposed side of the wafer (13, which is thermally oxidized film 4 described
`
`above) of the first substrate opposite to the side overlying the etch-stop layer:
`
`19
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`

`
`58. Thus, it is my opinion that Takahashi discloses the claim limitations
`
`
`
`recited in [1.2].
`
`[1.3] “attaching the wafer of the first substrate to a second substrate; and”
`
`59. Takahashi discloses attaching the wafer of the first substrate to a
`
`second substrate.
`
`60. Takahashi discloses that “the support substrate 15 is adhered to the
`
`surface of the applied adhesive film 14.” ʼ154 Patent, 16:13-15. Takahashi further
`
`discloses that “[b]y heat treatment in this state, the solvent contained in the
`
`adhesive film 14 is evaporated away, and the fusion of the silicon dioxide particle
`
`advances until the support substrate 15 and the SOI substrate 81 are rigidly adhered
`
`to each other in face-to-face relation.” ʼ154 Patent, 16:18-23.
`
`61. Figure 14 of Takahashi illustrates this configuration:
`
`20
`
`

`
`62. Thus, it is my opinion that Takahashi discloses the claim limitations
`
`
`
`recited in [1.3].
`
`[1.4] “etching away the etchable layer of the first substrate down to the etch-
`stop layer.”
`
`
`63. Takahashi discloses etching away the etchable layer of the first
`
`substrate down to the etch-stop layer.
`
`64. Takahashi discloses that “[f]or forming the insulating film, a silicon
`
`nitride film may be deposited at first as a surfacing treatment on the tentative
`
`silicon substrate, and then the silicon dioxide layer may be deposited by the CVD.”
`
`ʼ154 Patent, 7:35-38.
`
`65. Takahashi further discloses that “[t]he silicon nitride layer thus
`
`deposited as the surfacing treatment performs as an etching stopper at a later step.
`
`At the aforementioned fourth step, the tentative substrate can be etched off by
`
`using the silicon nitride layer as the etching stopper. As a result, a flat insulating
`
`21
`
`

`
`film is exposed to the outside.” ʼ154 Patent, 7:42-47; see also id. at 16:43-47
`
`(“Specifically, due to the difference in the etching rate between the silicon and the
`
`silicon nitride, the etching removal of the tentative substrate 82 of silicon
`
`substantially ends at the step reaching the silicon nitride film.”).
`
`66. Takahashi also discloses that “[t]his removal is carried out by etching
`
`the tentative substrate 82 of silicon, for example.” ʼ154 Patent, 16:37-38. Figure 1
`
`of Takahashi shows the tentative substrate 82 (etchable layer) having been etched
`
`away down to the etch-stop layer:
`
`67. Thus, it is my opinion that Takahashi discloses the limitations recited
`
`
`
`in [1.4].
`
`68.
`
`See claim chart A in Exhibit SAM1016.
`
`Claim 2
`
`69.
`
`It is my opinion that Takahashi anticipates claim 2 of the ʼ678 Patent.
`
`
`
`22
`
`

`
`[2.0] “The method of claim 1, further including an additional step, after the
`step of etching, of patterning the etch-stop layer.”
`
`
`70. Takahashi also discloses the additional step after the step of etching,
`
`the step of patterning the etch-stop layer.
`
`71. The ʼ678 Patent explains that “the etch-stop layer 44 is patterned by
`
`well-known patterning techniques to precisely identify the location to be
`
`penetrated. Material is removed from these locations of the etch-stop layer 44 by
`
`any appropriate method.” ʼ678 Patent, 6:15-19. In other words, “patterning” as
`
`described in the ʼ678 Patent is not limited to a particular technique or location on
`
`the device. Takahashi discloses the patterning step of claim 2.
`
`72. For example, Takahashi discloses that “[t]he thin film laminated layer
`
`1 is partially formed with a through hole 16. This through hole 16 can be formed
`
`by etching the field insulated film 13 selectively.” ʼ154 Patent, 9:21-23. A person
`
`of skill in the art would have understood that etching a through hole requires
`
`patterning before etching.
`
`73. Figure 3 of Takahashi illustrates patterning the etch-stop layer with a
`
`through hole 16 etched through the insulating film 3 (etch-stop layer). In other
`
`words, the insulating film 3 is patterned. As shown in Figure 3 of Takahashi the
`
`patterning is done after the etchable layer 82 is etched away.
`
`23
`
`

`
`74. Thus, it is my opinion that Takahashi discloses the limitations recited
`
`
`
`in [2.0].
`
`75.
`
`See claim chart A in Exhibit SAM1016.
`
`Claim 3
`
`76.
`
`It is my opinion that Takahashi anticipates claim 3 of the ʼ678 Patent.
`
`[3.0] “The method of claim 2, further including an additional step, after the
`step of patterning, of forming an electrical connection to the microelectronic
`circuit element through the patterned etch-stop layer and through the wafer.”
`
`
`77. Takahashi further discloses forming an electrical connection to the
`
`microelectronic circuit element through the patterned etch-stop layer and through
`
`the wafer.
`
`78. For example, Takahashi discloses that
`
`The surface insulating film 3 is formed thereover with a
`pad electrode 17 for connecting the drain electrode 12
`electrically through the through hole 16. The pad
`electrode 17 is provided for electric connection between
`the semiconductor device and an external circuit and is
`
`24
`
`

`
`wire-bonded, for example. For this purpose, the pad
`electrode is given a size of about 100 μm square far
`larger than that of the transistor element. Thus, the pad
`electrode occupying an especially large area is separated
`from the back wiring of the integrated circuit and formed
`on the surface so that the area of the back can be
`effectively exploited. ʼ154 Patent, 9:24-36 (emphasis
`added).
`79. A person of ordinary skill in the art would have understood that the
`
`pad electrode 17 is an example of forming an electrical connection to the
`
`microelectronic circuit element through the patterned etch-stop layer and through
`
`the wafer.
`
`80. Takahashi accomplishes patterning for the same purpose as the
`
`patterning described in the ʼ678 Patent—to exploit back-side circuitry.
`
`81. Figure 3 of Takahashi illustrates the pad electrode 17 (red) forming an
`
`electrical connection between the semiconductor device, an external circuit, and
`
`through the wafer:
`
`25
`
`

`
`
`
`82. This electrical connection through the wafer is accomplished by
`
`metalized through hole 16, which allows the pad electrode 17 to electrically
`
`connect to the drain electrode 12 that is formed in the wafer (thin film 4).
`
`83. Thus, it is my opinion that Takahashi discloses the limitations recited
`
`in [3.0].
`
`84.
`
`See chart A in Exhibit SAM1016.
`
`Claim 4
`
`85.
`
`It is my opinion that Takahashi anticipates claim 4 of the ʼ678 Patent.
`
`[4.0] “The method of claim 2, further including an additional step, after the
`step of patterning, of forming an electrical connection to the wafer through
`the patterned etch-stop layer.”
`
`
`86. Takahashi discloses forming an electrical connection to the wafer
`
`through the patterned etch-stop layer.
`
`87. As explained above in [3.0], Ground 1, the pad electrode 17 connects
`
`the drain electrode 12 electrically through the through hole 16 and provides an
`
`26
`
`

`
`electrical connection between the semiconductor device, an external circuit, and
`
`through the wafer. Additionally, Figure 3 of Takahashi also illustrates that an
`
`electrical connection is formed to the wafer through the patterned etch-stop layer:
`
`
`
`88. A person of ordinary skill in the art would have readily understood
`
`that the electrical connection to the wafer is accomplished by metalized through
`
`hole 16, which allows the pad electrode 17 to electrically connect to the drain
`
`electrode 12 and thus to drain region 7 that is formed in the wafer (thin film 4). In
`
`other words, in Takahashi, forming an electrical connection through the wafer also
`
`accomplishes forming an electrical connection to the wafer.
`
`89. Thus, it is my opinion that

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