`al. (“the ʼ678 Patent”) under 35 U.S.C. § 102
`
`
`Prior Art Cited in this Chart:
`U.S. Patent No. 4,599,792 to Cade et al. (“Cade”)
`
`
`Claim Language
`Claim 1
`A method of fabricating
`a microelectronic device,
`comprising the steps of:
`
`furnishing a first
`substrate having an
`etchable layer, an etch-
`stop layer overlying the
`etchable layer, and a
`wafer overlying the etch-
`stop layer;
`
`Cade
`
`
`“The invention pertains generally to integrated circuits.
`In particular, it pertains to the fabrication of a buried
`field shield beneath other semiconductor devices on an
`integrated circuit chip.” 1:8-11.
`“Fabrication in the second embodiment begins with a
`heavily doped p+ seed substrate 80, shown in FIG. 15,
`on which is grown the n- epitaxial layer 54.” 7:4-6.
`
`“Then the n+ emitter layer 56 and the thin dielectric
`layer 58 are grown just as in the first embodiment.”
`7:10-12.
`
`Figure 15
`
`forming a
`microelectronic circuit
`element in the exposed
`side of the wafer of the
`first substrate opposite to
`the side overlying the
`etch-stop layer;
`
`
`
`
`
`
`“The field shield 64 and the boron-rich quartz 66 are
`likewise formed by similar procedures using the laser-
`scribed alignment marks for any required definition
`including possible definition of the emitter layer 56.”
`7:24-27.
`
`“It is anticipated that the n+ region 56 is delineated on
`top of the dielectric layer 58 so that devices, such as
`1
`
`Petitioner Samsung - SAM1017
`
`
`
`Claim Language
`
`Cade
`capacitors, can be fabricated using both the insulating
`layer 58 and the field shield 64 as constituent
`elements.” 7:64-68.
`
`Figure 15
`
`attaching the wafer of the
`first substrate to a second
`substrate; and
`
`
`
`
`“The mechanical substrate 68 of silicon is then
`anodically bonded to the quartz 66 by applying voltage
`to a voltage probe 84 with the seed substrate 80
`grounded.” 7:27-30.
`
`Figure 15
`
`etching away the
`etchable layer of the first
`substrate down to the
`etch-stop layer.
`
`
`
`
`
`
`“The etch-back of the seed substrate 80 is performed
`with hydrofluoric-nitric-acetic acid (HNA) in the
`proportions of 1:3:8. The etchant HNA is an isotropic
`etch and attacks heavily doped p+ or n+ silicon.
`However, it does not appreciably attack silicon doped
`below the level of 1018 /cm3. The etch stopping
`2
`
`
`
`Claim Language
`
`Cade
`characteristics are improved by the p+ /n junction at the
`interface 82.” 7:31-37.
`
`Figure 16
`
`Claim 2
`The method of claim 1,
`further including an
`additional step, after the
`step of etching, of
`patterning the etch-stop
`layer.
`
`
`
`
`
`“The support transistors 110 and 112, the field shield
`contacts 106 and 108 and the storage cells are all
`isolated by dielectric trenches 124 extending from the
`surface to the dielectric layer 58.” 8:23-27.
`
`Figure 16
`
`
`Figure 17
`
`
`
`Claim 3
`The method of claim 2,
`
`
`
`
`
`“The field shield 104 is connected to the surface by
`3
`
`
`
`
`
`Claim Language
`further including an
`additional step, after the
`step of patterning, of
`forming an electrical
`connection to the
`microelectronic circuit
`element through the
`patterned etch-stop layer
`and through the wafer.
`
`Claim 4
`The method of claim 2,
`further including an
`additional step, after the
`step of patterning, of
`forming an electrical
`connection to the wafer
`through the patterned
`etch-stop layer.
`
`Cade
`field shield reach-throughs or contacts 106 and 108.”
`8:15-17.
`
`Figure 17
`
`
`
`
`
`“A planar contact is made to the n epitaxial layer
`18[sic]1 with an n+ layer 120 connected to the surface
`with a diffused n+ reach-through 122.” 8:20-22.
`
`Figure 17
`
`
`
`Claim 10
`The method of claim 1,
`wherein the step of
`etching includes the step
`of contacting the
`etchable layer to a liquid
`etchant that attacks the
`
`1 The reference number 18 to the n- epitaxial layer is a typographical error. The n-
`
`
`
`“The etch-back of the seed substrate 80 is performed
`with hydrofluoric-nitric-acetic acid (HNA) in the
`proportions of 1:3:8. The etchant HNA is an isotropic
`etch and attacks heavily doped p+ or n+ silicon.
`However, it does not appreciably attack silicon doped
`below the level of 1018 /cm3. The etch stopping
`
`epitaxial layer should correspond to reference number 118, as seen in Figure 17.
`
`
`
`4
`
`
`
`Cade
`characteristics are improved by the p+ /n junction at the
`interface 82.” 7:31-37.
`
`Claim Language
`etchable layer rapidly
`and the etch-stop layer
`slowly.
`
`
`
`
`
`5
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