United States Patent [191
`Margail et al.
`
`[11]‘ Patent Number:
`[45] Date of Patent:
`
`4,975,126
`Dec. 4, 1990
`
`[54] PROCESS FOR THE PRODUCTION OF AN
`INSULATING LAYER EMBEDDED IN A
`SEMICONDUCTOR SUBSTRATE BY IONIC
`IMPLANTATION AND SEMICONDUCTOR
`STRUCTURE COMPRISING SUCH LAYER
`[75] Inventors: Jacques Margail, Grenoble, France;
`John Stoemenos, Salonica, Greece
`[73] Assignee: Commissariat a l’Energie Atomique,
`France
`[21] Appl. No.: 207,379
`[22] Filed:
`Jun. 15, 1988
`[30]
`Foreign Application Priority Data
`Jun. 15, 1987 [FR] France .............................. .. 87 08272
`
`[51] Int. Cl.5 ......................................... .. H01L 21/265
`[52] US. Cl. ................................... .. 145/332; 437/24;
`437/25; 437/26; 437/ 84; 437/248
`[58] Field of Search ..................... .. 437/24, 26, 82, 84,
`437/247, 248, 25; 148/33, 33.2, 33.3
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,676,841 6/1987 Celler .................................. .. 437/24
`
`FOREIGN PATENT DOCUMENTS
`
`56-60556 4/1983 Japan ................................... .. 437/24
`
`OTHER PUBLICATIONS
`Electronics Letters, Apr. 1986, vol. 22, No. 9, K. J.
`Reeson.
`
`Japanese Journal of Applied Physics, vol. 20, No. 12,
`1987 (Irita).
`Japanese Patent Abstracts, vol. 7, No. 148, Jun. 1983
`(Toshio).
`IEEE Transactions on Electron Devices, vol. ED-33,
`Mar. 1986 (Foster).
`Solid State Technology, Mar. 1987 (G. K. Celler).
`Appl. Phys. Lett., 50(1), Jan. 1987 (Alice et al.).
`Bunker et al., “Formation of Silicon-on—1nsulator
`Structures by Multiple Oxygen Implantations”, Mat.
`Res. Soc. Symp. Proc. vol. 93 (Apr. 1987), pp. 125430.
`Primary Examiner-Olik Chaudhuri
`Attorney, Agent, or Firm—Hayes, Soloway, Hennessey
`& Hage
`ABSTRACI‘
`[s7]
`A process for the production of an insulator buried in a
`semiconductor substrate by ionic implantation, and
`semiconductor structure comprising such layer.
`According to the invention the semiconductor structure
`comprises a silicon dioxide layer (104) interposed be
`tween a silicon substrate (102) and a silicon film (106)
`obtained by successive implantations of oxygen ions in
`the substrate, with doses less than 1.51018 ions/cm2,
`each implantation being followed by an annealing at a
`temperature higher than 1100“ C. The semi-conductor
`?lm (106) has a level of dislocations lower than 105 per
`cm2, and the oxide layer (104) is completely homogene
`ous.
`
`12 Claims, 3 Drawing Sheets
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`I05
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`1
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`PROCESS FOR 'THE PRODUCTION OF AN
`INSULATING LAYER EMBEDDED IN A
`SEMICONDUCTOR SUBSTRATE BY IONIC
`IMIPLANTATION AND SEMICONDUCTOR
`STRUCTURE COMPRISING SUCH LAYER
`
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`4,975,126
`2
`line silicon substrate 2 surmounted by a silicon dioxide
`layer 4 coated with a monocrystalline silicon ?lm 6.
`The Si/SiOz interface 8 is the monocrystalline ?lm 6,
`the dioxide layer 4 being referred to as the “front inter
`face”, the Si/SiOz 10 interface between the solid sub
`strate 2 and the dioxide layer 4 being referred to as the
`“rear interface”.
`The standard conditions of the SIMOX technology
`for the formation of an oxide layer are: oxygen implan
`tation doses of 1.6 to 2.5-1018O't/cm2 ions, an implanta
`tion energy of 200 keV, a substrate heating during im
`plantation to a temperature of between 500° and 700°
`C., then a high temperature annealing to complete the
`formation of the buried silica layer at temperatures of
`between 1150° to 14050 C. More particularly, annealing
`is performed at 1300° C. for 6 hours (cf. the above arti
`cles by Stoemenos and Bruel) or at 1405° C. for 30
`minutes, as disclosed in the Celler article.
`High temperature annealing induces a segregation of
`all the implanted oxygen towards the inside of the bur
`ied silicon dioxide layer. More particularly, the silicon
`?lm 6 surmounting the dioxide layer 4 no longer con
`tains any oxide precipitate, as indicated in Bruel’s arti
`cle.
`The widely used SIMOX process has some disadvan
`tages. More particularly, the movement of oxygen or
`nitrogen ions into the silicon to a varying extent dam—
`ages the monocrystalline silicon ?lm 6, creating often
`irreparable defects 12 (FIG. 1). The defects are more
`particularly traversing dislocations anchored to the
`Si/SiOg interface 8, passing through the silicon ?lm 6
`and coming out on the surface 14 thereof. Their density
`varies between 106 and low/cmz.
`FIG. 2, which is a photograph of a semiconductor
`structure obtained by implanting oxygen ions with a
`dose of 1.61018 ions/cm2 in a silicon substrate heated to
`600° C., the substrate then being annealed at 1300° C.
`for 6 hours, clearly shows the dislocations traversing
`the monocrystalline silicon ?lm. This photograph is a
`microscopy by electronic transmission on edge.
`These defects or dislocations of the silicon ?lm cause
`a reduction in the preformances of the-electric compo‘
`nents subsequently produced in the semiconductor
`layer 6, and can form, for example, the source of junc
`tion leaks, thus producing considerable leakage cur
`rents.
`In the ?eld of guided optics such dislocations disturb
`the light vehicled by the buried silica layer, causing
`light losses.
`Moreover, the quality of the buried silicon dioxide
`layer is not perfect. More particularly, it has silicon
`islets 16 which are very troublesome, more particularly
`in microelectronics, since they reduce the voltage be
`haviour of the dioxide layer 4 and may be priviledged
`centres of charge trapping. Such silicon islets are
`clearly shown in FIG. 2.
`The presence of silicon islets or precipitates in the
`oxide layer is particularly troublesome in the case of
`MIS transistors produced in the semiconductor ?lm 6.
`In this respect FIG. 3 shows a front transistor 18
`comprising source 20 and a drain 22 respectively de
`?ned by implantation of n-type or p-type ions in the
`monocrystalline ?lm 6, and a grid 24, generally consist~
`ing of polycrystalline silicon, surmounting the silicon
`?lm 6 and isolated therefrom by the grid oxide 26. The
`channel 28 of the front transistor 18 is de?ned beneath
`
`DESCRIPTION
`The invention relates to a process for the production
`of a continuous layer of oxide or nitride buiiedin a
`semiconductor substrate, by implantation of oxygen or
`nitrogen ions in the substrate, and also to semiconductor
`structures comprising such buried layer of oxide or
`nitride.
`The invention relates more particularly to the pro
`duction of MIS (metal/insulator/semiconductor) inte
`grated circuits, CMOS (compatible metal/oxide/semi
`conductor) integrated circuits or bipolar circuits of the
`silicon-on-insulator type, which operate very quickly
`and are possibly highly resistant to ionizing radiations
`and must dissipate high powers. The invention also
`applies to the ?eld of guided, possibly integrated optics,
`for the production of ?at or stripe-type light guides.
`Silicon-on-insulator technology represents a substan
`tial improvement in the ?eld of microelectronics in
`comparison with the standard techniques in which the
`active components of the integrated circuits are pro
`duced directly on a solid silicon monocrystalline sub
`strate, since the use of an insulating support results in a
`considerable reduction in the stray capacity as between
`the source and the substrate on the one hand, and the
`drain and the substrate on the other, and reduces con
`siderably the active components of the circuits, the
`result being an increase in the operating speed of such
`circuits.
`Silicon~on-insulator technology also leads to an ap
`preciable simpli?cation of manufacturing processes, an
`increase in integration density, improved behaviour
`under high voltages, and low sensitivity to radiations,
`since the volume of monocrystalline silicon is low.
`One of the silicon-on-insulator technologies at pres
`ent known ‘consists of implanting oxygen 0+ ions or
`nitrogen N+ ions in heavy doses in solid monocrystal
`line silicon, so as to form, after high temperature anneal
`. ing of the substrate, a buried insulating layer‘ of silicon
`dioxide or silicon nitride. This process, known as the
`SIMOX process (separation by implanted oxygen) has
`formed the subject of a large number of publications.
`In this respect the following may be cited: the article
`by P. L. F. Hemment “Silicon~on-insulator formed by
`0+ or N+ ion implantation”, published in Mat. Res.
`Soc. Symp., vol. 53, 1986; the article by J. Stoemenos et
`al. “New conditions for synthesizing SOI structures by
`high dose oxygen implantation”, published in the Jour
`nal of Crystal Growth 73 (1985) 546-550; the article by
`55
`M. Bruel et al. “High temperature annealing of SIMOX
`layers”, published in E. MRS. Strasbourg, June 1986,
`pp. 105-119; the article by J. Stoemenos et al., published
`in Appl. Phys. Lett. 48 (2l), 26 May 1986, PP.
`1470-1472, entitled “SiOz buried layer formation by
`60
`subcritical dose oxygen ion implantation” or the article
`by G. K. Celler et a1. “High quality Si-ON-SiOz ?lms by
`large dose oxygen implantation and lamp annealing”,
`published in Appl. Phys. Lett. 48 (8), of 24 Feb. 1986,
`pp. 532-534.
`FIG. 1 shows a semiconductor structure obtained by
`the SIMOX process in diagrammatical longitudinal
`section. The structure comprises a solid monocrystal
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`tion is also applied to the obtaining of a buried nitride
`the grid oxide 26, between the source and the drain of
`layer and allows an improvement in the crystalline
`the transistor.
`properties of such nitride layer and in the monocrystal
`Associated with the front transistor 18 is a rear tran
`line ?lm surrounding such layer.
`sistor 30 whose channel 32 lies between the source 20
`and the drain 22; the buried oxide layer 4 plays the role
`The invention therefore relates to a process for the
`of grid oxide, while the solid silicon substrate 2 plays
`production of a continuous layer of insulating material
`the role of grid in the rear transistor.
`buried in a semiconductor substrate, characterized in
`The presence of silicon islets 16 in the buried oxide
`that a number of successive ionic implantation of oxy
`layer 4 may more particularly act as a ?oating grid and
`gen or nitrogen are formed in the substrate, with the
`modify the threshold voltage of the rear transistor 30,
`same energy and doses lower than 1.5-1Ol8 ions
`which it may therefore trigger at the wrong time.
`O't/cm2, each implantation being followed by an an
`The precise location of the silicon islets 16 depends
`nealing of the substrate at a temperature higher than
`on the implantation dose of oxygen ions, since the low
`800° C., but lower than the melting temperature of the
`implantation does, lower than 141018 ions/cm2, the
`substrate, so as to form a buried insulating layer of oxy
`islets 16 are inside the oxide layer 4, as shown in FIG. 2
`gen or nitride respectively.
`of the Stoemenos article in Appl. Phys. Lett cited here
`The process on the one hand allows a considerable
`inbefore.
`reduction in the level of dislocation of the semiconduc
`In the case of does of between 1.4 and 1.6-10l8
`tor ?lm formed above the buried insulating layer, while
`ions/cm2, the presence of the silicon islets is limited to
`at the same time eliminating the presence of precipitates
`the front 8 and rear 10 Si/SiOz interfaces (FIG. 1), as
`of semiconductor materials observed in the buried insu
`shown in FIG. 5 of Bruel’s article.
`'
`lating layer by the oxidation or nitridation of such pre
`Lastly, for higher doses, above 161018 ions/cmz, the
`cipitates, in dependence on whether oxygen or nitrogen
`presence of these silicon islets is observed solely adja
`ions are implanted.
`cent the rear interface 10, as disclosed in the Article by
`According to the invention the implantation of oxy
`Stoemenos published in the Journal of Crystal Growth.
`gen or nitrogen ions is performed in a number of stages.
`This latter con?guration is shown in FIGS. 1 and 2.
`The dose of ions implanted in each ionic implantation is
`The formation of these silicon islets, also known as
`lower than the total dose of ions to be implanted. More
`silicon precipitates, was explained in Bruel’s article; it
`over, the number of implantations is a function of the
`results from the development after high temperature
`total dose of ions to be implanted and of the dose of ions
`annealing (approximately 1300° C.) of non-abrupt Si/
`implanted in each implantation.
`SiOz interfaces of lamellar structure. The formation of
`The total dose of ions depends on the thicknesses of
`these islets is inevitable.
`the insulating layer and of the monocrystalline ?lm
`Since the coef?cient of diffusion of the silicon
`surmounting such insulating layer which is to be ob
`through the silicon oxide is extremely low (of the order
`tained. For a given implantation energy, the thickness
`of lO-29 /cm2 at 400° C.), the Inventors have found that
`of the layer of insulator increases with the number of
`the only way to eliminate the silicon precipitates from
`dose of implantation and conversely, the thickness of
`the oxide layer was to oxidize them. The processing
`the monocrystalline ?lm surmounting the layer of insu
`according to the invention allows such oxidation of the
`lator decreases with the number and dose of implanta
`silicon precipitates.
`tion.
`The Inventors also show in an article “Self-interstitial
`By way of example, for a number of implantations of
`migration in Si implanted with oxygen” published in
`oxygen ions with an energy of 200 keV in silicon, the
`Physica Scripta, vol. 35, 42-44, 1987, that the formation
`total dose of implanted ions must be lower than 3.8-1018
`of the buried layer of silicon dioxide 4 (FIG. 1) brings
`ions O+/cm2; above that value there is no silicon ?lm
`into play in the direction of the surface 14 of the struc
`and the insulating layer is no longer buried.
`ture an important ?ux of silicon atoms displaced from
`The number of implantations and the dose of ions
`their positions in the crystal and therefore being in an
`implanted in each implantation also depends on the
`interstitial position.
`nature of the ions and the nature of the substrate in
`During implantation, the silicon dioxide precipitates
`which the ions are implanted.
`forming in the monocrystalline ?lm 6 block the “migra
`In the case of the implantation of 0+ ions in a silicon
`tion” towards the surface 14 of the interstitial silicon
`substrate, the number of implantations can, for example,
`atoms, which therefore tend to become condensed in
`vary between 2 and 10, and the dose of ions implanted
`the form of dislocation loops in either side of the buried
`in each implantation can vary between 1016 and 0.9-1018
`oxide layer. The number of dislocation loops increases
`ions O+/cm2. More particularly, in the case of a buried
`with the dose of oxygen ions implanted. After annealing
`silicon dioxide layer 330 and 400 nm in thickness respec
`at high temperature, it is the dislocation loops which
`tively for a monocrystalline silicon ?lm of 260 and 200
`cause the formation of the traversing dislocations 12 in
`nm respectively, use can be made respectively of 5 and
`the semiconductor ?lm.
`6 oxygen ion implantations with doses of 3-1017 ions
`In addition to eliminating the silicon precipitates pres
`O+/cm2, corresponding to a monoimplantation of 1.5
`ent in the silicon dioxide layer, the process according to
`and 1.8-10l8 ions/cm2 respectively.
`the invention allows a reduction in the density of the
`The implantation energies, which are identical from
`dislocations, more particularly the traversing disloca
`one implantation to another, are a function of the depth
`tions, present in the silicon ?lm surrounding the silicon
`dioxide layer.
`of penetration of the ions; the more the energy in
`creases, the more the penetration depth increases. The
`Although not much is known about the phenomena
`energies, for example, are between 100 and 1000 keV.
`of defect formation in the monocrystalline silicon ?lm
`65
`and the obtaining of a buried insulating layer, resulting
`According to the invention, for example, oxygen or
`nitrogen ions can be implanted in a monocrystalline
`from the implantation of N+ ions in a silicon substrate in
`silicon substrate.
`order to form a buried layer of silicon nitride, the inven
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`as illustrated in the article by Stoemenos in Appl. Phys.
`For a silicon substrate, the implantation of oxygen
`ions leads to the obtaining of a buried SiOz layer, while
`Lett. cited hereinbefore.
`Then the encapsulating layer is eliminated by a chem
`nitrogen ionic implantation results in the formation of a
`ical engraving with an attack bath comprising FH and
`buried silicon nitride layer of formula Si3N4.
`To perform an in situ annealing of the lattice defects
`created by ion implantation, in other words to avoid
`making the seminconductor ?lm amorphous and to
`improve its quality, advantageously the substrate is
`heated during implantation. For a silicon substrate such
`heating varies between 500° and 700° C.
`The temperature of annealing following each ion
`implantation depends on the nature of the semiconduc
`tor substrate. Moreover, the higher the annealing tem
`perature, the shorter will be the duration of such anneal
`ing. For a silicon substrate the annealing temperature is
`higher than 1100° C. and may range between 1150° and
`1400° C. and advantageously between l300° and 1400°
`C.; the melting temperature of silicon is l415° l C.
`The process according to the invention enables semi
`conductor structures to be obtained comprising an insu
`lating layer interposed between a semiconductor sub
`strate and a semiconductor ?lm and obtained by the
`ionic implantation of oxygen or nitrogen in the sub
`strate, characterized in that the semiconductor ?lm has
`a level of dislocations less than 105 per cm2, and the
`insulating layer is homogeneous.
`The value 105 per cm2 is due to the limit of detection
`by present-day planar electronic microscopy.
`Other features and advantages of the invention will
`be gathered from the following illustrative, non-limi -
`tive description. The description refers to the accompa
`nying drawings, wherein:
`FIG. 1 already described, shows diagrammatically in
`longitudinal section a prior art structure obtained by the
`SIMOX process,
`FIG. 2 is a microscopy photograph by electronic
`transmission on edge of a prior art structure obtained by
`implanting oxygen ions in monocrystalline silicon,
`FIG. 3, already described, shows diagrammatically
`an MOS transistor produced in a silicon layer surmount
`ing a layer of silicon dioxide,
`FIG. 4 illustrates the process of producing a buried
`silicon dioxide layer, and
`FIG. 5 is a microscopy photograph by electronic
`transmission on edge of the structure obtained by the
`process according to the invention.
`In an example of an embodiment of the process ac
`cording to the invention, illustrated in FIG. 4, a ?rst
`implantation of 0+ ions 103 is performed with a dose of
`0.84013 ions/cm2 and an energy of 200 keV in a monoi
`crystalline silicon substrate 102. An implanted oxygen
`layer 105 is obtained surmounted by a monocrystalline
`silicon ?lm 106, as indicated in part (a) of FIG. 4. Heat
`ing the substrate to a temperature of the order of 600° C.
`during the implantation more particularly forms an
`annealing stage enabling the crystalline quality of the
`semiconductor ?lm 106 to be improved.
`Then a plasma-assisted chemical deposit in the va
`pour phase is preformed of an encapsulating silicon
`dioxide layer 600 nm in thickness, as illustrated in part
`(b) of FIG. 4, ensuring protection of the silicon ?lm 106
`during the high temperature annealing. The annealing is
`performed at l320° C. for 6 hours.
`According to the invention the ?rst ion implantation
`followed by the ?rst high temperature annealing
`(higher than 1100. C.) leads to a buried silicon dioxide
`layer 104 containing very numerous precipitates or
`islets of silicon localized inside the silicon dioxide layer,
`
`Then a fresh oxygen ion implantation is performed
`with a dose of 0.8-10l8 ions/cm2 and an energy of 200
`keV. An encapsulating layer 107 is again deposited by
`plasma-assisted chemical deposit in the vapour phase,
`whereafter annealing is again performed at 1320’ C. for
`6 hours.
`The second implantation followed by annealing con
`tributes the oxygen necessary for the oxidation of the
`silicon precipitates present in the buried dioxide layer
`104, thus leading to abrupt front 108 and rear 10 Si/
`SiOz interfaces.
`After the elimination of the second encapsulating
`layer, a semiconductor structure as shown in part (c) of
`FIG. 4 is obtained.
`The two successive implantations lead to a total im
`planted dose of 1.6-1018 ions/cm2.
`This method of operation leads to the obtaining of a
`silicon dioxide layer 104 having a thickness of 380 nm
`and a semiconductor ?lm 106 of the order of 170 nm in
`thickness.
`The structure obtained in these conditions is shown in
`the photograph reproduced in FIG. 5. It can clearly be
`seen from the photograph, which was produced by
`X-microscopy by electronic transmission on edge that
`the silicon ?lm 106 surmounting the buried silicon diox
`ide layer 104 is free from traversing dislocations. A
`characterization by electronic transmission on edge
`showed that the density of dislocations in the silicon
`?lm is less than 105 per cmZ. Moreover, the dioxide
`layer 104 is free from silicon islets and the front 108 and
`rear 110 Si/SiOz interfaces are abrupt. This is very
`important for the industrial production of integrated
`circuits or wave guides having outstanding electric and
`optical properties respectively.
`The process according to the invention enables sili
`con-on-insulator structures of outstanding quality to be
`produced. It enables SIMOX structures to be produced
`which contain a very small quantity of dislocations, less
`than l05/cm2 and comprising a buried silicon dioxide
`layer free from Si islets and completely homogeneous.
`The process according to the invention does not
`question the industrial nature of the production of
`SIMOX structures, but on the other hand enables the
`quality of the layer of monocrystalline silicon to be
`improved, thus making this kind of material more com
`patible with industrial requirements.
`Apart from the production of integrated circuits in
`silicon-on-insulator technology, the process according
`to the invention can be advantageously used for making
`wave guides in integrated optics on a silicon substrate.
`The wave guides are formed by one or more layers of
`SiO; and or Si3N4 produced by the ionic implantation of
`oxygen or nitrogen according to the invention, with
`different implantation energies, the depth of implanta
`tion of the ions increasing with the implantation energy.
`The foregoing description is of course merely given
`by way of illustration, since any modi?cation may be
`considered without exceeding the scope of the inven
`tion. More particularly, an implantation can be per
`formed after covering of the semiconductor substrate
`with an encapsulating S102 layer. The use of such en
`capsulating layer is more particularly disclosed in the
`article by Bruel cited hereinbefore.
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`7. A process for producing an oxide continuous layer
`(104) buried in a silicon monocrystalline substrate (102),
`consisting essentially of the steps in sequence:
`(A) a ?rst ionic implantation of oxygen in the sub
`strate which is at a temperature from 500° to 700°
`C. for performing an in situ annealing of the lattice
`defects created by the ?rst implantation, said ?rst
`implantation being performed at a predetermined
`energy and at a dose lower than 1.5><1013 ions
`O‘t/cm2 whereby to avoid the formation of dislo
`cations in the silicon ?lm provided in the oxide
`layer;
`(B) a ?rst encapsulation of the structure obtained in
`Step (A),
`(C) a ?rst annealing of the structure obtained in step
`(B) at a temperature higher than 800° C., but lower
`than the melting temperature of the substrate,
`whereby to produce said oxide buried layer and
`precipitates of silicon at the interfaces silicon
`oxide;
`(D) eliminating the ?rst encapsulation;
`(E) at least one second ionic implantation of oxygen
`in the structure obtained in step (D) at said prede
`termined energy and at a dose lower than
`l.5>< 1018 ions O+/cm2, said second implantation
`being performed while the substrate is at a temper
`ature from 500° to 700° C. for performing an in situ
`annealing of the lattice defects created by said
`second implantation;
`(F) at least second encapsulation of the structure
`obtained in step (E); and
`(G) at least one second annealing of the structure
`obtained in step (F) at a temperature higher than
`800° C., but lower than the melting temperature of
`the substrate, so as to oxidize said precipitates of
`silicon.
`8. A process according to claim 7, characterized in
`that the number of implantations and the dose of im
`planted ions depend on the total dose of ions which is to
`be implanted.
`9. A process according to claim 7, characterized in
`that the annealings are performed at a temperature
`higher than 1100° C.
`10. A process according to claim 7, characterized in
`that the annealings are performed at a temperature be
`tween l300° and 1400“ C.
`11. A semiconductor structure comprising an insulat
`ing layer (104) interposed between a semiconductor
`substrate (102) and a semiconductor ?lm (106) and ob
`tained by the process according to claim 7, character
`ized in that the semiconductor ?lm (106) has a level of
`dislocations less than 105 per cm2, and the insulating
`layer (104) is homogeneous.
`12. A process according to claim 7, characterized in
`that the number of implantations is 2, each implantation
`being performed at 08-1018 ions/cm2.
`* i * * *
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`
`We claim:
`1. A process for producing an oxide continuous layer
`(104) buried in a silicon monocrystalline substrate (102),
`consisting essentially of the steps, in sequence:
`(A) a ?rst ionic implantation of oxygen in the sub
`strate which is at a temperature from 500° to 700°
`C. for performing an in situ annealing of the lattice
`defects created by the ?rst implantation, said ?rst
`implantation being performed at a predetermined
`energy and at a close lower than 1.5)(10l8 ions
`O+/cm2 whereby to avoid the formation of dislo
`cations in the silicon ?lm provided in the oxide
`layer;
`(B) a ?rst annealing of the structure obtained in step
`(A) at a temperature higher than 800° C., but lower
`than the melting temperature of the substrate,
`whereby to produce said oxide buried layer and
`precipitates of silicon at the interfaces silicon
`oxide;
`(C) at least one second ionic implantation of oxygen
`in the structure obtained in step (B) at said prede
`termined energy and at a dose lower than
`l.5>< 1018 ions O+/cm2, said second implantation
`being performed while the substrate is at a temper
`ature from 500° to 700° C. for performing an in situ
`annealing of the lattice defects created by said
`second implantation; and,.
`(D) at least one second annealing of the structure
`obtained in step (C) at a temperature higher than
`800° C., but lower than the melting temperature of
`the substrate, so as to oxidize said precipitates of
`35
`silicon.
`2. A process according to claim 1, characterized in
`that the number of implantations and the dose of im
`planted ions depend on the total dose of ions which is to
`be implanted.
`3. A process according to claim 1, characterized in
`that the annealings are performed at a temperature
`higher than 1100° C.
`4. A process according to claim 1, characterized in
`that the annealings are performed at a temperature be»
`tween l300° and. 1400° C.
`5. A semiconductor structure comprising an insulat
`ing layer (104) interposed between a semiconductor
`substrate (102) and a semiconductor ?lm (106) and ob
`tained by the process according to claim 1, character
`ized in that the semiconductor ?lm (106) has a level of
`dislocations less than 105 per cm2, and the insulating
`layer (104) is homogeneous.
`6. A process according to claim 1, characterized in
`that the number of implantations is 2, each implantation
`being performed at 08-1018 ions/cm2.
`
`55
`
`50
`
`65
`
`8