UNITED STATES DEPARTMENT OF COMMERCE •
`
`Maurice H. Stans, Secretary
`
`NATIONAL BUREAU OF STANDARDS e
`
`Lewis M. Branscomb, Director
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`TECHNOLOGY
`
`FEDERAL DOC.
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`Silicon Device Processing
`
`Proceedings of a Symposium
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`Held at Gaithersburg, Maryland
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`June 2-3, 1970
`
`Charles P. Marsden, Editor
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`Institute for Applied Technology
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`National Bureau of Standards
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`Washington, D.C. 20234
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`
`
`Under the Sponsorship of Committee F-1
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`of the
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`American Society for Testing and Materials
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`and
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`The National Bureau of Standards
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`National Bureau of Standards Special Publication 337
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`Nat. Bur. Stand. (U.S.), Spec. Publ. 337, 467 pages (Nov. 1970)
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`CODEN: XNBSA
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`Issued November 1970
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`For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402
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`(Order by SD Catalog No. C 13.10:337), Price $5.50
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`UNIVERSITY OF MICHIGAN
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`3 9015 08649.9962
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`1
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`Petitioner Samsung - SAM1009
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`

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`Paper No.
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`Page No.
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`CONTENTS
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`Welcoming Remarks
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`Dr. Lewis M. Branscomb, Director, National Bureau of Standards
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`Some Thoughts on How We Might Improve Our Materials and Process Work
`
`Dr. D. G. Thomas, Executive Director, Bell Telephone Laboratories
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`SESSION I – GENERAL, CHAIRMAN – D. E. KOONTZ
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`Crystallographic Imperfections as Related to Silicon Crystal Growth
`
`l]
`
`J. A. Lenard, IBM, Components Division
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`A Review of Silicon Substrates Surface Preparation and Evaluation
`
`K. E. Lemons, Signetics Corporation
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`Paper Withdrawn from Publication
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`Epitaxial Growth of Silicon
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`B. A. Joyce, Mullard Research Laboratories
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`Diffusion in Silicon: Properties and Techniques
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`C. F. Gibbon, Bell Telephone Laboratories, Inc.
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`Measurement and Control of Dielectric Film Properties During Semiconductor Device
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`Processing
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`B. E. Deal, Fairchild Camera and Instrument
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`SESSION II-A - EPITAXY-TECHNIQUES AND FACILITIES, CHAIRMAN - J. W. CARLSON
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`Equipment Considerations for Silicon Epitaxy Reactors
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`M. L. Hammond and W. P. Cox, Hugle Industires, Inc.
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`19
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`2]
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`36
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`5]
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`A Comparison of a Resistance Heated Reactor for Silicon Epitaxial Growth With Other
`
`60
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`Epitaxial Systems
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`W. A. Kohler, Fairchild Camera and Instrument Corp.
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`10.
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`Techniques for Depositing Highly Uniform and Defect-Free Epitaxial Silicon
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`66
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`D. C. Gupta, The Waltham Research Center of the General Telephone and Electronics
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`Laboratories, Inc. and J. L. Porter, Sylvania Electric Products, Inc.
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`11.
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`Control of Thin Silicon Films Grown From Silane
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`D. J. Dumin, RCA Laboratories
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`12.
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`The Growth of Submicron Single and Multilayer Silicon Epitaxy
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`J. Simpson, A. C. Adams and M. H. Hanes, Bell Telephone Laboratories, Inc.
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`SESSION II-B - DIFFUSION-PROPERTIES CHARACTERISTICS, CHAIRMAN - E. E. GARDNER
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`13.
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`Techniques for Determining Surface Concentration of Diffusants
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`J. C. Irvin, Bell Telephone Laboratories
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`14.
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`15.
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`Current Status of the Spreading Resistance Probe and Its Application
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`T. H. Yeh, IBM Components Division
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`Incremental Sheet Resistivity Technique for Determining Diffusion Profiles
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`R. P. Donovan and R. A. Evans, Research Triangle Institute
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`16.
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`Nuclear Methods for the Determination of Diffusion Profiles
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`B. J. Masters, IBM Components Division
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`Use of High-Energy Ion Beams for Analysis of Doped Surface Layers
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`S. L. Chou, L. A. Davidson and J. F. Gibbons, Stanford Electronics Laboratories
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`79
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`87
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`99
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`111
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`123
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`132
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`14]
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`Vi
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`2
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`

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`Paper No.
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`Page No.
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`Determination of Diffusion Coefficients in Silicon and Accepted Values
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`M. F. Millea, Aerospace Corporation
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`SESSION III-A - DIFFUSION-TECHNIQUES AND FACILITIES, CHAIRMAN - F. L. GITTLER
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`19.
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`Diffusion Technology For Advanced Microelectronic Processing
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`. .
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`.
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`.
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`W. Greig, K. Cunniff, H. Hyman and S. Muller, RCA Solid State Division
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`20.
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`Diffusion From Doped-0xide Sources
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`M. L. Barry, Fairchild Camera and Instrument Corporation
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`2].
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`Capacitance-A Device Parameter and Tool for Measuring Doping Profiles
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`B. R. Chawla, Bell Telephone Laboratories, Inc.
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`22.
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`Concentration Dependent Diffusion Phenomena
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`P. E. Bakeman, Jr., Rensselaer Research Corporation and J. M. Borrego,
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`Rensselaer Polytechnic Institute
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`23.
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`Orientation Dependent Diffusion Phenomena
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`L. E. Katz, Bell Telephone Laboratories, Inc.
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`24.
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`Diffusion Inducted Defects and Diffusion Kinetics in Silicon
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`M. L. Joshi, IBM, Components Division and S. Dash, Fairchild Semiconductor
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`156
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`168
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`175
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`182
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`184
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`192
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`202
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`SESSION III-B - EPITAXY-PROPERTIES AND CHARACTERISTICS, CHAIRMAN - D. C. GUPTA
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`25.
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`26.
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`27.
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`28.
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`29.
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`Limitations of Current Epitaxial Evaluations (Abstract Only)
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`223
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`R. N. Tucker, Fairchild Semiconductor. Paper Withdrawn from Publication
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`On the Interpretation of Some Measurement Methods for Epitaxially Grown Layers
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`224
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`P. J. Severin, Philips Research Laboratories
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`Thickness Measurement of Very Thin Epitaxial Layers by Infrared Reflectance
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`234
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`P. A. Schumann, Jr., IBM Components Division
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`Spreading Resistance Measurements on Buried Layers in Silicon Structures
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`244
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`R. G. Mazur, Westinghouse Research Laboratories
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`Wariations of a Basic Capacitance-Voltage Technique for Determination of
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`256
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`Impurity Profiles in Semiconductors
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`W. C. Niehaus, W. VanGelder, T. D. Jones and P. Langer, Bell Telephone
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`Laboratories
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`3I.
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`Structural Faults in Epitaxial and Buried Layers in Silicon in Device Fabrication
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`285
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`P. Wang, F. X. Pink and D. C. Gupta, General Telephone and Electronics Laboratories
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`An Instrument for Automatic Measurement of Epitaxial Layer Thickness
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`A. C. Roddan, Beckman Instruments, Inc. and W. Vizir, Fairchild Semiconductor
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`30.
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`A New Impurity Profile Plotter for Epitaxy and Devices
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`B. J. Gordon and H. L. Stover, University of Southern California and
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`R. S. Harp, California Institute of Technology
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`SESSION IV-A - INTERDEPENDENCE OF UNIT PROCESSING OPERATIONS, CHAIRMAN – J. OROSHNIK
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`33.
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`A Statistical Approach to the Design and Fabrication of Diffused Junction
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`Transistors
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`D. P. Kennedy, IBM, Components Division
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`Previously published in IBM J. of R and D 8, 482 (1964)
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`34.
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`Defects Induced in Silicon Through Device-Processing
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`M. L. Joshi and J. K. Howard, IBM, Components Division
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`35.
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`A Study Relating MOS Processes to a Model of the Al-SiO2-Si System
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`M. H. White, F. C. Blaha and D. S. Herman, Westinghouse"Corporation
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`302
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`273
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`313
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`365
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`Vii
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`3
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`

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`Paper No.
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`36.
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`37.
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`38.
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`39.
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`Activation Analysis in Silicon Device Processing
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`G. B. Larrabee and H. G. Carlson, Texas Instruments, Inc.
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`Page NO.
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`375
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`The Use of the Scanning Electron Microscope as a Semiconductor Device Production
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`384
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`Line Quality Control Tool
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`_
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`J. w. Adolphsen and R. J. Anstead, NASA Goddard Space Flight Center.
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`Metallization Deposition Parameters and Their Effect on Device Performance
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`J. R. Black, Motorola, Inc.
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`Methods for Determination of the Characteristics of Hyper-pure Semiconductor
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`Silicon and Their Information Content for Device Production
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`Fritz G. Vieweg-Gutberlet, Hacker Chemitronic GMBH
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`398
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`409
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`SESSION IV-B - SURFACE PREPARATION, CHAIRMAN - E. MENDEL
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`40.
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`Mechanical Damage-Its Role in Silicon Surface Preparation
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`412
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`R.
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`B. Soper, Semiconductor Processing Co., Inc.
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`4l.
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`Crystallographic Damage to Silicon By Typical Slicing, Lapping, and Polishing
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`419
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`Operations
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`T. M. Buck and R. L. Meek, Bell Telephone Laboratories
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`42.
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`43.
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`44.
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`4s.
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`The Preparation of Practical, Stabilized Surfaces for Silicon Device Fabrication
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`43l
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`A. Mayer and D. A. Puotinen, RCA Corporation
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`Surface Contamination
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`436
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`J. N. Faust, Jr., University of South Carolina
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`The Precipitation of Oxygen in Silicon and Its Effect on Surface Perfection
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`442
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`w. J. Patrick, IBM, Components Division
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`Auger Spectroscopy and Silicon Surfaces
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`J. H. Affleck, General Electric Company
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`450
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`457
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`46.
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`Characterization of Semiconductor Surfaces and Interfaces by Ellipsometry
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`N. M. Bashara, University of Nebraska
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`viii
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`4
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`

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`Mechanical Damage - Its Role in Silicon Surface Preparation
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`R. B. Soper
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`Semiconductor Processing Co., Inc.
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`Hingham, Mass. 02043
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`Silicon is mechanically damaged during the centerless grinding, slicing, lapping and mechanical
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`polishing operations used to shape the ingot into wafers. Surface damage, removed by chemical pro
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`cesses and peripheral defects such as conchoidal fractures, indents, and microcracks are discussed.
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`A comparison of various polishing methods and how they relate to mechanical damage is given.
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`Key Words: Centerless grinding, etching, lapping, mechanical damage, peripheral damage,
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`polishing, silicon, slicing, surface damage, surface preparation.
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`1. Introduction
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`The silicon surface quality sufficient for the manufacture of different devices varies widely; for instance, a
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`simple diode may require only a surface obtained from the free etching of a sawn slice, whereas the slice used
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`for the vidicon image tube should be of precise diameter, polished on both sides, free of any peripheral or sur
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`face damage, thin (four to six mils), flat and parallel.
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`To prepare the high quality silicon surface required for today's sophisticated devices, consideration must be
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`given to the damage created by the necessary abrasive operations such as centerless grinding, orientation flat
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`generation, slicing and lapping. Operations such as polarity probing, resistivity measurements, thickness mea
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`surement and handling with tweezers can also cause thermal or impact damage to the silicon surface. Abrasive,
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`thermal and impact damage is best removed by chemical processes. The final polishing operation should leave
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`the surface as damage-free as possible.
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`In the last decade mechanical damage induced in semiconductor materials has been investigated by many
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`workers. (1-10)" There has been a difference in the depths of damage reported by different workers because of
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`the variables involved in the abrasive operations and in the techniques used to determine the depth of the damaged
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`layer. These points will be further discussed by others at this meeting.
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`The primary concern of this paper will be the damage created at the periphery of the wafer and how it can be
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`controlled.
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`2.
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`Peripheral Damage
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`Below is a description of the different types of mechanical damage which is located or is generated at the
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`periphery of the wafer.
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`Conchoidal Fracture – A conchoidal fracture is a spalled flake of silicon. It may be shallow or deep, and multiple
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`fractures may be on both sides of the wafer. In some cases partial spalling results due to incomplete fracturing.
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`Indent - An indent fracture is any irregularity from the normal profile of the wafer. It may be bounded by crystal
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`ographic planes or be random in shape.
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`Microcrack - A microcrack is a minor break which does not involve any appreciable separation of silicon. The
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`depth usually penetrates the entire thickness of the wafer. The break normally follows a crystalographic plane,
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`but the initiating force can be directed so as to yield a multi-directional break.
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`1 Figures in brackets indicate the literature references at the end of this paper.
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`412
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`5
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`

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`Scratch - A scratch is a very narrow surface groove caused by an oversized abrasive particle or other sharp ob
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`ject. Scratches can be classified into three categories:
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`-
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`a) An invisible scratch beneath a specular surface
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`b) A microscratch with shallow damage and
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`c) A macroscratch with deep damage which often causes wafer breakage.
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`Saw Mark - A saw mark is a definite damaged line which follows the curvature of the saw blade.
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`These damage defects often appear in combination with each other such as a microcrack extending from the
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`edge of a conchoidal fracture or from the apex of an indent.
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`The peripheral damage is frequently de-emphasized because it appears outside of the complete device pattern;
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`however, this damage is a prime source of high density dislocations and of ultimate breakage of costly wafers
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`which have been processed to the device stage. A sawn slice with peripheral damage can harbor abrasives and
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`other foreign materials which may be released during polishing and which in turn may scratch the surface of the
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`wafer.
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`3. Shaping Operations
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`3.1 Centerless Grinding
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`The peripheral damage begins with the centerless grinding of the silicon ingot which is required when a uni
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`form slice diameter is desired. Severe damage can be created if great care is not taken.
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`The technology of grinding has advanced a great deal in recent years, but it is still a complicated art which
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`is not well understood. Grinding implies that the abrasive is fixed or bonded to the grinding tool; therefore, the
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`silicon is abraded away by a cleaving action.
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`Centerless grinding machines use either abrasive belts or abrasive wheels. The latter is normally associated
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`with more massive and stable machines. Some of the other variables in centerless grinding are type of abrasive,
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`size of abrasive particles, surface speed of abrasive, type of coolant, thickness of silicon removed on each pass
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`and, of course, the skill of the operator. These variables influence the degree of damage because large abrasive
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`particles cleave out chips from the silicon surface; and high surface speed, improper coolant and gross thick
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`nesses of silicon removed with each pass cause excessive frictional heat which drives the damage deeper into the
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`crystal.
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`In properly ground ingots the damaged layer does not exceed 5 mils and can be removed by chemical etching.
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`A slow etch rate is preferred since the heat generated by fast etches may propagate the damage still further into
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`the surface. (11)
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`Orientation flats or notches are also generated by abrasive methods and must receive the same considerations
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`as the ground cylindrical surface of the ingot.
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`3.2 Ingot Mounting
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`The next operation to be considered is the mounting of the silicon ingot on a fixture for sawing. This will vary
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`with the machine and method used for sawing but usually the ingot is held in place with a wax or plastic. In using
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`wax, it becomes necessary to heat the ingot above the melting point of the wax for good adhesion; but care should
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`be employed to heat the ingot slowly and evenly to reduce the thermal gradient within the ingot, otherwise thermal
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`damage may be caused – especially in any area in which mechanical damage exists. If a plastic such as an epoxy
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`is used, the ingot need not be heated because the plastic will cure at room temperature even though it takes longer
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`than at elevated temperatures.
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`Often times the etched ingot is abraded in the region where it is bonded to the mounting fixture so as to in
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`crease the adhesion. Of course, this abrasion introduces mechanical damage, and this procedure should be
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`eliminated if possible. If the etched ingot is clean and free from soils deposited onto the surface during handling
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`or storage and the proper mounting medium is chosen, the abrading step will not be necessary.
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`413
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`6
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`

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`3.3 Slicing
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`The effect of peripheral damage is first observed at slicing. Obviously, peripheral damage can be initially
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`caused by slicing, but often it is the result of the preceding operations. An improperly mounted and damaged in
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`got will create many slicing problems and defects.
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`Semiconductor Processing Co. receives from many customers as-sawn silicon wafers to be polished. The
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`quality of the wafers vary widely. Some wafers are flat, parallel, free of peripheral defects and have no saw
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`marks, where as other wafers have gross damage which extends throughout the thickness of the wafer. Bowed
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`and non-parallel wafers must receive special consideration so as to insure the complete removal of all surface
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`damage.
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`Both peripheral and surface damage is influenced by the sawing technique used. The conventional ID diamond
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`wheel is capable of producing less damage than the OD diamond wheel. The Norton multi-blade abrasive saw and
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`the various wire saws produce a minimum of damage because of the more gentle lapping action involved, but one
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`must be aware of the possibility of abrasive being imbedded into the silicon surface. Electrochemical and chemi
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`cal slicing may be the ideal approach in respect to damage produced, but as yet these techniques have not gone
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`beyond the stage of laboratory investigation.
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`If the silicon ingot has been properly prepared and the slicing procedure has been optimized, the sawn wafer
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`will have a minimum damaged layer. A signal that the damaged layer in much deeper is the observance of
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`numerous edge defects.
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`Also there is evidence that the extent of damage differs between the two surfaces A & B (Figure 1) of the sawn
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`wafer. The A surface, Figure 1, is more susceptible to damage as it is flexing while in intimate contact with the
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`diamond saw. This is especially true as the slicing cycle approaches completion. Severe damage will cause the
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`wafer to break away prematurely. It is in this area that the mounting material plays an important role by giving
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`the sawn wafer structural support. As previously mentioned, when the ingot is abraded to improve the adhesion
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`of the mounting material, the damaged region is subject to greater damage during slicing.
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`It is a common notion that between the two orientations (100) and (111), the (100) silicon is more easily chipped
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`and broken than (111). The author has found that any difference in physical strength between the two orientations
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`is of little significance in producing good polished wafers. What is more significant is how the silicon wafers
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`were processed. Grossly damaged regions will contribute to breakage regardless of the orientation.
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`The etching of sawn silicon wafers before any further processing is highly desirable. The advantages are:
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`3.4 Etching
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`1.
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`It removes surface damage.
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`2 .
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`It facilitates the inspection for peripheral defects.
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`3.
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`It removes small silicon particles and residual sawdust which may lead to scratches during polishing.
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`4.
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`It reduces the propagation of saw damage deeper into the wafer when abrasive lapping is required.
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`5.
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`It generates a clean, smooth surface.
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`6.
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`It decreases the polishing time required to remove the damaged layer.
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`7.
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`It facilitates the cleaning of the final polished wafer.
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`3.5 Lapping
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`On occasion silicon wafers are lapped to improve flatness, parallelism, surface finish or to remove saw
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`marks or to reduce thickness. Some of the variables in the lapping operation are type of machine (planetary, co
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`planar), abrasive size (2–25 micron), type of abrasive (diamond, silicon carbide, aluminum oxide, garnet),
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`type of vehicle (oil, water), type of lapping plate (steel, glass), pressure, and previous history of the silicon
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`wafers. These variables obviously affect the nature of damage generated.
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`414
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`7
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`

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`In planetary lapping the wafer moves freely within the boundary of the cut-out in the thin metal carrier. Un
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`less the cut-out is just slightly larger than the diameter of the wafer, the periphery of the wafer strikes against
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`the metal carrier and create numerous chips.
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`In co-planar lapping the wafers are normally waxed to a plano, circular disk giving greater protection to the
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`wafer. However, the wafers can easily be damaged if the disk is handled too roughly while positioning the disk
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`onto the lapping plate.
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`There is always the possibility of imbedding abrasive particles into the silicon; consequently, the abrasive
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`lapping process should be eliminated if at all possible.
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`The polishing of silicon is accomplished by various methods:
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`3.6 Polishing
`
`A)
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`abrasives
`
`B)
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`abrasives and chemicals reacting simultaneously and
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`C)
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`chemicals.
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`In all three cases, the polishing media is administered to the silicon mechanically. The fourth method, D, is a
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`chemical reaction not involving mechanical action such as slices immersed in a liquid etch. The term "Mechani
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`cal-Chemical polishing" is misleading because the word "mechanical" may refer to the machine or the abrasive.
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`Sub-micron diamond or aluminum oxide is an example of Method A because the silicon is abraded from the
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`surface. Gross damage results by this method as evidenced by the scratch density observed after the surface
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`has been lightly etched.
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`Zirconium oxide is commercially available suspended in an aqueous chemical solution. Since silicon is re
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`moved by the abrasive action of the zirconium oxide as well as the chemical action of the solution, this is an
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`example of Method B. The degree of damage resulting from this method depends largely upon the actual pro
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`cessing technique but is considerably less than Method A.
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`The role played by colloidal silicon dioxide in an aqueous system is not fully understood, but it can be con
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`sidered an example of Method C because the silicon dioxide particles appear to have little or no abrasive action
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`on the silicon. The polishing rates are low but good surfaces are obtained with a minimum damaged layer. An
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`other example of Method C involves the cupric ion. (12–13) The cupric ion, in a fluoride solution, displaces the
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`silicon atom; and the thin copper layer is subsequently removed by the mechanical action of an appropriate pad on
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`the polishing wheel. Two advantages of the cupric ion process are the fast removal rate and damage-free surface.
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`Conventional acid etching and vapor etching are examples of Method D.
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`All of the previous abrasive and chemical processes are in preparation of the final polishing step which should
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`leave the silicon surface damage free. The ideal polishing method is one using only chemicals which will reveal
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`damage in the form of surface defects and blemishes. One such method is the cupric-ion process which produces
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`a polished surface only after all of the damaged layer has been removed. Microcracks associated with peripheral
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`indents or conchoidal fractures are easily revealed with this polishing method because the chemical activity is
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`greater in these damaged areas. In contrast when abrasive or abrasive-chemical polishing methods are used, the
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`microcracks may not be optically visible. The peripheral defects also act as sites to harbor abrasive particles
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`which may be released during the polishing cycle and cause surface scratches.
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`4. Wafer Handling
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`During the various shaping operations, the wafers are subjected to many cleaning and etching steps with sub
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`sequent turbulent water rising. Proper baskets or other fixtures should be chosen to prevent the wafer edges from
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`coming into sharp contact with hard surfaces such as glass or metal. The contact may be severe enough to cause
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`peripheral damage.
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`415
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`8
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`

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`5. Summary
`
`In summary the presence of peripheral damage in a polished silicon wafer can be related to wafer breakage
`
`during device processing. Surface damage can be related to an irregular surface obtained in an epitaxial growth
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`process which in turn affects the quality of photo masking. Surface damage may also lead to irregular diffusion
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`and alloying depths causing electrical shorts and high leakage currents.
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`Abrasive shaping operations should be controlled so as to minimize both surface and peripheral damage and
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`this damage should be chemically removed before any further abrasive operations are performed.
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`Figure 2 shows the many processing routes that can be taken to prepare silicon surfaces for devices.
`
`416
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`9
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`

`
`6. References
`
`(1)
`
`Pugh, E. N. and Samuels, L. E., A Metallograph
`
`(7)
`
`Pugh, E.N. and Samuels, L. E., Damaged Layers
`
`ic Investigation of the Damaged Layer in Abraded
`
`in Abraded Silicon Surfaces, J. Electrochem. Soc.,
`
`Germanium Surfaces, J. Electrochem. Soc., 108,
`
`111, 1429 (1964).
`
`1043 (1961).
`
`(2)
`
`Sticker, R. and Booker, G.R., Nature of the
`
`Two Different Techniques to Determine the Depth
`
`Damaged Layer on Abraded Silicon Specimens,
`
`of Damage, Electrochem. Tech., 4, 399 (1966).
`
`(8)
`
`Stickler, R. and Faust, J.W. Jr., Comparison of
`
`J. Electrochem. Soc., 109, 743 (1962).
`
`(3)
`
`Pugh, E. N. and Samuels, L. E., Etching of
`
`mond-Sawing Damage to Germanium and Silicon,
`
`Abraded Germanium Surfaces with CP-4 Reagent,
`
`J. Electrochem. Soc., 116, 893 (1969).
`
`(9)
`
`Meek, R. L. and Huffstutler, M. C. Jr., ID-Dia
`
`J. Electrochem. Soc., 109, 409 (1962).
`
`(10)
`
`Whitten, W. N. Jr., Heitz, A. J. and McNamara,
`
`(4)
`
`Stickler, R. and Booker, G.R., Transmission
`
`J. E., Depth of Work Damage Resulting From
`
`Electron Microscope Investigation of Removal of
`
`Shaping Operations on Silicon, E. C. S. Meeting,
`
`Mechanical Polishing Damage on Si and Ge by
`
`Washington, D.C., Oct. 1964, Abst. 162.
`
`Chemical Polishing, J. Electrochem. Soc., 111,
`
`485 (1964).
`
`(11)
`
`Fairchild Semiconductor, 5th Quarterly Report,
`
`(5)
`
`Maruyama, S. and Okada, O., Crow Track Form
`
`tronics Material Agency, Contract No. DA-36-039–
`
`Section III, Task 2, Exhibit I, U.S. Army Elec
`
`ed by Mechanical Force on Silicon Crystal Wafer,
`
`SC 86726 (1963).
`
`Japan. J. Appl. , Phys. , 3, 300 (1964).
`
`(6)
`
`Faust, J.W. Jr., Factors That Influence the
`
`cal Polishing, Electrochem, Tech., 6, 155 (1968).
`
`Damaged Layer Caused by Abrasion on Si and Ge.,
`
`Electrochem. Tech., 2, 339 (1964).
`
`(13)
`
`Mendel, E. and Yang, K., Polishing of Silicon by
`
`(12)
`
`Regh, J. and Silvey, G.A., Silicon Planar Chemi
`
`the Cupric Ion Process, Proc. IEEE, 57, 1476
`
`(1969).
`
`417
`
`10
`
`

`
`A Surface
`
`<
`
`B Surface
`
`Fig. 1.
`
`Identification
`
`of the two sawn
`
`surfaces.
`
`Fig. 2.
`
`Processing
`
`W
`
`routes for the
`
`preparation of
`
`Slice
`
`silicon sub
`
`StrateS.
`
`Centerless
`
`Grind
`
`~
`
`Etch
`
`Y
`
`Orientation
`
`Flat >
`
`|
`
`Etch
`
`Etch
`
`7-
`
`Lap
`
`>"
`
`Etch
`
`*
`
`Polish
`
`418
`
`11