PCT
`WORLD INTELLECfUAL PROPERTY ORGANIZATION
`International Bureau
`INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`WO 96/11440
`
`( 11) International PubUcatlon Number :
`
`(51) International Patent Classification 6 :
`G06F 12/16
`
`Al
`
`(43) International Publication Date:
`
`18 April 1996 (18.04.96)
`
`(21) International Application Nwnber:
`
`PCTIUS95112933
`
`(22) International Filing Date:
`
`6 October 1995 (06.10.95)
`
`(81) Designated States: AU, CA, CN, JP, KR, MX. European
`pacem (AT, 8E, C H, DE. DK, ES. FR, GH. GK, l.t::. IT.
`LU, MC. NL, PT. SE).
`
`(30) Priority Data:
`08/319,231
`
`6 October 1994 (06.10.94)
`
`us
`
`(71) Applicant: VIRC, INC. [US!US]; 4910 Keller Springs Road,
`Dallas, TX 75248 (US).
`
`(72) Inventor : WHAI. Lim; 1120 Galloway Street, Pacific Pal·
`isades, CA 90272 (US).
`
`(74) Agent: HOWISON, Gregory, M.; Thompson & Howison,
`L.L.P., Suite 995, 12225 Greenville Avenue, Dallas, TX
`75243 (US).
`
`Published
`With intunatioMI search report.
`Before the upiration of the tir~U limit for amending the
`claims and 10 bt republished in the event of the rueipt of
`amendments.
`
`(54) T iUc; SHARED MEMORY SYSTEM
`
`(57) Abstract
`
`A sharol memory system (10) interfaces a shared memory bus (I 4) and EISA processor bus (20). The shared memory system (10)
`has an associated arbitration logic circuit (78) that services bus requests from each of the memory interfaces (16). In one of 2 arbitration
`modes, the shared memory system (10) allows a bus request from one of the memory interfaces (16) to transfer one byte of data, after
`which its priority is lowered and it relinquishes the bus to another one of the memory interfaces (16). This allows a byte-by-byte transfer
`without allowing any memory interface (16) to seize the bus. In another mode, each of the memory interfaces (16) is allowed to seize the
`bus to continuously ttansfer data with a priority system implemented to allow a hieher priority one to seize the bus away from a lower
`priority one.
`
`Page 1 of 34 ·
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`

`
`FOR THE PURPOSES OF INFORMATION ONLY
`
`Codes used to identify States party to the PCT on the front pag~ of pamphlets publishing international
`applications under the Per.
`
`AT
`AU
`BB
`BE
`BF
`BG
`BJ
`BR
`BY
`CA
`CF
`CG
`CH
`Cl
`CM
`CN
`cs
`cz
`DE
`DK
`ES
`Fl
`FR
`GA
`
`Austria
`Aualnlia
`Barbados
`Betaium
`Blrl:ina Fuo
`BuJcaria
`Benin
`Brazil
`Belarus
`CU1ada
`Cenlnl African Republic
`Con&o
`SwitutlaDd
`COle d"lvoirt
`Cameroon
`Olina
`Czcchollovaki!i
`Czcctl Republlc
`Gcmwly
`Deamart
`Spt.ia
`Fmlmd
`France
`Gabon
`
`Page 2 of 34
`
`GB
`G£
`GN
`GR
`HV
`IE
`IT
`1P
`K.£
`KC
`KP
`
`KR
`KZ
`Ll
`LK
`LU
`LV
`MC
`MD
`MC
`ML
`MN
`
`United Kinc6om
`GeorJia
`Guinea
`Greeu
`Huncuy
`Ireland
`Italy
`Japan
`Kl:nya
`Kyrzystan
`Dcmocllllk hople"' Republk
`of KO!U
`Republic of Kon:a
`KuakhsWJ
`Liechlerutein
`Sri Lanka
`Luxernbourc
`Lllvia
`Monaco
`Republlc of Moldova
`MadJCucar
`Mali
`Mongolii
`
`MR
`MW
`NE
`NL
`NO
`NZ.
`PL
`PT
`RO
`RU
`SD
`SE
`Sl
`SK
`SN
`TD
`TG
`TJ
`TT
`UA
`us
`uz
`VN
`
`Mauriwoia
`Malawi
`Nicer
`Netherlands
`Nor. .. y
`New Zealand
`Poland
`PartucaJ
`Rom &Ilia
`Ruuian Federation
`Sudan
`Sweden
`Slovenia
`Slovakia
`Senecal
`Chad
`Toco
`Tajikistan
`Trinidad and Tobqo
`Utraine
`Ullited Swes ol America
`Uzbekistan
`VietNam
`
`

`
`WO 96/11440
`
`PCTIUS95/12933
`
`SHARED MEMORY SYSTEM
`
`In large integrated computer networks, large storage systems are typically
`
`disposed in a server-based system with multiple peripheral systems allowed to operate
`
`independently and access the server main memory. One typical way for integrating such
`
`5
`
`a network is that uti lized in Local Area Networks (LANs). In these type of networks, a
`
`single broadband communication bus or media is provided through which all signals are
`
`passed. These LANs provide some type of protocol to prevent bus conflicts. In this
`
`manner. they provide an orderly method to allow the peripheral systems to "seize" the
`
`bus and access the server main memory. However, during the time that one of the
`
`I 0
`
`perjpheral systems has seized the bus, the other peripheral systems are denied access to
`
`the server main memory.
`
`In the early days of computers, this was a significant problem in computer centers
`
`in that a computer operator determined which program was loaded on the computer,
`
`which in turn determined how the computer resources were utilized. However, the
`
`15
`
`computer operator would assign priority to cenain programs such as those from a well(cid:173)
`
`known professor in a university system. In such an environment, it was quite common
`
`for priority to be assigned such that the computer could be tied up for an entire evening
`
`working on a problem for an individual with such a high priority. Students in the
`
`university-based system. of course. had the lowest priority and, therefore, their programs
`
`20 were run only when the system resources were available. The problem with this type of
`
`system was that an extremely small program that took virtually no time to run was
`
`required to sit on the shelf for anywhere from five to twenty hours waiting for the larger,
`
`higher priority progr.am to run. Although it would have been desirable to have the
`
`system operator instruct it to interrupt the higher priority program for a relatively sho11
`
`25
`
`lime to run a number of the fairly shon programs. this was not an available option. Even
`
`if this interruption may have extended the higher priority program for a fairly shol1 time,
`
`it would clearly provide a significantly higher level of service to the low priority small
`
`program users.
`
`Page 3 of 34
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`

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`wo 96/11440
`
`2
`
`PCTfUS95/l2933
`
`Present networks are seldom comprised of a single LAN system due to the fact
`
`that these networks are now distributed. For example, a single system at a given site
`
`utilizing a local network that operates over, for example, an Ethernet® cable, would
`
`have a relatively high data transfer rate on the local cable. The Ethernet® cables in those
`
`5
`
`systems provide a means to access remote sites via the telephone lines or other
`
`communication links. However, these communication links tend to have significantly
`
`slower access time. Even though they can be routed through a relatively high speed
`
`Ethernet® bus. they still must access and transmit instructions through the lower speed
`
`communication link. With the advent of multimedia, the need for much larger memories
`
`I 0
`
`that operate in a shared memory environment has increased. In the multimedia world,
`
`the primary purpose of the system is for data exchange. As such, the rate of data
`
`transfer from the server memory to multiple systems is imponant. However, regardless
`
`of the type of memory system or the type of data transfer performed, the system still
`
`must transfer the data stored in the server memory in a serial manner: that is, only one
`
`I 5 word of data can be accessed and transferred out of the memory (or written thereto) on
`
`any given instruction cycle associated with the memory. When multiple systems are
`
`attempting to access the given server memory, it is necessary to control the access to the
`
`server memory by the peripheral system in an orderly manner to ensure all peripheral
`
`systems are adequately served.
`
`20
`
`In typical systems that serve various communication links to allow those
`
`communication links to access the server meftlll>ry, separare coprocessors are typically
`f
`-r-
`
`provided to handle the communication link . ._.
`
`.
`
`This will therefor requires the server processor to control access to the server
`
`main memory. By requiring the server processor to serve access control limits the
`amount of data that can be trah~terred between the server and the communication
`
`25
`
`coprocessor, thus to the per p
`
`aJ.
`
`Page 4 of 34
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`

`
`W096/11440
`
`PCT/US95f12933
`
`SUMMARY OF THE INVENTION
`
`3
`
`The present invention, disclosed and claimed herein, comprises a shared memory
`
`system that includes a centrally located memory. The shared memory has a plurality of
`
`storage locations, each for storing data of a finite data size as a block of data. The block
`
`5
`
`of data is accessible by an address associated with the storage location of the block of
`
`data for storage of data therein or retrieval of data therefrom. The centrally located
`
`memory is controlled by a memory access control device. A plurality of peripheral
`
`devices are disposed remote to the shared memory system, each operable to access the
`
`centrally located memory and generate addresses for transmittal thereto to address a
`
`10
`
`desired memory location in the central locating memory system. The peripheral device is
`
`then allowed to transfer data thereto or retrieve data therefrom. A memory interface
`
`device is disposed between each of the peripheral devices and the centrally located
`
`memory system and is operable to control the transmittal of addresses from the
`
`associated peripheral device to the centrally located memory and transfer of data
`
`J 5
`
`therebetween. The memory interface device has a unique JD which is transmitted to the
`
`centrally located memory. Associated with the centrally located memory is an arbitration
`
`device that is operable to determine which of the peripheral devices is allowed to access
`
`the centrally located memory. The arbitration device operates in a block-by-block basis
`
`to allow each peripheral unit to only access the centrally located memory for a block of
`
`20
`
`data before relinquis hing access, wherein all requesting ones of the peripheral devices
`
`will have access to at least one block of data prior to any of the peripheral devices having
`
`access to the next block of data requested thereby.
`
`In an alternate embodiment of the present inven:ion, each block of data
`
`comprises a byte of data. Further, each memory interface device is given a priority bas
`
`25
`
`upon its unique ID. The arbitration device operates in a second mode to allow the
`
`highest priority one of the requesting peripheral devices to seize the bus away from any
`
`of the other peripheral devices to access all of the data requested thereby.
`
`Page 5 of 34
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`PCT/US95/12933
`
`4
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`For a more complete understanding of the present invention and the advantages
`
`thereof, reference is now made to the following description taken in conjunction with the
`
`accompanying Drawings in which:
`
`5
`
`FIGURE I illustrates an overall block diagram ofthe system;
`
`FIGURE 2 illustrates a perspective view of the physical configuration of the
`
`system;
`
`FIGUREs 3a and 3b illustrate views of the shared memory board and peripheral
`
`interface board. respectively;
`
`I 0
`
`FIGURE 4 illustrates a diagram of the shared memory system;
`
`FIGURE 5 illustrates a diagram ofthe shared memory interface;
`
`FIGURE Sa illustrates a memory map for the system of the present invention;
`
`FIGUREs 6 and 7 illustrate a timing diagram for the memory access;
`
`FIGURE 8 illustrates a flowchart for the operation of the system;
`
`15
`
`FIGURE 9 illustrates a prior art configuration for the overall system;
`
`FIGURE 10 illustrates the configuration for the system of the present invention;
`
`FIGURE II illustrates an alternate block diagram ofthe present invention; and
`
`FIGUREs 12a and 12b illustrate block diagrams of the CIM illustrated in
`
`F1.GtJRE,; .
`
`Page 6 of 34
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`

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`W096fll440
`
`PCTIUS95/12933
`
`5
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`Referring now to FIGURE I. there is illustrated an overall block diagram of the
`
`system ofthe present invention. At the heart ofthe system is a shared memory system
`
`l 0 which, as will be described hereinbelow, provides a global memory that is accessible
`
`5
`
`by a plurality of peripheral systems 12. The shared memory system 10. as will be
`
`described in more detail hereinbelow, is operable to serve each of the peripheral systems
`
`by receiving requests for data transfer, i.e., reading or writing of dat<. o the global
`
`memory in the shared memory system 10, and arbitrating the service such that all
`
`peripheral units I 2 are served in an even manner. Also, as will be described hereinbelow,
`
`1 0
`
`various priorities are given to the peripheral units 12. The shared memory system 10 is
`
`operable to interface with each of the peripheral memories 12 through a shared memory
`
`bus 14. Each ofthe shared memory buses 14 are connected to the various peripheral
`
`memories 12 through an interface 16. In addition. in the preferred embodiment a host
`
`processor 18 is provided This host processor I 8 is given the highest priority in the
`
`15
`
`system, and is operable to interface with the shared memory system 10 via an EISA bus
`
`20. The EISA host processor 18 functions similar to the peripheral units 12 and, in fact,
`
`is logically a peripheral system to the shared memory system 10. The host system 18
`
`does. however, have additional functions with respect to initializing the operation, etc.
`
`Referring now to FIGURE 2, there is illustrated a perspective view ofthe
`
`20
`
`physical configuration for the system of FIGURE I. An EISA host processor/bus board
`
`26 is provided whic·h is operable to contain the host processor 18 and the EISA bus 20.
`
`A plurality of EISA bus connectors 28 are provided, into which a plurality of peripheral
`
`interface boards 30 are inserted. Each ofthe peripheral interface boards is provided with
`
`an EISA interface connector 34, which is disposed on the lower edge ofthe peripheral
`
`25
`
`interface board 30 and inserted into EISA bus connector 28. However, this could be any
`
`type of computer bus architecture, such as ISA PCI, etc. A shared memory bus
`
`connector 36 is disposed on one end of the peripheral interface boards 30 and operable
`
`to be inserted into a common shared memory bus connector 38. In addition to the
`
`peripheral interface boards 30, a shared memory board 40 is disposed in one of the EISA
`
`30 memory bus connectors 38 on the EISA host processor/bus board 26. The shared
`Page 7 of 34
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`

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`wo 96/11440
`
`6
`
`PCTIUS95/12933
`
`memory 40 has a shared memory bus connector 36 associated therewith which is also
`
`operable to be interfaced with the common shared memory bus connector 38.
`
`Additionally. each of the peripheral interface boards 30 has associated therewith a
`
`peripheral interface connector 42. The peripheral interface connector 42 is operable to
`
`5
`
`interface with the peripheral device 12.
`
`The peripheral devices 12 can be of many different types. One example is an
`
`RS232 interface. which allows any type of peripheral device 12 that utilizes an RS232
`
`communication protocol to access the shared memory system 1 0. When the peripheral
`
`device 12 generates an address to access the shared memory, the peripheral interface
`
`10
`
`board 30 is operable to service this request and generate the instructions necessary t o the
`
`shared memory board 40 in order to access the memory disposed thereon, this also
`
`including any memory mapping function that may be required. It is noted that each of
`
`the peripheral interfaces 30 has a unique ID on the shared memory bus. The unique ID
`
`determines both priority and the [0 of the board and, hence. it determines how a shared
`
`15
`
`memory system I 0 services memory access requests from the peripheral interface boards
`
`30. As will be described hereinbelow. each ofthe peripheral interface boards 30 is
`
`operable to buffer memory requests from the peripheral device 12 until they are served
`
`by the shared memory system I 0.
`
`Referring now to FIGUREs 3a and 3b, there are illustrated general layouts for
`
`20
`
`boards themselves. In FIGURE 3a. the shared memory board 40 is illustrated depicti ng
`
`on one edge thereof the male shared memory bus connector 36 and on the lower edge
`
`thereof. the host EISA bus interface connector 28. In FIGURE 3b. the peripheral
`
`mnterface board 30 is illustrated. The peripheral interface board 30 is comprised of two
`
`sections, a shared memory interface section 46 and a Communication Interface Modu~e
`
`25
`
`(CIM) 48. The shared memory interface portion 46 is operable to interface with the
`
`shared memory bus 14 and the communication interface module 48. The communication
`
`interface module 48 determines the nature of the peripheral interface board 30. For
`
`example, if the peripheral interface board 30 ofFIGURE 3b were associated with an
`
`R$232 peripheral device 12. the communication interface module 48 would be operable
`
`30
`
`to convert between a parallel data system and a serial data system, generating the various
`
`transmission signals necessary to handle the protocol associated with an RS232 interface.
`Page 8 of 34
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`

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`
`PCTIUS95/129JJ
`
`7
`
`This allows data to be transmitted in an RS232 data format. Additionally, the CIM 48 is
`
`operable to receive data in RS232 format and convert it to a parallel word for
`
`transmission to the shared memory interface portion 46.
`
`The shared memory interface portion 46 contains various processors for allowing
`
`5
`
`the shared memory interface portion 46 to interface with the shared memory system 10
`
`via the shared memory bus 14. If the CIM 48 were associated with an ISDN function,
`
`for example, the CIM 48 would also provide the interface between a parallel bus an
`
`ISDN format. The functionality of a CIM 48 is quite similar to that associated with
`
`peripheral boards in an JSA bus architecture, i.e .. it allows for conversion between a
`
`10
`
`parallel bus and the communication identity. In the present embodiment, the EISA
`
`architecture utilizes a 32-bit bus structure.
`
`Referring now to FIGURE 4. there is illustrated a block diagram of the shared
`
`memory system I 0 . The shared memory system 10 has associated therewith a number of
`
`buses. At the heart of the shared memory system I 0 is a global random access memory
`
`1 5
`
`(RAM) 50. The global RAM 50 has an address input, a data input and a control input
`
`for receiving the Read/Write signal and various control signals for the Read operation
`
`such as the Column Address Strobe (CAS) and the Row Address Strobe (RAS). These
`
`are conventional signals. The global RAM 50 occupies its own memory space such that
`
`when it receives an address, this address will define one of the memory locations ofthe
`
`20
`
`global RAM 50. This. is conventional. The data input of the global RAM 50 is
`interfaced with a global RAM data (GRD) bus 52. and the address input of the global
`
`RAM 50 is interfaced with a global RAM address (GRA) address bus 54. The control
`
`input of the global RAM 50 is interfaced with a control bus 56. Data is not transferred
`
`directly from the GRD bus 52 nor addresses transferr~·d directly from the GRA bus 54 to
`
`25
`
`the connector 36 associated with the shared memol)
`
`Jard 40 which is then relayed to
`
`the other connectors 3 6 associated with the peripheral interface boards 30 via the
`
`connector 38. The connector 36 provides for control inputs. address inputs and data
`
`inputs. The address inputs and data inputs are interfaced with the shared memory bus
`
`14. The shared memory bus 14 is comprised of a global address bus 58 and a global data
`
`30
`
`bus 60. The global address bus 60 is interfaced through a transceiver 64 to the GRD bus
`
`52. The transceiver 64 allowing for the transfer of data from the global data bus 60 to
`Page 9 of 34
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`8
`
`PCTIUS9S/J 2933
`
`the GRD bus 52 and also from the GRD bus 52 to the global data bus 60. The global
`
`address bus 60 is connected through a buffer 66 to the GRA bus 54 to allow the
`
`peripheral syslems 12 to address the global RAM SO As will be described hereinbelow,
`
`the address space in the peripheral system is mapped into the memory space of the global
`
`5
`
`RAM SO, such that the global RAM 50 merely becomes an extension of the memory
`
`system at the peripheral system 12.
`
`The EISA data is provided on EISA data bus 68, which EISA data bus 68 is
`
`interfaced through a transceiver 70 to the GRD bus 52. The EISA address is input to an
`
`EISA address bus 72. The EISA address is input to an EISA address bus 72 and then
`
`JQ_
`
`input to GRA bus 54 through a buffer 74. The transceiver 70 and buffer 74. are a
`
`··gated devices'". as are the transceiver 64 and buffer 66. This allows the shared memory
`
`system I 0 to prevent bus contention and service or receive addresses from only the
`
`peripheral units 12 or the host processor 18. However, it should be understood that the
`
`host processor I 8 could merely have been defined as a peripheral device and interfaced
`
`15
`
`with a peripheral interface board 30 to the shared memory bus 14. Each ofthe
`
`peripheral systems 12 and EISA host processor 18 are interfaced with the control bus 56
`
`to allow control signals to be passed therebetween.
`
`The shared memory system 1 0 is controlled primarily by logic, with the processor
`
`function being distributed to the memory interfa<Ce 16. The shared memory system 10
`
`20
`
`provides the operation of arbitration and priority determination. In the arbitration
`
`function, the shared memory system I 0 determines via various bus signals generated by
`
`the shared memory interfaces I 6 to determine how to service these requests and which
`
`one is serviced at a given time. Additionally, each of the peripheral systems is ass[gned a
`
`priority such that the arbitration function is based upon priority. This will be described in
`
`25 much more detail hereinbelow The arbitration function is provided by an arbitratmon
`
`logic block 78 with the priority provided by a priority logic block 80. The various
`
`control functions for the global RAM 50 are provided by a RAM control block 82. The
`
`logic blocks 78 and 80 are provided by programmable logic devices (PLD). This function
`
`is provided by an integrated circuit such as the Intel N85C-220-80. a conventional PLD.
`
`Page 10 of 34
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`PCTIUS95/12933
`
`9
`
`Referring now to FIGURE 5, there is illustrated a block diagram ofthe peripheral
`
`interface board 30. The peripheral interface board 30, as described above, is operable to
`
`perform a slave function between the peripheral device 12 and shared memory system
`
`10. The peripheral interface board has at the heart thereof a central processing unit
`
`S
`
`(CPU) 96. In actuality. the CPU 96 is based on a 32-bit Extended Industry Standard
`
`Architecture (EISA) bus architecture and utilizes three Motorola fNP68302s. These are
`
`conventional chips and have onboard a 16 tv1Hz. 6800 processor core, which operates on
`
`a 6800 32-bit bus. The 32-bit bus has associated therewith an interrupt controller, a
`
`general purpose DMA control block and timers. The 32-bit bus is operable to interface
`
`I 0
`
`with ofT-chip memory and other control systems. providing both data and address in
`
`addition to control functions. The internal 6800 32-bit bus interfaces through various
`
`DMA channels with a RISC processor bus. Attached to the RJ SC processor bus is a
`
`16 MHz RISC communication processor. This processor is operable to interface with
`
`such things as ISDN support circuits, etc. Again. this is a conventional design and, in
`
`J 5
`
`general. the three processors that make up the CPU 96 are divided up such that one
`
`o perates as a master and the other two are slaves to distribute various processing
`
`functions. However. a single CPU could be utilized.
`
`The CPU 96 interfaces with an onboard processor bus 98, which processor bus is
`
`comprised of an address. a data and a control bus. The processor bus 98 is
`
`20
`
`interfaced with an input/output circuit 100, which is generally realized with a peripheral
`
`input/output device manufactured by Intel, Part No. 82C55A. This provides for a local
`
`input/output function that allows the processor bus 98 to communicate with the
`
`communication interface module 48, communication interface module 48 then operable
`
`to interface through the connector 42 with the peripheral unit 12. Local memory 102 is
`
`25
`
`also provided, which local memory o ccupies an address space on the processor bus 98_
`
`As will be described hereinbelow. the address space associated with local memory 102
`
`also occupies the address space of the peripheral unit 12. i.e., directly mapped thereto.
`
`In order for the processor bus 98 to interface with the s~ared mef"ory connector 36 and
`
`the shared memory system 10, the data porti1o'fo~t~processor b us 98 is interfaced with
`an intermediate data bus 106 via data buffers~ for mt~rri~data from the data
`
`30
`
`portion ofthe processor bus 98 to the intermediate data bus 106, and a data latch 110 for
`
`transferring data from the intermediate data bus I 06 to the data portion of the processor
`Page 11 of 34
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`10
`
`bus 98. A bi-directional transceiver I 14 is provided for connecting the intermediate data
`
`bus I 06 with a global data bus I 16 when the global data bus I 16 is interfaced with the
`
`shared memory connector 36. Similarly, a global address bus 1 I 8 is interfaced with the
`
`shared memory connector 36 for receiving addresses from the address portion ofthe
`
`5
`
`processor bus 98. However, as will be described in more detail hereinbelow, the address
`
`on the address portion of the process memory ofthe processor bus 98 is mapped or
`
`translated via an address translator block 120 to basically map one Megabyte portions of
`
`the address space to the address space in the shared memory system. This address
`
`translation is facilitated via a static random access memory (SRAM) of the type
`
`10
`
`T6TC6688J. This is a 32K memory for translating the eight megabyte portions to the
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`desired portions of the shared memory address space.
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`In addition to translating the address that is input from the peripheral unit 12 to
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`the peripheral interface board 30. the address that is generated from the processor bus 98
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`and relayed to the global address bus 1 I 8 also has control information associated
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`15
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`therewith. There are a number of higher order address bits that are not required for the
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`available memory space in the shared memory system I 0. These address bits are used as
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`control bits and are generated by a control bit generator I 24. Each unit has an ID tllat is
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`input via a DIP switch I 26 which allows the user t o set the ID for a given board.
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`Therefore, whenever an address is sent to the shared memory system 10, it not only
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`20
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`contains an address as translated into the memory space of the shared memory system I 0
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`but also contains the control bit. Various other controls are input along a global control
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`bus 130 that is connected to control portion of the processor bus 98 and also to the
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`shared memory connector 36.
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`Referring now to FIGURE Sa, there is illustrated a diagrammatic view of the
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`25
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`address space of the shared memory system and the peripheral interface board 30. A 32
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`Megabyte shared memory map 136 is provided. representing the memory map of the
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`shared memory system I 0, although this could be any size. In general, in the memory
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`space associated with the shared memory system I 0, the first location in the memory
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`map 136 is represented by the "0" location. The highest order bit would be the Hex
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`30
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`value for 32 Megabytes. By comparison. the peripheral interface board 30 has
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`associated therewith a 16 Megabyte map 138. This therefore allows up to 16 Megabytes
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`of memory to be associated with the peripheral interface board 30. This local memory
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`provides the ability for the peripheral interface board 30 to carry out multiple processing
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`fu nctions at the peripheral interface board level. These operations will be described in
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`some detail hereinbelow. However, it is important that when data is being transferred to
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`S
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`the peripheral interface board that there is no conflict between the two memory spaces.
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`Therefore, data that is being transmitted to the shared memory system l 0 must have a
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`different address above the physical eight Megabyte memory space. This is facilitated by
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`defining the address space for the shared memory system 10 relative to the input to the
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`peripheral interface board from the peripheral unit 12 as being at a higher address.
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`I 0
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`Therefore, the "0" location in the address space of the map 136 appears to be in a
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`different portion ofthe memory space of the peripheral interface board 30 above the
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`eight Megabyte memory space. This is represented by a virtual memory space 142.
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`When an address exists in this space, it is recognized and transmitted to the shared
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`memory system 10 after translation thereof to the address space of the shared memory
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`15
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`system 10. This allows a n address to be generated at t he peripheral unit 12 and then
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`transmitted directly to the shared memory system I 0.
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`Referring now to FIGUREs 6 and 7, there are illustrated timing diagrams for the
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`arbitration sequence for two modes of operation, a byte-by-byte arbitration mode and a
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`priority based bus seizing mode. The two modes are facilitated by a control bit referred
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`20
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`to as a "Fair" Bit that. when set to "I " causes the mode to operate in a byte-to-byte
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`mode and when set to "0", forces the system to operate in the priority based bus seizing
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`mode. FIGURE 6 illustrates the byte-to-byte mode and FIGURE 7 illustrates the
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`priority based bus seizing mode.
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`With further reference to FIGURE 6. there are illustrated five bus accessing
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`25
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`systems, the host system and fou r peripheral units 12. As described above, the host
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`processor 18 essentially operates as a peripheral unit with the exception that it is given
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`the highest priority, as will be described hereinbelow. W henever memory is accessed, it
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`typically requires four memory access cycles. The first operation is a bus request that is
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`sent from the peripheral interface board to the shared memory system 10. When this is
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`30
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`processed. a bus grant signal is then sent back from a shared memory system I 0 to the
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`peripheral interface board 30. On the next cycle, an address is transmitted to the
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`peripheral unit 12, followed by data in the next cycle. This is then repeated for the next
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`byte of information that is transmitted. As such, four cycles in the timing diagram of
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`FIGURE 6 are required for each byte of data that is transmitted. However, the
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`arbitration logic 78 operates to provide a pseudo-concurrence of data transfer. This
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`5
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`pseudo-concurrence is provided in that each peripheral board is allowed to seize the bus
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`for the purpose of transferring one byte of data. Therefore, the bus is relinquished to
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`another peripheral interface board 30 to allow it to transfer a byte of information and so
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`on. As such, this provides a relatively fair use for a fully loaded system such that a single
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`peripheral interface board 30 cannot seize and occupy the bus. In applications such as a
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`I 0 massive transfer of video or image information, it is necessary to allow all peripheral
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`systems to have as much access to the data as possible. This is true especially for such
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`systems as interactive applications. For example, when two systems are accessing the
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`same database such that two peripheral systems interact with each other, it is important
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`that one system be able to write to a memory location in one cycle, i.e., four
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`15
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`uninterruptable memory access cycles required for the memory system, and then another
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`peripheral system is able to access the data on the next data transfer cycle. This provides
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`for the maximum flexibility in an interactive system utilizing a shared memory. If, on the
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`other hand, one system were allowed to seize the bus, it would virtually isolate another
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`peripheral system from the memory while it has seized control of it. This, therefore,
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`20
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`detracts from the interactive nature of any type of shared memory application.
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`In the system illustrated in FIGURE 6, the peripheral unit P 3 initially generates a
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`bus request, followed by receipt of the bus grant and then transmission of address and
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`data. Upon the next cycle, three bus requests are then received, one from peripheral unit
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`P2, one from peripheral unit P4 and one from peripheral unit P5. However, due to the
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`25
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`priority nature of this system, the bus is released to peripheral unit P2 for transfer of data
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`therebetween. However, the bus requests for P4 and PS remain and upon the next data
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`transfer cycle, the bus is relinquished to P4 and. at the end of this cycle, a decision is
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`made as to the next peripheral unit to receive it. At the end of the data transfer cycle for
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`P4, the host generates a bus request. Although the system