Trials@uspto.gov
`571-272-7822
`
`
`
`Paper 11
`Entered: August 22, 2016
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`ASUSTEK COMPUTER, INC. and
`ASUS COMPUTER INTERNATIONAL,
`Petitioner,
`
`v.
`
`AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.,
`Patent Owner.
`____________
`
`Case IPR2016-00646
`Patent 5,870,087
`____________
`
`
`
`Before GLENN J. PERRY, PATRICK R. SCANLON, and
`J. JOHN LEE, Administrative Patent Judges.
`
`SCANLON, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
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`IPR2016-00646
`Patent 5,870,087
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`I. INTRODUCTION
`ASUSTeK Computer, Inc. and ASUS Computer International (collectively,
`“Petitioner”) filed a Petition (Paper 3, “Pet.”) requesting an inter partes review of
`claims 1, 5, 7–11, and 16 of U.S. Patent No. 5,870,087 (Ex. 1001, “the ’087
`patent”) pursuant to 35 U.S.C. §§ 311–319. Avago Technologies General IP
`(Singapore) Pte. Ltd., (“Patent Owner”) filed a Preliminary Response (Paper 6,
`“Prelim. Resp.”).
`We have jurisdiction under 35 U.S.C. § 314, which provides that inter partes
`review may not be instituted unless “the information presented in the petition
`. . . and any [preliminary] response . . . shows that there is a reasonable likelihood
`that the petitioner would prevail with respect to at least 1 of the claims challenged
`in the petition.” 35 U.S.C. § 314(a).
`Upon consideration of the Petition and the Preliminary Response, and for the
`reasons discussed below, we determine that Petitioner has established a reasonable
`likelihood of prevailing in showing the unpatentability of the challenged claims.
`Accordingly, we institute inter partes review of claims 1, 5, 7–11, and 16.
`
`II. BACKGROUND
`A. Related Matters
`Petitioner indicates that the ’087 patent is at issue in the following United
`States District Court proceedings: Avago Technologies General IP (Singapore)
`PTE Ltd. v. ASUSTeK Computer, Inc., Case No. 3:15-cv-04525 (N.D. Cal.) and
`Avago Technologies General IP (Singapore) PTE Ltd. v. ASUSTeK Computer Inc.,
`Case No. 3:16-cv-00451 (N.D. Cal.). Pet. 1. The ’087 patent is also asserted
`against entities unrelated to Petitioner in Avago Technologies General IP
`(Singapore) PTE Ltd. v. Acer Inc., Case No. 3:15-cv-05427 (N.D. Cal.). Id.
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`B. The ’087 patent
`The ’087 patent describes “an MPEG decoder system and method for video
`decoding or decompression which includes a unified memory for multiple
`functions.” Ex. 1001, 4:65–5:1. Figure 3, reproduced below, shows an
`embodiment of an MPEG decoder system.
`
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`Figure 3 is a block diagram illustrating an MPEG
`decoder system including a unified memory. Ex. 1001, 5:55−56.
`
`The system includes channel receiver 202 that receives a coded stream and
`provides the coded stream to transport and system controller block 204. Id. at 8:7–
`9. Transport and system controller block 204 includes transport logic 206, which
`demultiplexes the received MPEG encoded stream into a plurality of multimedia
`data streams, and system controller 208, which monitors and preferably controls
`the MPEG system. Id. at 8:10–13, 29–35. The system also includes MPEG
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`decoder 224 that “receives data from the transport and system controller block 204
`and operates to perform MPEG decoding to produce a decoded or decompressed
`signal.” Id. at 8:50–53. Transport and system controller block 204 couples to
`external memory 212 via memory controller 211 in MPEG decoder 224. Id. at
`8:38–40. The system “includes a single unified memory which stores code and
`data for the transport logic, system controller and MPEG decoder functions.” Id. at
`5:3–6.
`
`C. Illustrative Claim
`Of the challenged claims in the ’087 patent, claims 1, 10, and 16 are
`independent. Claim 1 is illustrative of the claims at issue:
`1.
`An MPEG decoder system which includes a single
`memory for use by transport, decode and system controller functions,
`comprising:
`a channel receiver for receiving and MPEG encoded stream;
`transport logic coupled to the channel receiver which
`demultiplexes one or more multimedia data streams from the encoded
`stream;
`a system controller coupled to the transport logic which
`controls operations within the MPEG decoder system;
`an MPEG decoder coupled to receive one or more multimedia
`data streams output from the transport logic, wherein the MPEG
`decoder operates to perform MPEG decoding on the multimedia data
`streams; and
`a memory coupled to the MPEG decoder, wherein the memory
`is used by the MPEG decoder during MPEG decoding operations,
`wherein the memory stores code and data useable by the system
`controller which enables the system controller to perform control
`functions within the MPEG decoder system, wherein the memory is
`used by the transport logic for demultiplexing operations;
`wherein the MPEG decoder is operable to access the memory
`during MPEG decoding operations;
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`wherein the transport logic is operable to access the memory to
`store and retrieve data during demultiplexing operations; and
`wherein the system controller is operable to access the memory
`to retrieve code and data during system control functions.
`Ex. 1001, 17:15–45.
`
`D. The Prior Art
`Petitioner relies on the following prior art:
`1. U.S. Patent No. 5,960,464, issued Sept. 28, 1999 (“Lam”)
`(Ex. 1004);
`2. U.S. Patent No. 5,898,695, issued Apr. 27, 1999 (“Fujii”)
`(Ex. 1005); and
`3. U.S. Patent No. 5,847,771, issued Dec. 8, 1998 (“Cloutier”)
`(Ex. 1006).
`
`E. The Asserted Grounds
`Petitioner challenges claims 1, 5, 7–11, and 16 of the ’087 patent on the
`following grounds:1
`References
`Lam
`
`Claims Challenged
`1, 5, 10, 11, and 16
`
`Basis
`§ 102(e)
`
`Fujii
`
`Fujii and Lam
`
`Lam and Cloutier
`
`Fujii and Cloutier
`
`Fujii, Lam, and Cloutier
`
`§ 102(e)
`
`1, 7, 10, 11, and 16
`
`§ 103
`
`§ 103
`
`§ 103
`
`§ 103
`
`1, 5, 7–11, and 16
`
`7–9
`
`7–9
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`7–9
`
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`1 Sections 3(b) and 3(c) of the Leahy-Smith America Invents Act (“AIA”)
`amended 35 U.S.C. § 102 and § 103, respectively. Pub. L. No. 112-29, 125 Stat.
`284, 285–287 (2011). Because the ’087 patent has a filing date before March 16,
`2013 (effective date of § 3), the pre-AIA versions of §§ 102, 103 apply in this
`proceeding. See id. § 3(n)(1), 125 Stat. at 293.
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`III. ANALYSIS
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are interpreted
`according to their broadest reasonable construction in light of the specification of
`the patent in which they appear. 37 C.F.R. § 42.100(b); see also Cuozzo Speed
`Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016) (upholding the use of the
`broadest reasonable interpretation standard). Consistent with the broadest
`reasonable interpretation, claim terms are presumed to have their ordinary and
`customary meaning as understood by a person of ordinary skill in the art in the
`context of the entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007). Furthermore, only those terms that are in controversy need
`to be construed, and only to the extent necessary to resolve the controversy. Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`For purposes of this Decision, we find it necessary to construe only the term
`“demultiplexes [or demultiplexing] one or more multimedia data streams,” as
`recited in independent claims 1, 10, and 16. Petitioner argues that the claims recite
`receiving an encoded stream and then require demultiplexing the stream, which
`suggests that the stream is received in a multiplexed form. Pet. 10–11. Petitioner
`also argues that one of ordinary skill in the art would understand demultiplexing to
`require separating the stream. Id. at 11. Based on these arguments, Petitioner
`proposes that this term should be construed as “separate the multiplexed encoded
`stream into one or more individual streams.” Id. Patent Owner argues that a
`formal construction of this term is not necessary, but does not object to using
`Petitioner’s proposed construction for the purposes of these proceedings only. We
`find Petitioner’s proposed construction to be supported by the evidence currently
`of record and adopt it for this Decision.
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`B. Alleged Procedural Defect
`As an initial matter, Patent Owner argues against institution because the
`Petition “omits any legal analysis of the standards” that must be met for Petitioner
`to prove its asserted grounds of unpatentability. Prelim. Resp. 15. Patent Owner
`argues that Petitioner’s expert makes unsupported, passing references to the legal
`standards that are “insufficient under 37 C.F.R. § 42.22(a), which requires that a
`petition provide ‘[a] full statement of the reasons for the relief requested, including
`a detailed explanation of the significance of the evidence including material facts,
`and the governing law, rules, and precedent.’” Id. at 16 (citing Ex. 1003 ¶¶ 20–
`22).
`
`We disagree. Petitioner identifies various prior art references under 35
`U.S.C. § 102, explains how it believes the claims should be interpreted, identifies
`its challenges as based on anticipation under 35 U.S.C. § 102(e) and obviousness
`under 35 U.S.C. § 103(a), and explains why it believes the claims are anticipated
`and/or would have been obvious based on the combined teachings of the
`references. See Pet. 2–3, 13–60. For these reasons, we determine that the Petition
`satisfies the requirements of 37 C.F.R. §§ 42.22(a) and 42.104(b). Thus, Patent
`Owner’s argument based on purported procedural deficiencies in the Petition is
`unpersuasive and does not present a sufficient reason to deny institution.
`C. Asserted Anticipation by Lam
`Petitioner challenges claims 1, 5, 10, 11, and 16 as anticipated under
`35 U.S.C. § 102(e) by Lam. Pet. 2, 12–21. To support this assertion, Petitioner
`relies on the Declaration of Richard Kramer under 37 C.F.R. § 1.68 (Ex. 1003).
`1. Overview of Lam
`Lam discloses a computer system including computer 102 comprising
`central processing unit (CPU) 104, main memory 106, and memory controller 108.
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`Ex. 1004, 4:9–15, Fig. 1. Display device 110 displays output produced by
`computer 102 and DVD/CD-ROM player 112, which is coupled to computer 102
`and plays back video images from DVD/CD-ROM disk 113. Id. at 4:18–22, Fig.
`1. Also coupled to computer 102 is MPEG2 2 decoder 114, which “decodes the
`compressed video images from the DVD CD-ROM player 112 to reconstruct the
`original, uncompressed video images so that they can be displayed on [display
`device] 110.” Id. at 4:30–34, Fig. 1.
`MPEG 2 decoder 114 includes microcontroller 120, having memory
`management unit (MMU) 122, and direct memory access (DMA) engine 124,
`which allows microcontroller 120 to access main memory 106 without employing
`CPU 104. Id. at 4:43–49, Fig. 2. Video decoding circuit 126 and audio decoding
`circuit 128 are coupled to microcontroller 120 for decoding video and audio
`signals, respectfully. Id. at 4:55–5:3, Fig. 2. Optional memory 129 can be coupled
`to microcontroller 120 to provide storage for a lookup table or memory map. Id. at
`5:8–10, Fig. 2. Alternatively, optional memory 129 can be omitted, in which case
`either memory management unit 122 is programmed to perform memory mapping
`to addresses in main memory 106 or a lookup table is stored in main memory 106.
`Id. at 8:15–31.
`Figure 3 of Lam, reproduced below, depicts the software elements employed
`by Lam’s computer system. Id. at 4:3–4.
`
`
`
`2 MPEG is an acronym for Motion Picture Expert Group, a technique for encoding
`and decoding video images. Ex. 1004, 1:46–49.
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`Figure 3 is a block diagram of the software elements
`used by Lam’s computer system. Ex. 1004, 4:3−4.
`
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`The software elements include operating system 152, user interface 154, and
`DVD driver 156. Id. at 5:14–18, 5:28–29, Fig. 3. DVD driver 156 routes data to
`DVD information file manager 158 and video objects manager 159. Id. at 5:28–
`31, Fig. 3. “The DVD information file manager 158 continuously reads the video
`objects from the DVD CD-ROM disk 113 and sends the objects to the video
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`objects manager 159.” Id. at 5:56–59. Video objects manager 159 parses video
`objects into packets and routes the packets to video driver 160 and audio driver
`162. Id. at 6:9–12, 6:38–41, Fig. 3.
`2. Petitioner’s Contentions
`Petitioner provides, with support of its declarant, analysis purporting to
`show where each limitation recited in claims 1, 10, and 16 is disclosed in Lam.
`Pet. 12–19. In particular, Petitioner maps Lam’s DVD information file manager
`158 and video objects manager 159 to the transport logic limitations of claims 1
`and 16, and the demultiplexing limitation of claim 10. Id. at 14. According to
`Petitioner, the video stream sent from DVD information file manager 158 is
`“‘parse[d]’ into separate audio and video packets” by video objects manager 159,
`and a person having ordinary skill in the art “would understand the term ‘parsing’
`in Lam to describe the demultiplexing (i.e., separating) of packets of the primary
`MPEG stream into streams of individual packets.” Id. (citing Ex. 1004, 5:55–64,
`6:1–16, 6:38–42, Ex. 1003 ¶¶ 67–68). Mr. Kramer testifies that “[o]ne of ordinary
`skill in the art would understand the term ‘parsing’ in Lam to describe
`demultiplexing (i.e., separating) of packets of the primary MPEG stream into
`streams of individual packets” because Cloutier (a reference relied on by Petitioner
`in other asserted grounds of unpatentability) “uses the same term ‘parse’ to
`describe the demultiplexing of packets of the primary MPEG stream.” Ex. 1003
`¶ 69 (citing Ex. 1006, 13:28–36).
`Petitioner also argues, “Lam discloses that the transport logic uses and
`accesses the main memory to store and retrieve data during demultiplexing.” Pet.
`18 (citing Ex. 1003 ¶ 69). Specifically, citing Lam’s disclosure that “[t]he
`microcontroller 120 then accesses the appropriate portion in the main memory 106,
`to write data to, and read data from, the main memory as requested by the video
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`decoding circuit 126 or audio decoding circuit 128,” Petitioner argues that an
`ordinarily skilled artisan “would understand from Lam that in order to read
`separate audio and video data from the main memory, the data was first
`demultiplexed and stored in the main memory during the parsing/demultiplexing
`operation performed by the video objects manager 159.” Id. at 18–19 (citing Ex.
`1004, 8:35–44; Ex. 1003 ¶ 69).
`3. Patent Owner’s Contentions
`Patent Owner argues that “there is no disclosure in Lam that the alleged
`transport logic has any access to memory during demultiplexing operations, much
`less that it stores and retrieves data during demultiplexing operations.” Prelim.
`Resp. 17. Patent Owner contends that “Lam discloses that ‘[t]he DVD information
`file manager 158 continuously reads the video objects from the DVD CD-ROM
`disk 113 and sends the objects to the video manager 159,’” and “the video objects
`manager 159 demultiplexes ‘the video objects into video, audio, sub-picture and
`other data packets [and] transfers the video and audio packets to the video and
`audio drivers 160 and 162, respectively.’” Id. at 18 (citing Ex. 1004, 5:56–59,
`6:38–42). In other words, according to Patent Owner,
`the video objects manager 159 receives data directly from the
`DVD information file manager 158 and immediately passes the
`demultiplexed data directly to the video and audio drives 160 and
`162. Nowhere in Lam – in the specification, the figures, or the
`claims – is there any disclosure or suggestion that the video
`manager 159 accesses any memory to store and retrieve data
`during demultiplexing operations.
`
`Id.
`
`4. Discussion
`We are not persuaded that Lam discloses accessing or using main memory
`106 during a demultiplexing operation. As discussed above, Petitioner contends
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`that Lam’s DVD information file manager 158 and video objects manager 159
`correspond to the transport logic recited in claims 1 and 16 and perform
`demultiplexing using a first unified memory as recited in claim 10. Pet. 14. To
`establish that this “transport logic” accesses memory 106 during the parsing or
`demultiplexing operation, Petitioner points to Lam’s disclosure that “[t]he
`microcontroller 120 then accesses the appropriate portion in the main memory 106,
`to write data to, and read data from, the main memory as requested by the video
`decoding circuit 126 or audio decoding circuit 128.” Id. at 18–19 (citing Ex. 1004,
`8:35–44; Ex. 1003 ¶ 69).
`The entire passage of Lam relied on by Petitioner reads as follows:
`Thereafter, the microcontroller 120 receives memory
`read/write requests from the video decoding circuit 126 and/or
`audio decoding circuit 128, and converts these requests to their
`appropriate page descriptor addresses based on the lookup table.
`Employing the DMA engine 124, the microcontroller 120 then
`accesses the appropriate portion in the main memory 106, to
`write data to, and read data from, the main memory as requested
`by the video decoding circuit 126 or audio decoding circuit 128.
`Ex. 1004, 8:35–44. This passage discusses read/write requests made to the main
`memory from the video and audio decoding circuits, not video objects manager
`159. As such, it appears to be describing a decoding operation, not the parsing
`operation carried out by video objects manager 159 discussed in column 6 of Lam.
`Petitioner fails to adequately explain how this passage discloses that Lam’s DVD
`information file manager 158 or video objects manager 159 (i.e., the asserted
`transport logic) accesses main memory 106. Instead, we agree with Patent Owner
`that Lam discloses that “the video objects manager 159 receives data directly from
`the DVD information file manager 158 and immediately passes the demultiplexed
`data directly to the video and audio drives 160 and 162.” See Prelim. Resp. 19; see
`also Ex. 1004, 5:56–59, 6:9–12 (disclosing that DVD information file manager 158
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`sends video objects continuously read from DVD CD-ROM disk 113 to video
`objects manager 159, and video objects manager 159 parses and routes packets to
`video driver 160 and audio driver 162).
`For the above reasons, we are not persuaded that Lam discloses using main
`memory 106 for demultiplexing one or more multimedia data streams, or that
`video objects manager 159 accesses main memory 106 to store and retrieve data
`during demultiplexing operations. Accordingly, we find that the Petition does not
`establish a reasonable likelihood that independent claims 1, 10, and 16, and claims
`5 and 11 depending from claims 1 and 10, respectively, are anticipated by Lam.
`D. Asserted Obviousness Based on Lam and Cloutier
`Petitioner challenges claims 7–9 under 35 U.S.C. § 103(a) as unpatentable
`over Lam. Pet. 2, 44–49. Claims 7–9 depend directly or indirectly from claim 1.
`Ex. 1001, 18:1, 18:7, 18:11. For this asserted ground, Petitioner contends that
`“Lam discloses the elements of claim 1” for the reasons discussed in the ground
`based on anticipation by Lam. Pet. 44.
`Patent Owner argues that Lam fails to disclose all the elements of claim 1,
`and that Petitioner does not allege that Cloutier remedies the deficiency of Lam.
`Prelim. Resp. 29. We agree with Patent Owner. As discussed above, we are not
`persuaded that Lam discloses a transport logic that accesses a memory to store and
`retrieve data during demultiplexing operations as required by claim 1. See supra
`Section III.C.4. Accordingly, we find that the Petition does not establish a
`reasonable likelihood that claims 7–9 are unpatentable over the combination of
`Lam and Cloutier.
`
`E. Asserted Anticipation by Fujii
`Petitioner challenges claims 1, 7, 10, 11, and 16 as anticipated under
`35 U.S.C. § 102(e) by Fujii. Pet. 2, 21–32.
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`1. Overview of Fujii
`Fujii relates to “[a]n apparatus for filtering TS packets3 multiplexed with a
`plurality of programs and sending the filtered packets to decoders.” Ex. 1005,
`Abstract (footnote added). Figure 11 of Fujii, reproduced below, shows one
`embodiment of such an apparatus. Id. at 5:32–33.
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`Figure 11 is a block diagram showing an
`embodiment of Fujii’s system. Ex. 1005, 5:32−33.
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`The system of Figure 11 includes tuner 1 that selects from a channel
`transmitted from a communications medium and supplies the selected channel data
`to demodulator 2. Id. at 6:2–5, 9:12–14, Fig. 11. The system also includes
`microprocessor 12 and random access memory (RAM) 7 that communicate via a
`data bus. Id. at Fig. 11. The output of demodulator 2 is supplied to program
`
`3 “TS packets” refers to transport stream packets. Ex. 1005, 1:36.
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`packet filter 15, which derives selected packets from the transmitted TS packets
`and supplies the filtered packets to interface unit 14. Id. at 9:16–19, Fig. 11.
`Relevant packets are transferred from interface unit 14 to packet landing buffer 71
`in RAM 7. Id. at 9:23–25, Fig. 11. Video decoder 8 and audio decoder 10 are
`provided for decoding video and audio data. Id. at 2:43–46.
`2. Petitioner’s Contentions
`a. Independent claims 1, 10, and 16
`Petitioner provides, with support of its declarant, analysis purporting to
`show where each limitation recited in claims 1, 10, and 16 is disclosed in Fujii.
`Pet. 21–29. In particular, Petitioner argues that “Fujii discloses an MPEG decoder
`system that includes a single RAM for use by transport, decode, and system
`controller functions.” Id. at 21 (citing Ex. 1003 ¶¶ 86–88). Petitioner asserts that
`Fujii’s tuner 1 is a channel receiver that receives an MPEG encoded stream. Id. at
`22 (citing Ex. 1003 ¶ 89). Petitioner also asserts that Fujii’s program packet filter
`15 and interface unit 14 correspond to the claimed transport logic that
`demultiplexes TS packets, as evidenced by Fujii’s disclosure that “[t]he program
`packet filter 15 derives from transmitted TS packets a PSI packet and a TS packet
`containing an element of the user selected program (program #k), and supplies the
`filtered packets to the interface unit 14.” Id. at 23 (quoting Ex. 1005, 9:16–21;
`citing Ex. 1003 ¶ 90).
`In addition, Petitioner maps Fujii’s microprocessor 12 to the claimed system
`controller, video and audio decoders 8, 10 to the claimed MPEG decoder, and
`RAM 7 to the claimed memory. Id. at 24–25 (citing Ex. 1003 ¶¶ 95, 97, 98).
`According to Petitioner, Fujii discloses accessing and using the RAM during
`MPEG decoding operations, system control functions, and demultiplexing
`operations. Id. at 25–29. Regarding the decoding operations, Petitioner argues
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`that “Fujii discloses using the RAM as a packet landing buffer to convert bit rates
`as needed by the MPEG decoders to prevent the decode buffers from overflowing.”
`Id.at 26 (citing Ex. 1005, 2:53–60, 10:13–16, Fig. 11; Ex. 1003 ¶ 99). Petitioner
`further asserts that “Fujii also discloses the MPEG decoder using the RAM for
`synchronization during MPEG operations. Id. (citing Ex. 1005, Fig. 11; Ex. 1003
`¶ 100). Petitioner also argues that Fujii’s disclosure of “a RAM used by a CPU for
`the system control” discloses accessing the RAM during system control functions.
`Id. at 27–28 (citing Ex. 1005, 3:60–419; Ex. 1003 ¶ 96).
`Regarding accessing and using memory during demultiplexing operations,
`Petitioner argues that Figure 14 of Fujii shows that “the transport logic (program
`packet filter 15 and interface unit 14) stores and retrieves data from the RAM
`during demultiplexing operations.” Id. at 28–29 (citing Ex. 1003 ¶¶ 93–94). In
`particular, as evidence of this contention, Petitioner points to Fujii’s disclosure that
`“[t]he microprocessor 12 reads the PID data corresponding to the user selected
`program #k from the program map table in RAM 12 [sic] and sets it to the register
`123. The PID data is then supplied from the output port to the PID filter 152 [in
`program packet filter 15].” Id. at 29 (citing Ex. 1005, 10:1–5; Ex. 1003 ¶ 94).
`b. Dependent claims 7 and 11
`Claim 7 depends from claim 1 and recites that the “memory includes a video
`frame portion for storing video frames, a system controller portion for storing code
`and data executable by the system controller, and a transport buffer portion for
`storing data used by the transport logic.” Ex. 1001, 18:1–6. Petitioner argues that
`“Fujii expressly discloses the RAM depicted in Figure 11 as including a system
`controller portion for storing code and data (system control program + data 72),
`and a transport buffer portion (packet landing buffer 71).” Pet. 30 (citing Ex.
`1005, Fig. 11; Ex. 1003 ¶ 102). Petitioner further argues that Fujii discloses a
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`video frame portion for storing video frames. Id. (citing Ex. 1005, 13:6–8; Ex.
`1003 ¶ 102).
`Claim 11 depends from claim 10 and recites
`wherein said demultiplexing one or more multimedia data
`streams from the encoded stream includes accessing multimedia data
`stream data from said first unified memory;
`wherein said performing MPEG decoding on the multimedia
`data streams includes accessing video frame data from said first
`unified memory; and
`wherein said controlling operations includes accessing code and
`data from said first unified memory.
`
`Ex. 1001, 18:35–44. Petitioner argues that Fujii discloses the first limitation
`because “PID filter 152 in program packet filter 15 receives data from the program
`map table in RAM 7 via register 123 when demultiplexing.” Pet. 31 (citing Ex.
`1005, 10:1–5, Fig. 14; Ex. 1003 ¶ 103). Regarding the second limitation,
`Petitioner argues Fujii discloses that “the video and audio decoders use packet
`transport buffers to convert the bit rates as needed ‘to supply element data to the
`video decoder 8 and audio decoder 10.’” Id. (quoting Ex. 1005, 2:53–60; citing
`Ex. 1003 ¶ 104). For the third limitation, Petitioner argues that Fujii’s disclosure
`of “a RAM used by a CPU for the system control” discloses accessing the RAM
`during system control functions. Id. at 27–28, 32 (citing Ex. 1005, 3:60–4:19; Ex.
`1003 ¶ 96).
`
`3. Patent Owner’s Contentions
`Patent Owner argues that Fujii “does not disclose that the transport logic
`retrieves data from the memory during demultiplexing operations.” Prelim. Resp.
`20. According to Patent Owner, the portion of Fujii cited by Petitioner as
`disclosing this limitation (i.e., Ex. 1005, 10:1–5) does not disclose what Petitioner
`contends it does. Id. at 21. Patent Owner argues that Fujii’s disclosure that “the
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`microprocessor 12 reads the PID data ‘from the program map table in RAM 12
`[sic] and sets it to register 123’ and the ‘PID data is then supplied from the output
`port to the PID filter 152’” indicates that “PID filter 152 retrieves information from
`a register (123) within the microprocessor, and not from the alleged memory
`(RAM 7).” Id. at 21–22 (citing Ex. 1005, 10:1–5).
`We do not find this argument persuasive. Figure 14 of Fujii, reproduced
`below, shows signal transfer among RAM 7, microprocessor 12, interface 14, and
`program packet filter 15. Ex. 1005, 5:38–39.
`
`Figure 14 is a diagram of RAM 7, microprocessor 12, interface
`14, and program packet filter 15. Ex. 1005, 5:38–39.
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`Program packet filter 15 includes TS header detector 151, which detects the
`header of an incoming TS packet, and PID4 filter 152. Id. at 9:39–41, Fig. 14. PID
`filter 152 uses PID data supplied by microprocessor 12 to supply the packets of the
`user selected program to transfer buffer 141 of interface unit 14. Id. at 9:47–50,
`Fig. 14. Data is transferred from transfer buffer 141 to RAM 7 and written in
`RAM 7 without passing through the register. Id. at 9:59–61, 9:65–67.
`Microprocessor 12 reads the PID data from the program map table in RAM 7 and
`sets this data to register 123 of the microprocessor. Id. at 10:1–4, Fig. 14. The
`PID data is fed from register 123 to PID filter 152. Id. at 10:4–5, Fig. 14. Using
`the PID data, program packet filter 15 filters (i.e., demultiplexes) the packets of the
`user selected program and also performs a clock recovery process. Id. at 10:6–8.
`In other words, PID filter 152 of program packet filter 15 retrieves PID data from
`RAM 7 to perform the filtering or demultiplexing process. Although the PID data
`is obtained via register 123, the claim language does not require that the transport
`logic directly access the memory.
`Accordingly, at this stage of the proceeding and based on the record before
`us, we are persuaded that Fujii discloses a transport logic that stores and retrieves
`data from a memory during demultiplexing operations, as required by claims 1 and
`16, and using a first unified memory during demultiplexing operations, as required
`by claim 10.
`Patent Owner also argues that the same arguments Petitioner is raising with
`respect to Fujii “were expressly considered and rejected by the International Trade
`Commission (‘ITC’) as part of Investigation No. 337-TA-837.” Prelim. Resp. 22–
`23. Patent Owner asserts that, in its Initial Determination,
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`4 “PID” refers to packet ID. Ex. 1005, 1:62.
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`the ITC rejected the allegation that “Fujii discloses the use of
`RAM (including RAM and Program Memory) that is accessed
`by the Channel Demultiplexer (including the Program Packet
`Filter and Interface Unit) for demultiplexing of multiple
`programs such as video and audio data, and that the transport
`logic in fact does store and retrieve data during demultiplexing
`operations.”
`Id. at 23 (citing Ex. 2001, 40).5 Patent Owner further asserts that the ITC relied on
`the expert testimony of Dr. Scott Acton, a professor at the University of Virginia,
`in reaching its determination. Id. Specifically, Patent Owner notes that Dr. Acton
`testified, in Q&A 273, “[t]hat the demultiplexer of Fujii cannot retrieve data from
`the memory during demultiplexing operations is shown in FIG. 17 of Fujii.” Id.
`(quoting Ex. 2002, 29).6
`We are not persuaded by this argument. First, although we have taken the
`ITC’s Initial Determination into account, we make an independent determination
`of patentability of the challenged claims based on the evidence before us and the
`standards applicable to an inter partes review. In the ITC proceeding, the
`respondent was required to establish invalidity by clear and convincing evidence.
`Ex. 2001, 31. In contrast, inter partes review may be instituted if there is a
`reasonable likelihood that the petitioner would prevail with respect to at least one
`of the challenged claims. 35 U.S.C. § 314(a). The ITC proceeding also did not
`employ the broadest reasonable interpretation standard for claim construction that
`is applicable to an inter partes review. Ex. 2001, 17. For these reasons, the ITC’s
`Initial Determination is not determinative in this proceeding.
`
`
`5 When referencing Exhibit 2001, we refer to the pagination inserted by Patent
`Owner.
`6 When referencing Exhibit 2002, we refer to the pagination inserted by Patent
`Owner.
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`Second, Patent Owner’s reliance on the Rebuttal Witness Statement of Scott
`T. Acton, Ph.D. (Ex. 2002) from the ITC proceeding is not persuasive. In the brief
`discussion of Fujii, as the reference relates to the ’087 patent, Dr. Acton testified
`that the demultiplexer shown in Figure 17 of Fujii cannot retrieve data from a
`memory during demultiplexing operations. Ex. 2002, 40. However, this testimony
`does not address the embodiment depicted in Figure 11 of Fujii, which Petitioner