United States Patent [19]
`Ichioka et al.
`
`US005546013A
`[ii] Patent Number:
`[45] Date of Patent:
`
`5,546,013
`Aug. 13, 1996
`
`[54] ARRAY TESTER FOR DETERMINING
`CONTACT QUALITY AND LINE INTEGRITY
`IN A TFT/LCD
`
`[75]
`
`Inventors: Yoshikazu Ichioka, Fujisawa, Japan;
`Leslie C. Jenkins, Holmes, N.Y.;
`Shinichi Kimura, Sagamihara, Japan;
`Robert J. Polastre, Ossining, N.Y.;
`Ronald R. Troutman, Ridgefield,
`Conn.; Robert L. Wisnieff, Yorktown,
`N.Y.
`
`[73] Assignee: International Business Machines
`Corporation, Armonk, N.Y.
`
`[21] Appl. No.: 26,897
`Mar. 5, 1993
`[22] Filed:
`G06F 7/02
`[51] Int. CI.6
`[52] U.S. CI
`324/770; 324/158.1
`[58] Field of Search
`324/770, 73.1,
`324/765, 158.1; 250/310; 365/98, 100,
`87; 359/55, 57, 59; 371/25.1, 15.1, 22.1;
`364/481
`
`[56]
`
`4,175,253
`4,290,013
`4,342,959
`4,801,869
`4,819,038
`4,843,312
`
`References Cited
`U.S. PATENT DOCUMENTS
`11/1979 Pitegoff
`9/1981 Thiel
`8/1982 Skilling
`1/1989 Sprogis
`4/1989 Alt
`6/1989 Hartman et al.
`
`.. 324/754
`324/158.1
`324/158.1
`.. 324/765
`.. 324/765
`.. 250/310
`
`1/1990 Ringleb et al
`4,894,605
`7/1990 Kawaguchi et al.
`4,940,934
`5,057,775
`10/1991 Hall
`5,072,175
`12/1991 Marek
`5,113,134
`5/1992 Plus et al
`1/1993 Jenkins et al
`5,179,345
`12/1994 Suzuki et al
`5,377,030
`FOREIGN PATENT DOCUMENTS
`
`324/537
`324/770
`324/770
`324/537
`324/73.1
`324/658
`324/770
`
`Japan .
`5/1989
`1130132
`Japan .
`246726 10/1989
`9209900
`6/1992 WIPO .
`OTHER PUBLICATIONS
`
`L. C. Jenkins et al., "Functional testing of TFT/LCD array-
`s"IBM Journal of Research and Development vol. 36, No. 1,
`Jan. 1992 pp. 59-68.
`
`Primary Examiner—Vinh P. Nguyen
`Attorney, Agent, or Firm—David Aker
`
`ABSTRACT
`[57]
`An apparatus for testing for and classifying defects in a
`TFT/LCD array having gate lines and data lines. Devices are
`provided for activating cells of the array by applying gate
`pulses to the gate lines and pulses to the data lines. Devices
`are also provided for acquiring waveforms from data lines of
`the array. Additional devices sample the waveforms at
`selected points in time. A computer may be used to classify
`the waveforms to indicate whether defects are present and if
`present, the nature of the defects by comparing voltages of
`the waveform at the selected points in time.
`
`4 Claims, 10 Drawing Sheets
`
`TEST
`46 Z s ' - CONTROLLER
`50—^
`
`54
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`
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`
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`
`38
`
`18
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`28
`22 \ 20
`
`•26
`
`GATE
`LINE
`DRIVE
`UNIT
`
`42
`
`44
`
`DATA
`STORAGE
`
`r 5 6
`
`12
`
`10
`
`40
`
`24
`
`18
`
`\
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`16
`
`SUBSTRATE
`HOLDER
`14
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`DATA LINE
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`UNIT
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`68
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`66
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`FIG. 2
`
`iO
`
`

`
`U.S. Patent
`
`Aug. 13,1996
`
`Sheet 3 of 10
`
`5,546,013
`
`FIG. 3
`
`LOCATE POSITION OF OPEN ALONG DATA LINE
`
`24 i: ' !
`
`•TO MULTIPLEX SWITCH AND
`SENSE AMPLIFIERS
`r20
`
`G/L #1
`
`#2
`
`#3
`
`#4
`
`# 6
`
`GATE/LINE
`DRIVERS
`
`TO MULTIPLEX SWITCH AND
`SENSE AMPLIFIERS
`D/L #1 2 3 4 5 6 * ' '
`
`

`
`U.S. Patent
`
`Aug. 13, 1996
`
`Sheet 4 of 10
`
`5,546,013
`
`FIG. 4
`
`LOCATE POSITION OF OPEN ALONG GATE LINE
`
`24
`
`-Jm ^
`
`• 1
`
`^TO MULTIPLEX SWITCH AND
`^20
`SENSE AMPLIFIERS
`
`G/L #1
`
`# 2
`
`#3
`
`#4
`
`#5
`
`GATE/LINE
`DRIVERS
`D/L #1 2 3 4 5 6
`
`TO MULTIPLEX SWITCH AND
`SENSE AMPLIFIERS
`
`

`
`U.S. Patent
`
`Aug. 13, 1996
`
`Sheet 5 of 10
`
`5,546,013
`
`FIG. 5
`NORMAL
`
`FIG. 6
`NO GATE
`PROBE CONTACT
`
`FIG. 7
`BROKEN
`LINE
`
`FIG. 8
`RESISTIVE
`CROSSING
`
`FIG. 9
`SHORTED
`ADJACENT
`LINES
`
`\
`
`r
`
`T: A B C
`
`D
`
`E
`
`

`
`U.S. Patent
`
`Aug. 13, 1996
`
`Sheet 6 of 10
`
`5,546,013
`
`FIG. \0
`
`START
`
`70
`
`LINE.TEST 0
`TAKES DATA POINTS ALONG THE _J~
`LENGTH DF EACH GATE LINE
`
`72
`
`LOOKS FOR "NORMAL" GATE LINES
`AT THE TOP AND BOTTOM OF
`THE PANEL. REPORTS ON ALL
`GATE LINES
`
`DLINE_TEST ()
`USING THE TWO GOOD GATE LINES
`TAKES DATA ON EVERY DATA LINE.
`
`74
`
`76
`
`WAVESLG1.PAS
`CATAGDRIZES ALL THE DRAIN LINES
`
`78
`
`SCAN PANEL FDR
`CROSSING SHORTS _/• 80
`
`SCANS PANEL COLLECTING DATA ON
`INDIVIDUAL CELL CHARGE RETENTION
`
`82
`
`COLLECTS WAVEFORM
`
`I
`
`COLLECTS TFT
`CHARACTERIZATION CURVES
`
`84
`
`86
`
`END
`
`88
`
`

`
`U.S. Patent
`
`Aug. 13, 1996
`
`Sheet 7 of 10
`
`5,546,013
`
`ARRAY TESTER CDNTRDL SEQUENCE
`
`NDN-INTERLEAVE DPERATIDN
`
`INITIALIZE
`HARDWARE
`INTERFACE
`
`100
`
`CLEAR
`HANDSHAKING
`LATCH
`
`M02
`
`SET MODE
`120 = SCAN
`88 = SINGLE CELL
`
`--104
`
`CLEAR GATES
`SEND 1023
`TD TESTER
`DO GATESETO
`DO GATE ENDO
`
`SEND ALL
`PARAMETERS
`•UT TD TESTER
`
`I
`
`SET BUFFER TD
`0,0,0 (CLEAR
`BUFFER ADDRESS)
`
`108
`
`110
`
`TURN MPX DN,
`SET EVEN / DDD
`MPXERS
`
`^112
`
`114
`
`TEST SPECIFIC
`SET UP, IE.
`INCREMENT TCDNV.
`
`RUNTESL WAIT FDR"\
`116
`TEST CDMPLETED
`
`118
`
`FINISHED ?
`
`ND
`
`YES
`
`CALCULATE WHERE
`YOUR DATA IS
`IN THE BUFFER. '
`SET BUFFER TD 0,0,0
`
`120
`
`j 122
`SELECT EVEN OR
`•DD DATA BUFFER '
`
`READ DATA
`FROM BUFFER
`
`124
`
`FIG.U
`
`

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`
`THEN
`
`226
`
`224
`
`FOR EITHER LINE
`
`IF (A>E+DIFF8>
`
`7
`'NO GATES*
`
`'BROKEN LINE'
`222
`
`END
`
`210
`
`218
`
`DIFF8 = 800 COUNTS
`DIFF7 = 100 COUNTS
`DIFF6 = 30 COUNTS
`DIFF5 = 80 COUNTS
`DIFF4 = 60 COUNTS
`DIFF3 = 20 COUNTS
`DIFF2 = 70 COUNTS
`DIFF1 = 40 COUNTS
`
`'SHORTED ADJACENT LINES'
`
`ELSE
`
`THEN
`
`ELSE
`
`THEN
`
`220
`
`8<
`
`<:A<E+DIFF3) FDR BDTH LINES
`CC<D+DIFF3) 8. CD<E+DIFF3) &
`IF CA<B+DIFF3) & (B<C+DIFF3>
`
`ELSE
`
`FDR BOTH LINES
`
`IFCD+DIFF 4<E)
`214
`
`THEN
`
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`
`216
`
`208
`
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`
`ELSE
`
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`
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`
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`
`'NORMAL'
`206
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`
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`
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`
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`
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`
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`
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`
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`
`8, <A<(E+DIFF5» FDR BOTH LINES
`
`200
`
`BEGIN
`
`FIG. 12
`
`

`
`U.S. Patent
`
`Aug. 13,1996
`
`Sheet 9 of 10
`
`5,546,013
`
`Gl
`
`G2
`
`G3
`
`Gn
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`Th
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`
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`
`WRITE
`
`READ
`
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`
`FIG.13
`
`

`
`U.S. Patent
`
`Aug. 13,1996
`
`Sheet 10 of 10
`
`5,546,013
`
`FIG. M
`
`300
`
`INITIALIZE
`HARDWARE
`INTERFACE
`
`CLEAR
`HANDSHAKING,-302
`LATCH
`
`ARRAY TESTER CONTROL SEQUENCE
`INTERLEAVE DPERATION
`
`1
`
`READ A
`BLOCK OF CELLS *
`
`t 315
`
`FINISHED
`READING
`
`ND
`
`316
`
`YES
`
`304
`
`SET BUFFER TD 0,0,0^17
`
`SET MODE
`120 = SCAN
`88 = SINGLE CELL
`
`I
`
`CLEAR GATES
`SEND 1023
`TD TESTER
`DD GATESETC)
`DD GATE.ENDO
`
`/ 306
`
`SEND ALL
`PARAMETERS
`•UT TD TESTER
`
`308
`
`' '
`SET BUFFER TD
`0,0,0 (CLEAR
`BUFFER ADDRESS)
`
`310
`
`312
`•-r
`TURN MPX ON,
`SET EVEN / ODD -*
`MPXERS
`
`. r313
`WRITE A
`BLOCK OF CELLS
`
`314
`
`NO
`
`FINISHED
`WRITING
`7
`
`SELECT EVEN
`DATA BUFFER
`
`I
`
`READ DATA •
`FROM BUFFER
`
`318
`
`319
`
`320
`
`SET BUFFER TO 0,0,0
`
`I
`
`SELECT DDD,^322
`DATA BUFFER
`
`READ DATA '^*324
`FROM BUFFER
`
`FINISHED
`TESTING 1
`
`YES
`
`ND
`
`325
`
`326
`
`NO
`
`ALL
`MPX USED
`
`YES
`
`'
`
`'
`
`END
`
`

`
`5,546,013
`
`1
`ARRAY TESTER FOR DETERMINING
`CONTACT QUALITY AND LINE INTEGRITY
`IN A TFT/LCD
`
`CROSS REFERENCE TO RELATED
`APPLICATION
`
`This application is related to U.S. patent application Ser.
`No. 07/450,635 of Jenkins and Wisnieff filed on Dec. 13, 10
`1989, now U.S. Pat. No. 5,179,345 the entire disclosure of
`which is hereby incorporated by reference.
`
`TECHNICAL FIELD
`
`This invention relates to electrical testers. More particu­
`larly it relates to a method and apparatus for electrical testing
`of a thin film transistor liquid crystal array (TFT/LCD).
`
`BACKGROUND ART
`
`20
`
`2
`In accordance with the invention a TFT/LCD array is
`tested by applying drive pulses to a driven end of gate lines,
`observing the presence of a corresponding signature pulse
`on a first data line near the driven end and a second data line
`5 at the end opposite the driven end so as to indicate the gate
`line is continuous; testing successive gate lines in the same
`manner to determine the top most and bottom most continu­
`ous gate line; and evaluating integrity of all the data lines by
`using the top most and bottom most gate lines having
`.
`.
`integrity-
`The invention also contemplates using data concerning
`integrity of gate lines and data lines to isolate at least one of
`defective lines and defective contacts to said lines.
`In accordance with the invention a method for testing
`15 probe contact integrity to electrodes of a TFT/LCD array
`comprises the steps of providing an electrically conductive
`connection ring for the electrodes; providing an electrical
`connection between said connection ring and each of said
`electrodes; applying electrically conductive probe contacts
`to at least two of said electrodes; applying a voltage between
`said at least two probe contacts; and measuring the current
`between said at least two contacts to determine the quality
`The array tester described in U.S. Pat. No. 5,179,345
`of electrical continuity between said probe contacts and said
`provides a means for comprehensively testing every cell in
`electrodes. The electrical connection is made by a high
`a TFT/LCD array using only the array's edge connections. 25
`resistance element.
`The basic test performed by the array tester is to write charge
`The invention further contemplates a method for testing
`onto a cell (by properly biasing the gate and data lines), store
`for probe contact integrity to electrode connection regions of
`charge on the cell by biasing the gate off, read the remaining
`a TFT/LCD array having gate lines and data lines compris-
`_
`charge off of the cell by connecting a charge integrating
`...
`.
`.
`circuit to the data line and biasing the gate line on, and then 30 ^n2 l'ie stePs 0f: providing adjacent a row of said connection
`regions a conductive line crossing said electrodes, and insu­
`measure the charge that has been transferred to the charge
`lated therefrom; providing a small capacitance between said
`integrating circuit to determine the final value of charge.
`line and each of said electrodes; placing a conductive probe
`Electrically testing the charge arrays inherent to TFT/LC
`in contact with each of said connecting regions; successively
`displays at any stage prior to the attachment of line drivers
`applying a voltage pulse to each of said connection regions
`requires contacting a large number of pads (typically in the 35
`through said probe; and observing the presence of a signa­
`thousands). Contamination (such as residual photoresist,
`ture pulse on said line for each applied pulse to determine
`oxide films, etc.) and the substrate non-planarity can inter­
`quality of electrical connection between said probe and said
`fere with good electrical connection between the tester
`connection regions.
`probes and the array pads. To insure validity of the many
`The invention also encompasses a method for testing a
`tests that write charge to, and read charge from, selected 40
`TFT/LCD array having data lines and gate lines comprising
`pixels, it is necessary to determine whether the tester probes
`the steps of: applying a pulse to one of said gate lines:
`are actually making contact to the array pads.
`integrating a resulting signature pulse on successive ones of
`There are various mechanical ways to assure electrical
`said data lines to obtain an integrated wave form and
`contact to the pads. However, these require at least one of
`45 observing the integrated waveform to obtain information
`mechanical motion between the pads and the probes, the use
`concerning at least of a level of functionality of said TFT/
`of additional probes to determine the integrity of the elec­
`LCD and quality of contact to said lines.
`trical contact, or mechanical abrasion of the pads or gate
`lines. These procedures are expensive, time consuming and
`may themselves introduce possible sources of failure for the
`array under test. Thus, it is highly desirable that various 50
`electrical integrity checks can be made using only the probes
`normally required to contact the pads, and that these probes
`be used in the normal manner described in the above
`mentioned patent.
`
`FIG. 1 is a partial schematic/partial perspective view of an
`array tester system in accordance with the invention using
`the methods described herein.
`FIG. 2 is an enlarged, somewhat schematic plan view of
`55 a substrate containing a thin film transistor/liquid crystal
`display array.
`FIG. 3 illustrates a method for locating opens in data lines
`of the array of FIG. 2.
`It is an object of the present invention to provide a method
`FIG. 4 illustrates a method of locating opens in gate lines
`for determining contact quality to the pads in a TFT/LCD
`60 of the array of FIG. 2.
`array.
`FIG. 5 is an array tester waveform which is characteristic
`It is another object of the invention to provide a method
`of normal operation.
`for determining the line integrity of gate lines and/or data
`lines in a TFT/LCD array.
`FIG. 6 is an array tester waveform which is characteristic
`It is a further object of the invention to identify specific 65 0f 110 gatc contact,
`types of defects in a TFT/LCD array by evaluating electrical
`FIG. 7 is an array tester waveform which is characteristic
`waveforms obtained therefrom.
`of an open line.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`SUMMARY OF THE INVENTION
`
`

`
`5,546,013
`
`50
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`3
`4
`so as to provide a convenient location for making electrical
`FIG. 8 is an array tester waveform which is characteristic
`connection thereto. Each data line pad 22 and gate line pad
`of a resistive crossing defect.
`26 is electrically connected to connection ring 60 through an
`FIG. 9 is an array tester waveform which is characteristic
`electrically resistive element 64. Element 64 is preferably a
`of shorted adjacent lines.
`high resistance, such as a 1000 megohm thin film (silicon
`FIG. 10 is a generalized flow chart for the process of 5
`planar) resistor but may also be a pair of back to back diodes
`testing an array of the type shown in FIG. 2.
`or a thin film transistor with connections which cause it to
`FIG. 11 is a flow chart illustrating the control sequence for
`have the proper resistance. It will be understood by those
`the apparatus in FIG. 1.
`skilled in the art that when the substrate 10 is assembled with
`FIG. 12 is a flow chart useful in analyzing the wave forms J O a second substrate, spacers, liquid crystal material and a seal
`in FIG. S to FIG. 8 to determine whether a defect is present
`that the conductive connection ring 60 and resistive ele­
`and if so the nature of the defect.
`ments 64 may not be present. In other words, substrate 10
`may be cut so as to remove these elements.
`FIG. 13 is a generalized timing diagram indicative of
`operation using interleave timing.
`One method for checking probe contact to the array pads
`FIG. 14 is a flow chart similar to FIG. 11, for operation 15
`is to apply a DC voltage to a selected gate line or data line
`using interleave timing.
`probe and measure the current flowing in the connection ring
`60. A complete circuit is made with a probe which contacts
`pad 62. When the probe is making contact to the gate line or
`data line pad, one volt applied to the probe will result in
`20 approximately 1 nA of current flow in the connection ring.
`If the probe fails to make contact to the pad, negligible
`Referring to FIG. 1, a substrate 10 having formed thereon
`current (<1 pA) will flow.
`a TFT array 12 is supported on a substrate holder 14 having
`a upper planar surface 16 in a predetermined position by at
`A variation of this method, which eliminates the need for
`contacting shorting ring 60, is to measure the current flow
`least 3 alignment pins 18. Substrate 10 has a large number
`of data lines 20 for driving the TFT/LCD array. Each data 25 between each adjacent pair of probes. If both probe contacts
`are good, the resulting current is approximately half that
`line terminates in a data line electrode or data line pad 22.
`Also formed on substrate 10 are a large number of gate lines
`above since the current must now flow through two resistive
`24 each terminating in a gate line electrode or a gate line pad
`elements 64 to be detected. If either probe is not contacting
`the pad, the current is again negligible. By comparing
`26.
`Each data line pad 22 is contacted by an electrically 30 currents when consecutive probe pairs are measured, a bad
`contact (or contacts) is easily located. For example, if only
`conductive testing probe 28 extending from data line probe
`two adjacent pairs exhibit negligible current, the probe
`holding fixture 30. A cable 32 connects each test probe 28 to
`common to both pairs is isolated as a bad contact, and, in
`a driving circuit within a data line drive/sense unit 34. Each
`general, n+1 consecutive bad pairs isolates n consecutive
`gate line pad 26 is contacted by an electrically conductive
`bad contacts. However, this variation cannot detect a single
`probe 38 extending from a fixture 40. A cable 42 has wiring 35
`good probe contact sandwiched between two bad ones. This
`for connecting each probe 38 to a responsive gate line driver
`method will not detect poor contact between a gate line pad
`in a gate line unit 44. The manner of operation of date line
`and its respective probe.
`drive/sense unit 34 and gate line drive unit 44 is described
`in detail in the above mentioned U.S. Patent to Jenkins and
`Substrate 10 of FIG. 2 also includes structure which
`Wisnieff.
`40 permits using an alternative method for determining probe to
`pad contact quality. A test line 66, which may also be in the
`Data line drive/sense unit 34 and gate line drive unit 44
`form of a conductive loop, is connected to a test pad 67. Line
`are controlled by a test controller 46. Controller 46 contains
`66 is insulated from pads 22 by a series of insulators 68.
`a series of latches, registers, memory buffers and control
`Thus> a small capacitor is formed between each of pads 22
`logic so that appropriate sequential activation of various gate
`lines 24 and data lines 20 occur. More specifically instruc-
`and line 66 Alternatively, as shown with respect to pads 26,
`lions on how to conduct a test such as voltages to be applied,
`311 insulating layer or a series of discreet insulators 68A may
`lines to be activated, and time and length of activation are
`be formed over line 66, and pads 26 may each have an
`transferred to test controller 46. While controller 46
`extension 26A which extend over insulators 68A, thus
`forming a capacitor. In addition, the line 66 may be formed
`sequences the operation of circuitry within gate line drive
`below insulators 68A and extensions 26A.
`unit 44 via a bus 47, interaction with data line driver/sense
`unit 34 is via a bi-directional bus 48. Specifically, there are
`With this alternative structure test line 66 may be con­
`provisions for obtaining signals from the data lines for
`nected through pad 67 to a detector, of the kind described in
`analysis in the manner set forth below.
`the above mentioned patent, which can recognize the sig-
`Test controller 46 is connected by a bi-directional bus 50 55 nature of a properly operating probe to pad contact. Thus,
`the quality of probe to pad contact can be checked, if
`to a computer 52 by means of a standard digital interface
`desired, without the use of connection ring 60.
`board 54 located within computer 52. Computer 52 may be
`any one of a number of personal computers such as an IBM
`Conductive line 66 may also be located in the fan-out
`PS/2 model 80 with suitable software support for program­
`region of the gate and data lines, that is the region between
`ming in the C language to accomplish the functions go Pads 22 or 26 and the TFT/LCD array 12. In this case,
`described below. Computer 52 is connected to a high volume
`through capacitors formed between a gate line or a data line
`data storage device 56, such as a magnetic disk array, in a
`and line 66, it is possible to ascertain whether there is an
`manner well known in the art-
`open in the region of the gate line or data line adjacent to its
`respective pad.
`Referring to FIG. 2 for additional detail of substrate 10 a
`connection ring 60 on the upper surface of substrate 10 65
`Referring to the somewhat schematic representation in
`forms a continuous conductive loop. Connection ring 60 is
`FIG. 3, vertical data lines 20 run from pads on the top and
`electrically connected to a connection ring contact or pad 62
`bottom of the substrate. Gate lines 24 run horizontally from
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`In order to test the TFT/LCD array it is important to
`pads on the left and right edges. A thin film insulator isolates
`evaluate whether there is a defect, and if so, the nature of the
`the gate and data lines where they cross over one another,
`defect. One approach would be to digitize the entire wave-
`forming an overlap capacitor. An electrical pulse can be
`form. This would be quite costly in terms of time to acquire
`applied to an individual gate line at its edge connector. This
`pulse is capacitively coupled to the data line and sensed by 5 data, memory required to store data, and time required for
`the circuitiy connected to the data line. Many data lines
`analysis of the data. Surprisingly, it has been found that the
`dispersed across the display can be sampled in parallel and
`procedure can be automated by merely sampling the wave-
`their waveforms analyzed. A normal waveform sensed at forms
`at various points in time. In particular, each of the
`data lines crossing at each end of a gate line assures that the
`waveforms can be sampled at a time A prior to the appli-
`gate line is continuous. This procedure can be repeated for 10 cation of the gate pulse, a time B shortly thereafter, a time
`all of the gate lines. Two gate lines that have been identified
`Q at approximately the center of the gate pulse (after which
`as good, one near the top of the display and the other near
`substantiaily the entire voltage change has occurred in the
`the bottom, are then used for data line testing. All of the data
`case of the normal waveform illustrated in FIG. 5), a time D
`lines are sensed m this case, and their contacts and conti-
`end ^
`before
`and
`tirne
`s
`,
`,
`J ^
`nuity venfied. Vanous failure mechanisms (shorting of lines,
`Al4,
`,
`poor contact to the line, line breakage) can also be deter- 15 after the end of the gate pulse. Although this general
`mined from this test, as more fully described below.
`description of the times is quite precise, the actual sampling
`.
`,
`,
`, •
`, . ,
`times are subject to adjustment for vanous widths of gate
`rm
`Thus, m FIG. 3 pulses are applied to the driven end of the
`lses ^ for various desi
`of TFr/LCD ^ s and in
`gate lines. If the presence of a corresponding signature pulse
`Further; it ^ be
`icular fm various
`ixel desi
`on a first data line near a driven end and a second data line
`ized ^ the ^ ^ chosen t0 facilitate the ^ is
`at the end opposite the driven end is observed, this indicates
`formedi as described below with respect to FIG.
`which ig
`that the gate line that is continuous. Successive gate lines are
`12.
`tested in this manner to determine the top most and bottom
`Referring to FIG. 10 the generalized sequence for testing
`most continuous gate lines. Finally, the integrity of all data
`a TFT/LCD array is shown. When computer 52 receives a
`lines is evaluated by using the top most and bottom most
`start command at step 70 the program advances to step 72
`gate lines which have integrity. In FIG. 3 data lines 3 and 4 25
`where a line test is performed. Data points are taken along
`are identified as having opens by this method. Sense ampli­
`the length of each gate line. At step 74 a search is made for
`fiers of the type described in the above mentioned U.S.
`normal gate lines at the top and bottom of the panel.
`patent are connected to defective data line 3 and defective
`However, data is taken and stored for all gate lines. At step
`data line 4 and gate line pulse excitation is applied sequen­
`30 76 the two gate lines having integrity are used to obtain data
`tially to gate lines starting from the top gate line. This is the
`on every data line. At step 78 the data that is obtained is
`normal excitation procedure and no special logic for deter­
`utilized to characterize the data lines. Waveforms of the type
`mining the sequence of operation of the gate line drivers is
`illustrated in FIG. 5 through FIG. 9 are obtained and
`required. The location of which data line response changes
`analyzed in the manner more fully set forth below with
`from normal to zero is noted to define the location of the
`35 respect to FIG. 12.
`open in the data line. For data lines sensed at the top (such
`as data line 3) the response changes from normal to zero
`At step 80 the panel is scanned for crossing shorts. In the
`after gate line 2 is deactivated while for data lines sensed at
`case of a short, waveforms of the type represented by FIG.
`the bottom (such as data line 4) the response changes from
`8 will be present, but the voltage drop will be much more
`zero to normal (as gate line 5 is activated).
`pronounced. By comparing the voltage at point A and point
`As an alternative, if additional logic is available for 40
`and noting a large difference the presence of a short is
`detected. It is advantageous to perform this early m the
`controlling the order of gate line driver excitation there are
`overall test sequence for a TFT/LCD array. If a sizable
`any number of search algorithms which may be used to find
`number of shorts are present, the array may be deemed
`the open location. One example is use of a Newton half
`defective immediately, and testing may be terminated.
`interval algorithm.
`At step 82 the panel is scanned to collect data on cell
`Referring to FIG. 4, gate line 3 has been identified as
`charge retention of the individual cells. The manner in which
`having an open by the method described above with refer­
`this is done is more fully explained with reference to FIG.
`ence to FIG. 3. Gate line pulse excitation is applied to gate
`11.
`line 3. The response on the various data lines, as determined
`At step 84 waveforms for the individual cells are col­
`by sense amplifiers connected through a multiplex switch as 50
`lected. At step 86 tests are performed to obtain character­
`in the above mentioned U.S. patent is observed. A second
`ization curves for the thin film transistors. The manner in
`gate line pulse for the next setting of the multiplex switch is
`which steps 84 and 86 are performed is fully described with
`applied and the responses of all sense amplifiers are stored.
`reference to the above mentioned U.S. patent.
`This procedure is continued until sensing has been dome for
`all data lines. The position where the response changes from 55
`At step 88 testing for a given TFT/LCD array is complete.
`normal to zero indicates the location of the open in the gate
`The substrate is removed from the tester. A new substrate 10
`line in a manner analogous to that described above with
`having a TFT/LCD array to be tested is then placed on
`respect to FIG. 3.
`substrate holder 14 (FIG. 1). At receipt of the appropriate
`command by computer 52 the test sequence is repeated.
`Referring to FIGS. 5 to FIG. 9, when a pulse is applied to
`one of the gate lines, a resulting pulse having a particular 60 starting at step 70, for the new substrate,
`FIG. 11 illustrates the control sequence for the apparatus
`signature will appear on successive ones of the data lines.
`The pulse may be integrated using the sense circuits
`of FIG. 1 which is accomplished under the program of FIG.
`described in the above mentioned patent. The pulse, or
`10. At step 100 all outputs from digital interface board 54
`preferably the integrated waveform resulting from the pulse,
`(FIG. 1) to test controller 46 are initialized by being set equal
`may be analyzed to obtain information concerning at least 65
`to a given logic level (for example, a logic zero state). At
`step 102, a so-called hand shaking latch in test controller 46
`one of level of functionality of the TFT/LCD and quality of
`contact to the lines.
`is cleared. This hand shaking latch is responsive to a register
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`step 120 also determines whether the data is on an odd data
`which an be reset only by software so that the hardware and
`software are kept in synchronization and so that functions
`buffer or an even data buffer. At step 122, in accordance with
`can be performed in the hardware while other operations
`the calculation at step 120, an even or odd data buffer is
`occur in the software.
`selected. Finally, at step 124 data that is read from the data
`buffer passes via bus 50 and digital interface board 54 to
`Step 104 is a mode selection step. If a so called single cell 5
`mode is selected (steps 84 and 86 in FIG. 10) repeated
`computer 52.
`measurements are generated on a single pixel. A family of
`FIG. 12 is a decision tree which, in accordance with the
`curves may be generated or waveforms may be analyzed. If
`invention, is used to analyze the integrated waveforms
`a so called scan mode is selected, every time a test is
`obtained by the method outlined in the above mentioned
`performed (a reading taken), the gate line number under test l0
`U.S. patent. In general the types of waveforms which may
`is incremented by 1. The scan mode would be used, for
`be obtained are illustrated in FIG. 5 through FIG. 9. FIG. 12
`example, for a test such as checking charge retention on
`is a detailed explanation of the implementation of step 78 of
`every cell on the panel. Because of the automatic sequencing
`FIG. 10.
`through the gate lines it is unnecessary to manually select the
`Referring to FIG. 12, mathematical expressions are in
`gate lines in the scan mode.
`15 parentheses while the
`symbol indicates a logical "and"
`At step 106 logic operations are conducted to clear all data
`operation. In order to simplify discussion, the letters A,B,
`out of the shift registers which drive the gate lines. A
`C,D, and E are used to represent voltage levels at times
`sub-routine entitled "do gateset" then increments a logic 1
`A,B,C,D and E respectively. Differences in voltage levels
`signal through the shift register either automatically if the
`scan mode of step 104 is selected or to the proper position _Q arc specified as Diffl, Diff2 . . . DiffS, and their values for
`so that a pulse is applied to the correct gate line if the single
`a typical panel are specified in FIG. 12, where 1 count is
`cell mode is selected. Another sub routine entitled "do gate
`equal to, for example, approximately 2.5 millivolts,
`end" then confirms that the proper gate line has been
`Operations begin at step 200 when appropriate initializa-
`activated by examining the hand shaking latch, thus assuring
`tions of software occur. At step 202 an initial characteriza-
`completion of this process before a test is begun.
`tion of the waveform is conducted. It is based on the
`At step 108 all test parameters that have been selected by
`relationship of the voltage at points. A,B,C,D and E. If the
`mathematical conditions set forth therein are met by data
`using computer 52 are sent out to test controller 46 by
`obtained from data lines associated with cells at both ends of
`operation of digital interface board 54 and transmission by
`a data line, then branching to step 204 occurs. In other
`bus 50. These values are latched into the appropriate regis­
`words, there are five different conditions that must be met.
`ters by control test controller 46.
`for the two selected pixels, for branching to step 204 to
`At step 110 an address in a memory buffer in test
`occur. While differences Diffl, Diff2,... DiffS, used in FIG.
`controller 46 is set to a value of 000 in preparation for
`12 are all defined for the particular TFT/LCD array being
`running a test.
`tested, there are some general waveform characteristics
`At step 112 the appropriate multiplexer are turned on in
`which arc required for operation to be deemed normal (FIG.
`preparation for run