$
`
`Europaisches Patentamt
`
`European Patent Office
`
`Office europeen des brevets
`
`(n)
`EUROPEAN PATENT APPLICATION
`
`EP 0 887 695 A2
`
`(19)
`
`(12)
`
`(43) Date of publication:
`30.12.1998 Bulletin 1998/53
`
`(21) Application number: 98304794.5
`
`(22) Date of filing: 17.06.1998
`
`(51) Intel.6: G02F 1/136
`
`(84) Designated Contracting States:
`AT BE CH CY DE DK ES Fl FR GB GR IE IT LI LU
`MC NL PT SE
`Designated Extension States:
`AL LT LV MK RO SI
`
`(71) Applicant: Seiko Epson Corporation
`Shlnjuku-ku, Tokyo 163-0811 (JP)
`
`(72) Inventor: Hirabayashi, Yukiya
`Suwa-shi, Nagano-ken 392-8502 (JP)
`
`(30) Priority: 17.06.1997 JP 159699/97
`02.03.1998 JP 49722/98
`
`(74) Representative: Sturt, Clifford Market al
`Miller Sturt Kenyon
`9 John Street
`London WC1N2ES(GB)
`
`(54)
`
`Electro-optical device substrate and electro-optical device comprising such a substrate
`
`[Fig. 21
`
`[Object] In a liquid crystal panel substrate hav­
`(57)
`ing a layered film structure of interlayer insulation films
`and metal layers alternately formed on a semiconductor
`substrate provided with a transistor region for pixel se­
`lection thereon, to provide a configuration for achieving
`a uniform polishing rate without thickening of the inter­
`layer insulation film to be polished.
`[Solving Means] A liquid crystal panel substrate is
`provided with a shading film 12 composed of a second
`metal layer in a pixel region, a second interlayer insula­
`tion film 11 under the shading film, a wiring film 10 com­
`posed of a first metal layer under the second interlayer
`insulation film, a pixel electrode composed of a third
`metal layer on a third interlayer insulation film 13 on the
`shading film, and a connecting plug 15 connecting the
`wiring film 10 and the pixel electrode through an opening
`provided in the shading film 12. An lower dummy pattern
`A composed of the first metal layer and an upper dummy
`pattern B composed of the second metal layer are
`formed on the periphery of input terminal pads 26 in the
`non-pixel region. Since the surface level of the third in­
`terlayer insulation film 13 formed on the dummy patterns
`A and B is raised, excessive polishing is prevented at
`the position. As a result, a uniform polishing rate is
`achieved in CMP treatment.
`
`Printed by Jouve, 75001 PARIS (FR)
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`ChinaStar Ex.1002
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`Page 1 of 1919
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`

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`1
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`EP 0 887 695 A2
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`2
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`Description
`
`flective liquid crystal panel substrate 31 used in the re­
`flective liquid crystal panel 30. The reflective liquid crys­
`tal panel substrate 31 includes a rectangular pixel region
`The present invention relates to substrates for elec­
`(display region) 20 provided with pixel electrodes dis-
`tro-optical devices such as a reflective liquid crystal pan­
`s posed in matrix 14 shown in Fig. 18; gate line driver cir­
`el substrate, and particularly relates to an electro-optical
`cuits (Y drivers) 22R and 22L lying at the exteriors of the
`device substrate comprising a pixel region formed on an
`right and left sides of the pixel region 20 for scanning
`element region for selecting a pixel.
`gate lines (scanning electrodes or line electrodes); a"
`The present applicant disclosed configurations of a
`liquid crystal panel substrate, a liquid crystal panel and
`precharging/testing circuit 23 lying at the exteriors of the
`i" upper side of the pixel electrode 14 for data lines (signal
`a projection display device in Japanese Patent Applica-
`electrodes or column electrodes); an image signal sam­
`tion No. 8-279388 filed on October 22, 1996, as de­
`pling circuit 24 lying at the exterior of the bottom side of
`scribed below. The projection display device (liquid crys­
`the pixel electrode 14 for supplying image signals to the
`tal projector) using a reflective liquid crystal panel as a
`light valve includes, as shown in Fig. 17, a light source
`data lines in response to the image data; a sealing re-
`110 arranged along the system optical axis LQ; a polar- >s gion 27 with a frame shape lying at the exterior of the
`ized light illumination unit 100 including an integrator
`gate line drivers 22R and 22L, the prechargingAesting
`lens 120 and a polarized light converter 130; a polarized
`circuit 23 and the image signal sampling circuit 24, for
`placing a sealing agent 36; a plurality of terminal pads
`light beam splitter 200 for reflecting the S-polarized light
`26 arranged along the bottom end and connected to a
`beam emitted from the polarized light illumination unit
`flexible tape wiring 39 with an anisotropic conductive
`100 by an S-polarized light reflecting face 201; a dichroic 20
`film (ACF) 38 therebetween; a data line driver circuit(X
`mirror 412 for separating the blue light component (B)
`driver) 21 lying between the terminal pad array 26 and
`from the light reflected by the S-polarized light reflecting
`the sealing region 27 for supplying image signals to data
`face 201 of the polarized light beam splitter 200; a re­
`lines in response to the image data; and relay terminal
`flective liquid crystal light valve 300B for modulating the
`2S pads (so-called silver points) 29R and 29L lying beside
`separated blue light component (B); a dichroic mirror
`both ends of the data line driver circuit 21 for energizing
`413 for separating by reflection the red light component
`the counter electrode 33 on the glass substrate 35.
`(R) from the light beams after separation of the blue light
`The peripheral circuits (the gate line driver circuits
`by a dichroic mirror 412; a reflective liquid crystal light
`22R and 22L, the precharging/testing circuit 23 and the
`valve 300R for modulating the separated red light com­
`ponent (R); a reflective liquid crystal light valve 300G for
`image signal sampling circuit 24) lying at the interior of
`modulating the residual green light component (G)
`the sealing region 27 have a shading film 25 (refer to
`passing through the dich roic mirror 413; a projection op­
`Fig. 18) to shield from the incident light, which is the
`tical system 500 including aprojection lens for projecting
`same as the pixel electrode 14 of the topmost layer.
`synthesized light onto a screen 600, in which the light
`Fig. 20 is an enlarged partial plan view of the pixel
`region 20 of the reflective liquid crystal panel substrate
`components modulated in the three reflective liquid
`31, and Fig. 21 is a cross-sectional view taken along the
`crystal light valves 300R, 300G and 300B are synthe­
`line A-A' of Fig. 20. In Fig. 21, numeral 1 represents a
`sized by the dichroic mirrors 413 and 412 and the po­
`single-crystal silicon P" semiconductor substrate (an N~
`larized light beam splitter 200 in their reverse paths. Re­
`semiconductor substrate is also available) having a side
`flective liquid crystal panels 30 shown in Fig. 18 as a
`40 of 20 mm. Numeral 2 represents a P-type well region
`cross-sectional view are used as the reflective liquid
`formed on the top surface (main face) in the device-
`crystal light valves 300R, 300G and 300B.
`forming region (MOSFET etc.) of the semiconductor
`The reflective liquid crystal panel 30 includes a re­
`flective liquid crystal panel substrate 31 fixed with an
`substrate 1, and numeral 3 represents a field oxide film
`adhesive on a supporting substrate 32 composed of
`(so-called LOCOS) which is formed for separating de-
`glass or ceramic; a glass substrate 35 which is provided. <5 vices in the non-element-fomning region of the semicon-
`ductor substrate 1. The p-type well region 2 shown in
`with a counter electrode (common electrode) 33 com­
`Fig. 21 is formed as a common well region for the pixel
`posed of a transparent conductive (ITO) film, and which
`region 20 provided with a matrix of pixels having dimen­
`lies at the incident light side, and is opposed with a gap
`sions of, for example, 768x1024, and it is separated
`to the reflective liquid crystal panel substrate 31 en­
`from a P-type well region 2' (refer to Fig. 22) for fabri­
`closed by a frame composed of a sealing agent 36; and so
`cating the devices of the peripheral circuits (the gate line
`a known twisted nematic (TN) liquid crystal or a super
`driver circuits 22R and 22L, the precharging/testing cir­
`homeotropic (SH) liquid crystal 37 in which liquid crystal
`cuit 23, the image signal sampling circuit 24 and the data
`molecules are vertically aligned in a no-applied voltage
`line driver 21).
`state, the liquid crystal being sealed in the space en­
`The field oxide film 3 is provided With two openings
`closed by the sealing agent 36 between the reflective ss
`in the divided region of each pixel. A gate electrode 4a
`liquid crystal panel substrate 31 and the glass substrate
`composed of polycrystalline silicon or a metal silicide is
`35.
`formed via a gate insulating film 4b in the center of one
`
`30
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`as
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`2
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`Fig. 19 is a plan view of an enlarged layout of a re-
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`Page 2 of 1919
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`EP 0 887 695 A2
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`opening; an N+ source region 5a, and an N+ drain region
`5b formed on the P-type well region 2 at the both sides
`of the gate electrode 4a form a N-channel MOSFET (in­
`sulated-gate field effect transistor) for pixel selection to­
`gether with the gate electrode 4a. Gate electrodes 4a in
`a plurality of pixels arrayed in a line extend in the scan­
`ning line direction (the line direction of the pixels) to form
`gate lines 4.
`A P-type capacitor electrode region 8, which is com-.
`mon to the line direction, is formed on the P-type well
`region 2 in the other opening; a capacitor electrode 9a
`composed of polycrystalline silicon or a metal silicide
`formed on the P-type capacitor electrode region 8 with
`an insulating film (dielectric film) 9b therebetween forms
`a retention capacitor C for retaining a signal selected by
`the MOSFET for pixel selection together with the P-type
`capacitor electrode region 8.
`A first interlayer insulation film 6 is formed on the
`gate electrode 4a and the capacitor electrode 9a, and a
`first metal layer composed mainly of aluminum is formed
`on the insulating film 6.
`The first metal layer includes a data line 7 (refer to
`Fig.20) extending in the column direction, a source elec­
`trode wiring 7a, which protrudes from the data line 7 in
`a comb shape and is brought into conductive contact
`with a source region 4b through a contact hole 6a, and
`a relay wiring 10 which is brought into conductive con­
`tact with the drain region 5b through a contact hole 6b
`and with the capacitor electrode 9a through a contact •
`hole 6c.
`A second interlayer insulation film 11 is formed on
`the first metal layer which forms the data line 7, the
`source electrode wiring 7a, and the relay wiring 10, and
`a second metal layer essentially consisted of aluminum
`is formed on the second interlayer insulation film 11. The
`second metal layer includes a shading film 12 to cover
`the entire pixel region 20. The second metal layer as the
`shading film 12 forms a wiring 12b (refer to Fig. 22) for
`connecting the devices in the peripheral circuits (the'
`gate line driver circuits 22R and 22L, the precharging/
`testing circuit 23, the image signal sampling circuit 24
`and the data line driver circuit 21) formed on the periph­
`ery of the pixel region 20.
`A plug hole 12a is provided at a position of the shad­
`ing film 12 corresponding to the relay wiring 10. A third
`interlayer insulation film 13 is formed on the shading film
`12, and a rectangular pixel electrode 14 which substan­
`tially corresponds to one pixel is formed as a reflective
`electrode on the interlayer insulation film 13. A contact
`hole 16 is formed through the third and second interlayer
`insulation films 13 and 11 so that it is located inside the
`opening 12a. After the contact hole 16 is filled with a
`high-melting-point metal such as tungsten by a CVD
`process, the high-melting-point metal layer formed on
`the third interlayer insulation film 13 and the front face
`of the interlayer insulation film 13 are flattened to form
`a mirror surface by a chemomechanical polishing (CMP)
`process. Next, an aluminum layer is formed by a low
`
`is
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`temperature sputtering process and a rectangular pixel .
`electrode 14 with a side of 15 nm to 20 nm is formed by
`a patterning process. The relay wiring 10 and the pixel
`electrode 14 are electrically connected by a pillar con-
`& necting plug (interlayer conductive section) 15. A.pas-
`sivatingfilm 17 is formed on the entire pixel electrode 14.
`Alternatively, the connecting plug 15 may be formed
`by planarizing the third interlayer insulation film 13 by a
`CMP process, providing a contact hole and burying a
`'0 high-melting-point metal such as tungsten.
`The planarization of the third interlayer insulation
`film 13 by the CMP process is essential for depositing
`a pixel electrode 14 with a mirror surface as a reflective
`electrode on each pixel. The process is also essential
`for the formation of a dielectric mirror film on the pixel
`electrode 14 with a protective film therebetween. The
`CMP process uses a slurry (polishing liquid) composed
`of components which simultaneously prompt chemical
`etching and mechanical polishing of a wafer before
`20 scribing.
`In the pixel region 20, however, the MOSFET for
`pixel selection, the electrode wirings 7a and 10 of the
`retention capacitor C and the shading film 12 are formed
`as underlying layers. Also, as shown in Fig. 22, in the
`25 peripheral circuit region (the gate line driver circuits 22R
`and 22L, the precharging/testing circuit 23, the image
`signal sampling circuit 24 and the data line driver circuit
`21), the electrode wirings 7a and the wiring 12b between
`the devices are formed as underlying layers. Further, in
`the region of the terminal pad 26, an lower layer film 26a
`composed of the first metal layer and an upper layer film
`26b composed of the second metal layer are formed. As
`a result, immediately after the deposition of the third in­
`terlayer insulation film 13, the surface level 13a repre­
`ss sented by a broken line in Fig. 22 rises up at the pixel
`region, the peripheral circuit region and the terminal pad
`region. When polishing the surface of the third interlayer
`insulation film 13 having such large unevenness by the
`CMP process, the finished level 13b after polishing rep-
`resented by the solid line in Fig. 22 reflects the original
`surface level 13a represented by the broken line. Ac­
`cording to intensive investigations by the present inven­
`tor, it is clarified that the surface planarization of the third
`interlayer insulation film 13 on the pixel region is partic-
`45 ularly important in the liquid crystal panel substrate 31
`subjected to such polishing treatment.
`Japanese Unexamined Patent Publication No.
`9-68718 discloses a technology for planarization of the
`third interlayer insulation film 13 on the pixel region 20,
`in which discrete dummy patterns of the metal layer for
`individual pixels are provided between the first metal
`layer, such as the relay wiring 10, and the second metal
`layer (shading layer) to raise the level in order to sup­
`press the entire surface unevenness of the shading film
`55 12. When the intermediate metal layer is formed only for
`raising the level for each pixel, an additional step for de­
`positing an interlayer insulation film should be incorpo­
`rated. When the surface unevenness of the interlayer
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`5"
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`so
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`EP 0 887 695 A2
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`insulation film is reduced before polishing, the initial pol­
`ishing rate in the CMP treatment unintentionally de­
`creases, and thus planarization of the interlayer insula­
`tion film 13 to form a mirror surface requires a long pol­
`ishing time and a large amount of polishing liquid. The
`deposition of dummy patterns on individual pixels in the
`pixel region 20 therefore has a disadvantage in the pro­
`duction process, resulting in increased production
`costs.
`
`[Problems to be Solved by the Invention]
`
`Fig. 23 is a contour plot of film illustrating the thick­
`ness distribution of the third interlayer insulation film 13
`after polishing of the liquid crystal panel substrate 31, in
`which the third interlayer insulation film 13 with a thick­
`ness of approximately 24,000 A is formed and then sub­
`jected to the CMP treatment until the residual thickness
`of the third interlayer insulation film 13 reaches approx­
`imately 12,000 A in the center of the pixel region 20. In
`Fig. 24, a graph depicted by marks X shows the residual
`thickness distribution of the left seal in the vertical direc­
`tion taken along line a-a' of Fig. 23. In Fig. 25, a graph
`depicted by marks x shows the residual thickness dis­
`tribution of the central pixel in the vertical direction taken
`along line b-b1 of Fig. 23. In Fig. 26, a graph depicted by
`marks X shows the residual thickness distribution of the
`upper seal in the transverse direction taken along line
`c-c' of Fig. 23. In Fig. 27, a graph depicted by marks x
`shows the residual thickness distribution of the central
`pixel in the transverse direction taken along line d-d' of
`Fig. 23. In Fig. 28, a graph depicted by marks X shows
`the residual thickness distribution of the lower sealing
`region in the transverse direction taken along line e-e'
`of Fig. 23.
`•
`As shown in Figs. 23 to 28, the maximum difference
`in the thickness is approximately 6,120 A in the pixel
`region 20 and the sealing region 27, hence the substrate
`including the pixel region 20 and sealing region 27 as a
`whole is not sufficiently flattened. The periphery of the
`terminal pad 26 and the upper and lower centers of the
`sealing regions 27 are excessively polished, whereas
`the right and left centers of the sealing region 27 are
`insufficiently polished.
`As shown in Fig. 22, since the protruding terminal
`pads 26 in spot shape are discretely arranged as an ar­
`ray in the terminal pad region, the protruding sections
`13c covered with the third interlayer insulation film 13
`will be rapidly polished. The region of the terminal pad
`26 therefore has a higher initial polishing rate than that
`of the pixel region 20. Accordingly, the region of the ter­
`minal pad 26 may be excessively polished to expose the
`underlying layer ( upper layer film 26b) before the pixel
`region 20 is sufficiently flattened.
`A means for compensating for the excessive polish­
`ing of the terminal pad 26 includes thick deposition of
`the third interlayer insulation film 13. According to this
`method, even if the region of the terminal pad 26 is rap-
`
`s
`
`10
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`2S
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`idly polished, planarization of the third interlayer insula­
`tion film 13 is almost completed in this region before the
`underlying layer is exposed, hence the polishing rate
`significantly decreases compared with the initial polish­
`ing rate. As a result, the pixel region 20 can be flattened
`by spending an increased polishing time without expos­
`ing the underlying layer.
`The formation of the thick third interlayer insulation
`film 13 causes an increased depth of the contact hole
`for the connecting plug 15, and it is difficult to embed
`the contact hole 16 with the high-melting-point metal
`which constitutes the connecting plug 15 as a result of
`such a high aspect ratio. The contact hole 16 originally
`has a large depth because the connecting plug 15 is a
`'5 conductive section skipping an interlayer, which is
`formed through the second interlayer insulation film 11,
`the shading layer 12 and the third interlayer insulation
`film 13, and reaches the pixel electrode 14. Further, the
`opening 12a and thus the diameter of the contact hole
`20 16 must be reduced in order to prevent leakage of the
`light entering from the gap between the pixel electrodes
`14 to the devices such as MOSFET and the like through
`the opening 12a. The contact hole 16 inevitably has a
`high aspect ratio. Thinning of the interlayer insulation
`film 13to be polished is therefore required. As described
`above, however, the CMP process excessively polishes
`the third interlayer insulation film 13 in the region of the
`terminal pad 26.
`Since the thickness of the upper and lower centers
`so of the sealing region 27 is smaller than that of the pixel
`region because of excessive polishing in the region of
`the terminal pad 26, the upper and lower edges of the
`pixel region 20 and the upper and lower center of the
`sealing region 27 are excessively polished, as shown in
`35 Fig. 26 and 28. The four corners of the sealing region
`27 at the right and left sides will have also small thick­
`nesses because of the excessive polishing of the region
`of the terminal pad 26, whereas the right and left centers
`of the sealing region 27 are hardly polished because of
`40 a low initial polishing rate caused by the flatness of the
`sealing region 27 before polishing. As a result, the right
`and left sides of the sealing region 27 and the right and
`left edges of the pixel region 20 are insufficiently pol­
`ished in their central portions. When the peripheral edg-
`« es of the pixel region 20 and the sealing region 27 have
`such tilted faces, the reflectance of the pixel electrode
`14 formed on the third interlayer insulation film 13 after
`polishing decreases, the cell gap is adjusted with diffi­
`culty in the liquid crystal assembly, and the sealing agent
`50. has unsatisfactory adhesiveness. When the contact
`hole 16 for the connecting plug 15 is provided after the
`CMP treatment, it is difficult to optimize the etching time
`for the contact hole because of the uneven thickness.
`In view of the incompatible problems regarding the
`interlayer insulation film formed between the shading
`film and the pixel electrode and requiring the polishing
`treatment in the reflective liquid crystal panel substrate,
`a first object of the present invention is to provide an
`
`55
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`Page 4 of 1919
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`electro-optical device substrate, such as a liquid crystal
`panel substrate, comprising a layered film structure of
`a plurality of interlayer insulation films and a plurality of
`conductive layers alternately formed in a pixel region
`formed on a substrate, wherein the electro-optical sub­
`strate has a structure requiring no additional deposition
`step and having a uniform polishing rate for the interlay­
`er insulation film without thickening of the interlayer in­
`sulation film.
`A second object of the present invention is to pro­
`vide an electro-optical device substrate, such as a liquid
`crystal panel substrate, which has a flattened polished
`surface of the interlayer insulation film in the sealing re­
`gion as well as in the pixel region, an improved reflect­
`ance of the pixel electrode, and which permits ready ad-
`justment of the cell gap, improved adhesiveness of the
`sealing agent, and an optimized etching time of the con­
`tact hole.
`Embodiments of the present invention will now be
`described by way of example only and with reference to
`the accompanying drawings, in which:
`Fig. 1 is a plan view of a layout of a reflective liquid
`crystal panel substrate for a reflective liquid crystal pan­
`el in accordance with Embodiment 1 of the present in­
`vention.
`Fig. 2 is a cross-sectional view taken along the line
`B-B'inFig. 1.
`Fig. 3 is a cross-sectional view of another configu­
`ration of the input terminal padcorrespondingtothe sec­
`tional structure in Fig.1.
`Fig. 4 is a partial plan view near the pixel region and
`the sealing region in the reflective liquid crystal panel
`substrate in Embodiment 1.
`Fig. 5 is a partial plan view near the data line driver
`circuit in the reflective liquid crystal panel substrate in 35
`Embodiment 1.
`Fig. 6 is a partial plan view near the terminal pads
`in the reflective liquid crystal panel substrate in Embod­
`iment 1.
`Fig. 7 is a partial plan view illustrating connection 40
`between the terminal pads and flexible tape wiring in the
`reflective liquid crystal panel substrate in Embodiment
`
`ns
`
`30
`
`tion of the sealing region in a reflective liquid crystal pan­
`el substrate in accordance with Embodiment 2 of the
`present invention.
`Fig. 12 is a cross-sectional view taken along the line
`s C-C in Fig. 11.
`Fig. 13 is a contour plot of film illustrating the thick-
`ness distribution of the third interlayer insulation film af­
`ter polishing of the liquid crystal panel substrate in ac­
`cordance with Embodiment 2, in which the third inter-
`layer insulation film with a thickness of approximately
`24,000 A is formed and then subjected to the CMP treat­
`ment until the residual thickness of the third interlayer
`insulation film reaches approximately 12,000 A in the
`center of the pixel region.
`Fig. 14 is a partial plan view of the four-corner por­
`tion of the sealing region in a reflective liquid crystal pan­
`el substrate in accordance with Embodiment 3 of the
`present invention.
`Fig. 15 is a cross-sectional view taken along the line
`C-C in Fig. 14.
`Fig. 16 is a contour plot of film illustrating the thick­
`ness distribution of the third interlayer insulation film af­
`ter polishing of the liquid crystal panel substrate in ac­
`cordance with Embodiment 3, in which the third inter­
`layer insulation film with a thickness of approximately
`24,000 A is formed and then subjected to the CMP treat­
`ment until the residual thickness of the third interlayer
`insulation film reaches approximately 12,000 A in the
`center of the pixel region.
`Fig. 17 is a schematic diagram of a video projector
`as an example of a projection display device using a re­
`flective liquid crystal panel as a light valve.
`Fig. 18 is a cross-sectional view of a reflective liquid
`crystal panel.
`Fig. 19 is a plan view of a reflective liquid crystal
`panel substrate used in a conventional reflective liquid
`crystal panel.
`Fig. 20 is a partial plan view of the pixel region of
`the reflective liquid crystal panel substrate in Fig. 19.
`Fig. 21 is a cross-sectional view taken along the line
`A-A' of Fig. 13.
`Fig. 22 is a cross-sectional view taken along the line
`B-B' of Fig. 12.
`Fig. 8 is a cross-sectional view taken along the line
`Fig. 23 is a contour plot of film illustrating the thick-
`A-A' in Fig. 7.
`4$ ness distribution of the third interlayer insulation film af­
`Fig. 9 is a partial plan view of the periphery of the
`ter polishing of the conventional reflective liquid crystal
`relay terminal pad in the reflective liquid crystal panel
`panel substrate shown in Fig.19, in which the third in­
`substrate in accordance with Embodiment 1.
`terlayer insulation film with a thickness of approximately
`24,000 A is formed and then subjected to the CMP treat-
`Fig. 10 is a contour plot of film illustrating the thick-
`ness distribution of the third interlayer insulation film af- so ment until the residual thickness of the third interlayer
`insulation film reaches approximately 12,000 A in the
`ter polishing of the liquid crystal panel substrate in ac-
`cordance with Embodiment 1, in which the third inter­
`center of the pixel region.
`layer insulation film with a thickness of approximately
`Fig. 24 is a graph of residual film thickness distribu­
`24,000 A is formed and then subjected to the CMP treat­
`tions in the vertical direction of the left side of the seal
`ment until the residual thickness of the third interlayer
`taken along the line a-a' in the conventional embodiment
`insulation film reaches approximately 12,000 A in the
`in Fig. 23, Embodiment 1 in Fig. 10, Embodiment 2 in
`center of the pixel region.
`Fig. 13 and Embodiment 3 in Fig. 16.
`Fig. 11 is a partial plan view of the four-corner por-
`Fig. 25 is a graph of residual film thickness distribu-
`
`7
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`EP 0 887 695 A2
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`8
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`9
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`EP 0 887 695 A2
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`10
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`tions in the vertical direction of the pixel center taken
`along the line b-b' in the conventional embodiment in
`Fig. 23, Embodiment 1 in Fig. 10, Embodiment 2 in Fig.
`13 and Embodiment 3 in Fig. 16.
`Fig. 26 is a graph of residual film thickness distribu­
`tions in the transverse direction of the upper side of the
`seal taken along the line c-c' in the conventional embod­
`iment in Fig. 23, Embodiment 1 in Fig. 10, Embodiment
`2 in Fig. 13 and Embodiment 3 in Fig. 16.
`Fig. 27 is a graph of residual film thickness distribu­
`tions in the transverse direction of the pixel center taken
`along the line d-d1 in the conventional embodiment in
`Fig. 23, Embodiment 1 in Fig. 10, Embodiment 2 in Fig.
`13 and Embodiment 3 in Fig. 16.
`Fig. 28 is a graph of residual film thickness distribu­
`tions in the transverse direction of the pixel center taken
`along the line e-e1 in the conventional embodiment in
`Fig. 23, Embodiment 1 in Fig. 10, Embodiment 2 in Fig.
`13 and Embodiment 3 in Fig. 16. In a first means in the
`present invention for achieving the first object, in order 20
`to flatten the surface level of the unpolished interlayer
`insulation film as uniformly as possible, a dummy pat­
`tern for raising the level of an interlayer insulation film
`to be polished is formed on the entire exterior of the pixel
`region by using the previously formed wiring layer, in- 25
`stead of on the space in the pixel region. That is, the
`arrangement is characterized by an electro-optical de­
`vice substrate comprising a layered film structure of a
`plurality of interlayer insulation films and a plurality of
`conductive layers alternately formed in a pixel region, in so
`which a switching element is arranged on the substrate
`in response to each pixel, at least one interlayer insula­
`tion film below the top conductive layer among the plu­
`rality of conductive layers being flattened by polishing;
`the substrate being characterized in that a dummy pat- 35
`tern with a single or a plurality of layers comprising the
`conductive layers below said interlayer insulation film
`subjected to the polishing is provided near at least a ter­
`minal pad formed at a non-pixel region on the substrate.
`The terminal pad includes an input terminal pad ar- 40
`ranged near the edge of the substrate and a relay ter­
`minal pad provided at the inner position of the substrate.
`Since the surface level of the formed interlayer in­
`sulation film to be polished is raised near the terminal
`pad in such a configuration of the dummy pattern pro­
`vided near the terminal pad, the surface level'is substan­
`tially the same as the surface level of the interlayer in­
`sulation film to be polished in the pixel region, and thus
`the surface level is made uniform over the entire sur­
`face. The uniform surface has a uniform polishing rate
`in chemomechanical polishing (CMP) or the like without
`prompted polishing near and outside the terminal pad
`region and the polished surface of the interlayer insula­
`tion film is more flattened than conventional surfaces.
`As a result, the pixel region is more satisfactorily flat­
`tened, control of the cell gap is improved in cell assem­
`bly using a counter substrate, and the etching time for
`the contact holes of the interlayer conductive portion
`
`etc., in the pixel region after polishing is easily deter­
`mined.
`Such a uniform polished surface prevents exposi­
`tion of the underlying terminal pad layer due to exces­
`s sive polishing at the terminal pad portion, and can
`achieve thinning of the unpolished interlayer insulation
`film. Since the aspect ratio of the contact hole at the in­
`terlayer conductive portion in the pixel electrode is im­
`proved by the thinning, an opening portion with a small
`to diameter is achieved by a contact hole with a small di­
`ameter. As a result, shading characteristics are im­
`proved.
`The interlayer conductive portion electrically con­
`nects the first conductive layer connecting to the switch­
`'s ing element and the upper conductive layer formed on
`the interlayer insulation film to be polished, and the dum­
`my pattern may be any one of a first dummy pattern
`composed of the first conductive layer, a second dummy
`pattern composed of the second conductive layer which
`is formed between the first conductive layer and the up­
`per conductive layer such as the shielding film, and a
`composite thereof.
`When a conductive dummy pattern lies near the ter­
`minal pads outside the pixel region, the dummy pattern
`functions as a shading film, hence it prevents the inva­
`sion of stray light from the exterior of the pixel region
`into the pixel region on the substrate, resulting in a sup­
`pressed photocurrent flow and an improved switching
`element.
`Since the input terminal pad is connected to the ex­
`ternal wiring by themnocompression