Interconnect Capacitances, Crosstalk, and Signal Delay
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`in Vertically Integrated Circuits
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`Stefan A. Ktihn(1’2), Michael B. Kleineru’ 2’, Peter Rammm, and Werner Weber“)
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`(1) Siemens AG, Corporate R&D, ZFE T ME2, Otto Hahn-Ring 6, D-81739 Mtinchen, Germany
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`Tel.: +49-89-636-41275, Fax.: +49-89-636-41442, email: stef@par1.zfe.siemens.de
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`(2) Institute for Integrated Circuits, Technical University of Munich, Arcisstr. 21, D-80333 Munchen, Germany
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`(3) Fraunhofer Institute for Solid State Technology, Hansastr. 27d, D-80686 Mfinchen, Germany
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`lateral multilayer interconnections
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`lateral multilayer interconnections
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`— — —
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`\ Z
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`vertical interconnect
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`silicon
`substrate
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`interlaycr-
`dielectric
`(poiyimidhc
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`vertical interconnect
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`iriterlayer—
`dielectric
`(polyimide)\L 22;;
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`active devi
`‘silicon isla
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`Abstract
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`The impact of the three-dimensional circuit structure in
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`on
`Vertically Integrated Circuits
`(VICS)
`interconnect
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`capacitances, crosstalk and signal delay is investigated
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`based on measurements and simulations. In comparison with
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`planar IC technologies,
`increased substrate coupling and
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`reduced coupling capacitances between adjacent
`inter-
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`connection lines considerably improve the noise immunity
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`for VICs with
`chiplayers fabricated in
`silicon—bulk
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`technology. For thin-film silicon—on-insulator chiplayers.
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`noise immunity can be assured through the integration of
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`conductive layers between active chips. The
`reduced
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`interconnection lengths at system level lead to decreased
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`interconnect delays despite higher
`total
`interconnect
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`capacitances.
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`Introduction
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`\_/ertically Integrated Circuits (VIC) consist of independently
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`processed chiplayers, which are stacked on top of each other
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`as
`with polyimide
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`interlayer-dielectric. The
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`individual chips are thinned down to a few microns of
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`remaining substrate thickness prior to assembly. Extremely
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`high integration densities in the three-dimensional circuit
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`structure allow the realization of complete multifunctional
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`systems on a single stack of chips [1,2]. The possibility of
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`fabricating a huge number of direct
`interconnects [3,4]
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`between adjacent chiplayers provides an adequate vertical
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`interconnection bandwidth. Fig. 1 shows a schematic cross-
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`sectional view of a two-layer VIC which forms the basis of
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`the study. Chiplayers fabricated in siliconqoulk and thin-film
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`silicon-on-insulator (S01)-technology are investigated.
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`Interconnect capacitances in VICs
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`has
`The
`structure
`densely packed circuit
`in VICs
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`considerable impact on the characteristics of interconnection
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`lines. Especially interconnect capacitances in the upper
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`metallization layers of the bottom chiplayer are strongly
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`affected by additional coupling to the upper chiplayer. Fig. 2
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`shows the increase in capacitance per unit length due to the
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`additional coupling to the substrate of the upper chiplayer
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`fabricated in silicon bulk technology. The impact of the
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`thickness h of the interlaycr dielectric on the capacitances of
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`Fig. 1: Schematic cross-sectional View of two-layer yertically
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`Integrated Circuits (VICS) with chiplayers fabricated in
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`silicon-bulk
`technology
`(top)
`and thin-film SOI-
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`technology (bottom).
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`‘interconnection lines with different width is depicted.
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`Measured data show good agreement with simulation results.
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`While the substrate capacitance is considerably increased,
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`coupling between interconnection lines
`in the
`same
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`0-7803-2700-4 $4.00 ©1995 IEEE
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`IEDM 95 —249
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`10.3.1
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`SAMSUNG ET AL. EXHIBIT 1059
`Page 1 of 4
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`switching at an amplitude of I/,-,, can be expressed with the
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`following equation:
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`Zck-I
`:V _
`'" (c,+cb+2ck)-l+CL+Cd,
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`P"
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`(1)
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`c,, c;, and c;, are capacitances per unit length to top substrate,
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`bottom substrate and neighboring line, respectively. 1 is the
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`coupled line length, CL the load capacitance of the line, and
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`the driver output capacitance. Additional coupling to
`Cd,
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`is
`interconnects
`not
`directly
`adjacent
`neglected
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`simplicity. Fig. 4 shows the ratio of the worst case peak
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`crosstalk amplitude at an unloaded signal line (CL , C,,,=O) to
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`the
`input
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`neighboring
`lines
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`simultaneously switching as a function of the line spacing s.
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`Compared to the planar case, in the 3D—IC the line spacing s
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`can be chosen much smaller without reaching the logic
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`threshold voltage of CMOS gates. Even with reduced
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`absolute values of VP“ due to finite CL and Cd,, noise
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`immunity on VlCs is considerably improved.
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`Vpet / Vii:
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`4
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`5 s/[pm]
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`metallization layer decreases substantially. Fig. 3 shows the
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`total and intralayer coupling capacitances per unit length as
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`function of line spacing in 3D-structures (VIC- bottom
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`layer)
`compared to planar
`technology. Deviations of
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`measured values from simulated results are mainly due to
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`inhomogeneities in the intcrlayer dielectric.
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`Cs / [fF/mm]
`300
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`5 d/[pm]
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`Fig. 2: Substrate capacitance C, of interconnection lines in the
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`bottom layer of a VIC (3d, with l llm polyirnide, sr= 3.5
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`and 0.8 pm of passivation between the chiplayers) and in
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`planar lCs (Zd) as a function of the thickness d of the
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`underlying dielectric
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`indicates measured
`(SiO;).
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`capacitance values
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`linewidth w =2 pm and line
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`thickness t= 0.8 um.
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`tF/mm]
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`3d,
`Cl Cu+2°k
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`» 2d,
`cb+2ck
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`’2d, 2ck
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`Fig. 4: Ratio of peak crosstalk amplitude to input voltage at a
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`minimum sized unloaded line between two simultaneously
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`switching interconnection lines as a function of the line
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`spacing s (linewidth w = 1.2 um, line thickness 2.‘ = 0.8 ].ll’I’l,
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`dielectric
`thickness d = 3.0 pm,
`polyimide
`thickness
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`hpf = 1.0 i1m,c, = 3.5).
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`vpc,—3d/vwgzd
`0.9‘
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`3 hpil [um]
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`Fig.5: Ratio of peak crosstalk voltage of bottom layer line to top
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`layer line or interconnect on planar IC as function of the
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`thickness hp] of the interlayer dielectric (polyirnide, 83:35).
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`3d, Zck
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`5 S/[Hm]
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`Fig. 3: Coupling capacitance and total capacitance per unit length
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`as a function of the line spacing s. linewidth w = 2 pm, line
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`thickness 1‘: 0.8 pm, thickness d of underlying dielectric
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`= 3 pm, 0.8 pm passivation and 1 pm of pnlyirnide between
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`the chiplayers. (0) indicate measured capacitances for the
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`VIC~bottom layer, (o) indicate measured values for planar
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`technology, respectively.
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`Signal crosstalk in 3D circuit structures
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`The worst case peak crosstalk amplitude VIM, at a quiescent
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`signal
`line between two neighboring lines simultaneously
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`250—IEDM 95
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`10.3.2
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`SAMSUNG ET AL. EXHIBIT 1059
`Page 2 of 4
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`clug-layer
`Silicon
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`Polyimide
`Si02 '
`Bottom
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`chip-layer
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`Bulk sag
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`Fig. 5 shows the worst case crosstalk amplitude ratio on a
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`signal line on t11e bottom chiplayer to the respective value for
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`a line on the top layer or on a planar IC. The amplitude ratio
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`is independent of line loading and is depicted as a function
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`of the polyimide thickness between the chiplayers. The
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`combination of additional substrate coupling and decreased
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`coupling between adjacent
`lines
`(c. f. Figs. 2
`and 3)
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`considerably increases noise immunity in VICs and allows
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`smaller spacings between adjacent signal lines. Fig. 6 shows
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`measured crosstalk amplitudes on a 1 cm long inter-
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`connection line between two parallel lines simultaneously
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`switching (w = s = 1.2 pm, Vin = 3.3 V) in the upper (top)
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`and lower (bottom) VIC chiplayer. The reduced absolute
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`values are due to impedance mismatch and load capacitances
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`of the measurement setup, but the experiment reproduces the
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`correct amplitude ratio.
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`Fig. 7: SEM photomicrograph of a VIC with two chiplayers in
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`silicon-bulk technology and 1 pm of polyimide between the
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`layers.
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`With chiplayers fabricated in thin—film SOI—technology,
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`capacitive shielding between the chiplayers is not assured by
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`a silicon layer. Fig. 8 shows the coupling mpacitance c,~
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`between a signal line in the lowest metallization layer of the
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`upper chip and a conductive plane
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`topmost
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`metallization layer of the bottom chip, and the intralayer
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`coupling capacitance ck as a fimction of the thickness of the
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`interlayer dielectric hpi. Measured data in Fig. 8 are obtained
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`from a specimen simulating the dimensional properties of a
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`stacked structure of thin-film SOI—chiplayers. For noise
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`sensitive applications, interlayer coupling in thin—f1lm SOl-
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`structures can be prevented by the integration of conductive
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`layers between the active chiplayers.
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`C / [fF/mm]
`so
`A
`70
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`chiplayer int/erfac
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`h,,./ [Hm]
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`60
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`0
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`Fig. 8: Intra- and Interlayer coupling capacitances for a VIC with
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`thin-film SOI-chiplayers, w = 2 pm, s = 2 pm, I : 0.8 pm,
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`d = 0.9 pm (oxide under top-metallization).
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`5
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`: imil
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`L
`l
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`l 2
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`E
`L... ......_l.._,
`ifi
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`l
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`top-chiplayer (ZD)
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`—LflB.Jmv
`rdfifins
`
`,
`Efinv
`'d:v‘
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`bottom-chiplayer (3 D)
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`rlflflmtl
`’4EEns
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`‘I-Tr]
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`l.Gn:
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`Eflflns/d x
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`Fig. 6: Measured crosstalk on a lcm long interconnection line
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`between two minimum spaced simultaneously switching
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`lines on upper chiplayer (top) and lower chiplayer (bottom)
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`(w = s =l.2 um, t= 0.8 pm, d= 3 pm, hpf = l urn).
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`For silicon bulk technology, the substrate of the upper layer
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`is capacitively decoupled from the underlying circuitry.
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`Fig, 7 shows an SEM photomicrograph of a two layer VIC
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`with 8.5 pm of substrate in the upper chiplayer and 1 pm of
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`polyimide between the layers.
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`SAMSUNG ET AL. EXHIBIT 1059
`Page 3 of 4
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`length. A line of equal length in the bottom chiplayer (B)
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`shows increased signal delay due to the higher capacitance
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`per unit length. The integration of systems on VIC leads to
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`shorter interconnection lengths. Traces (C) and (D) show
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`reduced interconnect delays compared to (A) for two layer
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`and four layer VlCs with the same chip area as the planar
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`system. The edge length of the chiplayers is taken as
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`measure of the interconnection length.
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`r,,/ [ns]
`2.0
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`1/ [mm]
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`Fig. 10: Signal delay for global interconnection lines as a function
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`of
`line length l
`in planar system (A), VIC-realization
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`(bottom layer) using the same length (B), two-layer (C)
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`and four layer structure (D) with equal area and reduced
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`interconnection lengths.
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`Conclusion
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`
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`delays
`With
`on
`signal
`system size,
`increasing
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`
`
`can
`and crosstalk requirements
`interconnection lines
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`influence the system performance considerably. Compared to
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`planar realizations, VICs allow major reductions in both
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`signal delay and crosstalk due to the reduced coupling
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`eapacitances, increased substrate coupling and reduced wire
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`lengths. In conclusion, major constraints on interconnect
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`system design can be alleviated using Vertical
`integration
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`technology.
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`
`Acknowledgment
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`The authors would like to thank H. Lezec from Micrion
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`Corp. for his support in sample preparation. This paper is
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`based on a project which is supported by the German
`
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`
`
`minister of research and technology under
`the support
`
`
`
`number 0 1 M 2926.
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`Interconnect delay in VICs
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`The increased total capacitances of interconnects in the
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`bottom layer
`(e. f. Fig. 2) affect
`the signal
`transmission
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`considerably. For equal line lengths the additional coupling
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`to the upper chiplayer leads to increased signal delays. Fig. 9
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`shows measured signal traces for a falling transition at the
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`end of a 1 cm long interconnection line on bottom- and top
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`chiplayer of a VIC.
`
`Exa
`
`'“\:\l“x\ bottom-ehip|ayer(3D)
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`‘.3§ns-div
`
`73.-Sns
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`Fig. 9: Signal transition at the end of a 1 cm long interconnection
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`line on bottom- and top—ehiplayer, w = 1.2 pm, t= 0.8 pm,
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`d= 0.3 pm, hpf:1l1m.
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`
`delay
`on
`Based
`values,
`capacitance
`the measured
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`
`
`
`lengths
`calculations for interconnection lines of different
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`were performed. The lines are loaded with a minimum size
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`inverter and driven by a buffer of cascaded inverters
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`optimized for minimum power-delay product [5]. The signal
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`
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`o11 an interconnection line of length I is given by
`delay 1,;
`
`
`
`
`the following equation:
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`
`
`drw
`r,,=ln2-(R c l+Rd,CL+0.5rwcWl2+rwCLZ)+rd,
`
`(2)
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`1,1, and R1, are intrinsic driver delay and output resistance,
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`CL is the load capacitance and r,,
`the line resistance per unit
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`length. The wiring capacitance per unit length is given by:
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`cW:c,+c,,+2ck
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`cw—c,,+2c,,
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`for 3D-IC (bottom layer), and
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`for planar IC.
`
`
`
`(3)
`
`References
`
`
`
`S. Kfihn et al. , Proe. l995 ECTC, pp. 592-599.
`
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`S. Takahasl-ii et al., Proc. I992 MCMC, pp. 159-162.
`
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`
`
`M. Engelhardt ct a.l., Proc. 1995 Europ. Plasma Seminar, pp. 13-24.
`
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`
`
`Y. Hayashi et al., Proc. 1991 IEDM, pp. 657-660.
`
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`J.—S. Choi and K. Lee, IEEE JSSC, 29(9), 1994, pp. 1142-1145.
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`c, and cb are the capacitances to top- and bottom-substrate.
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`A single contribution of the coupling eapacitances ck to the
`
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`interconnect delay corresponding to quiescent neighboring
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`lines is assumed. Indicated in Fig. 10 is the signal delay on
`
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`the top metallization layers of a planar 1C or on the top
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`chiplayer in a VlC’(A) as a function of the interconnection
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`252—lEDM 95
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`SAMSUNG ET AL. EXHIBIT 1059
`Page 4 of 4