MCM ’94 Proceedings
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`3-D MULTICHIP PACKAGING FOR MEMORY MODULES
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`by
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`Robert T. Crowley and E. Ian Vardaman
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`TechSearch International, Inc.
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`9430 Research Blvd., Bldg. 4, Suite 400
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`Austin, Texas 78759 USA
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`Tel: (512)343-4508 Fax: (512) 343-4509
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`Abstract
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`High density memory packaging is important for high performance computing systems and for
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`small size memory systems.
`Smaller single chip packages as well as multichip packages have been
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`Three-dimensional
`(3-D) packaging is another
`technique that
`developed for
`these applications.
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`provides size and performance benefits. Memory chips are well suited to 3-D stacking techniques due to
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`the relatively low number of I/O terminals,
`the ability to share many common signal
`lines, and low
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`power dissipation. This paper presents an analysis of recent worldwide developments in 3-D multichip
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`packaging for memory modules, including analyses of assembly processes and vertical interconnection.
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`Key Words: 3-D, Stacked, Memory, Vertical, Interconnection
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`Introduction
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`Performance and size are the driving factors
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`for memory subsystems in many applications.
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`Smaller single chip packages, such as the thin
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`small outline package (TSOP) and the ball grid
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`array (BGA) package, help to shrink the amount
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`of board space required for memory chips. As
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`these chips are mounted closer to the processor in
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`computer applications, the signal propagation
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`time decreases.
`Planar multichip module
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`assembly has been used to further decrease the
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`amount of area and the chip-to-chip spacing.
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`Three-dimensional (3-D) packaging techniques
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`have been developed to provide even greater
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`packaging efficiencies for applications in space,
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`defense, and computing. Our research has
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`identified more than 30 companies that have
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`developed 3-D packaging solutions, most aimed
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`at memory packaging. These techniques include
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`stacked packaged chips, laminated bare chips,
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`stacked 2-D MCMS, stacked wafers, and folded
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`flex circuits.
`In some cases, these 3-D modules
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`incorporate multiple conventional 2-D modules.
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`In other cases, multiple chips are assembled into
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`a stack that can be mounted on a conventional
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`MCM.
`In either case, memory stacking will be
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`important to MCM assembly either as an end
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`application for MCMS or as components for MCM
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`assembly.
`This paper describes the key
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`applications for memory stacking; compares the
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`assembly processes, volumetric efficiency, and
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`vertical
`interconnection techniques for 3-D
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`multichip memory modules; and reviews the
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`current status of the industry infrastructure.
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`Applications
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`Three-dimensional packaging techniques
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`have been developed for many non-memory
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`applications
`including focal plane array
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`detectors that contain as many as 64 signal
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`processor chips in one stack, and parallel
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`processor computer architectures based on stacked
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`MCM technology.
`and military
`Space
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`applications have been instrumental
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`development of 3-D technology, often under
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`ARPA funding. However, computer applications
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`SAMSUNG ET AL. EXHIBIT 1057
`Page 1 of 6
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`MCM ’94 Proceedings
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`3-D MULTICHIP PACKAGING FOR MEMORY MODULES
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`by R.T. Crowley and EJ. Vardaman
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`from memory chip stacking size reductions in
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`addition to performance improvements. Texas
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`Instruments uses memory stacks on Aladdin
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`processor MCMs and dual C30 DSP modules [2].
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`Irvine Sensors, in cooperation with nCUBE and
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`NASA's Jet Propulsion Lab, developed a memory
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`stack that is integrated into a compact node for a
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`massively parallel processor computer [3].
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`Most applications use stacks with four to
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`nine memory chips. Both bare chip stacks (e.g.
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`Irvine Sensors, Texas Instruments, and Thomson-
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`CSF) or packaged chip stacks (e.g. Dense-Pac
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`Microsystems, Fujitsu, Mitsubishi, RTB
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`Technology, and Staktek) can be used. However,
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`the major barrier is cost.
`If 3-D technology does
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`not become cost competitive with single chip
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`packages and SIMMs, it will not be adopted.
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`Memory Cards
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`PCMCIA cards have tight restrictions on
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`thickness and size. Bare die stacking can
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`quadruple the memory storage density.
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`Matsushita has developed a process using
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`stacked TAB technology to build memory cards
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`IBM has licensed Irvine Sensors technology
`[4].
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`and could incorporate this into future memory
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`cards.
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`Solid State Disk Drives
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`Memory stacking can be used for solid state
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`disk drives that offer higher speed than rotating
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`storage devices. At least three companies are
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`investigating stacked wafer technologies in an
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`effort to make this product a reality.
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`3-D Techniques
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`Three fundamental packaging techniques
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`have been developed for 3-D assemblies:
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`packaged chips, bare chips, and multichip
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`modules. Other techniques that have not been
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`commercialized yet include stacked wafers and
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`folded flex circuitry. TechSearch International
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`will drive the technology into commercial
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`production. The major applications for 3-D
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`memory are all related to memory stacking:
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`secondary cache memory, SIMM replacements for
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`DRAM storage, solid state disk drives, and high
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`density PCMCIA memory cards.
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`Solid State Data Recorders
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`Observation satellites generate a large
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`amount of data that must be stored and then
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`transmitted back to earth. Electromechanical
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`recorders are being replaced by solid state data
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`recorders for several reasons including:
`less
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`vibration, smaller size, less mass, and greater
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`data storage and retrieval flexibility. To image
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`a 60 km x 60 km area with 1.8 meter resolution, 10
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`Gbits of data storage are required with a 100
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`Mbit/ sec data rate. Matra Marconi Space France
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`plans to assemble 10 Gbit recorders in 1994 and
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`lTbit recorders by 2002 for this application [1].
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`Several other companies have developed solid
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`state data recorder technology based on 3-D
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`memory stacking technology including Texas
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`Instruments, General Electric, and Harris. Each
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`of these companies has chosen a unique stacking
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`approach including stacked bare die, stacked
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`MCMs, and stacked packages.
`Today's
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`technology requires more than one thousand
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`1Mbit chips to make a 1Gbit recorder, while
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`future systems may use sixteen thousand 64Mbit
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`chips for a lTbit recorder. Hermetic enclosures
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`are required for space operation. This can be
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`implemented at the single chip level, complete
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`recorder level, or an intermediate level.
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`Processor Memory Stacks
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`Computer processor chips and digital signal
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`processing (DSP) chips require high—speed
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`memory located near the processor. High
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`performance workstation applications can benefit
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`from the reduced cache memory access times made
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`possible by memory stacking. Sun Microsystems
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`recently incorporated cache memory stacks on a
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`server's processor board. Smart weapons benefit
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`SAMSUNG ET AL. EXHIBIT 1057
`Page 2 of 6
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`MCM ’94 Proceedings
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`3-D MULTICHIP PACKAGING FOR MEMORY MODULES
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`by R.T. Crowley and E.]. Vardaman
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`has
`that have
`identified 27 companies
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`investigated 3-D packaging techniques with
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`eleven companies in production; most are still in
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`the R&D phase [5].
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`Stacked Packages
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`Packaged chip assembly techniques include
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`standard packages and custom packages.
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`Thomson—CSF and Mitsubishi have developed
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`stacking techniques using standard TSOPs to
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`provide low cost memory stacks. Thomson-CSF
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`mounts TSOPs to copper lead frames, stacks the
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`packages, and then molds the stack in plastic [6].
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`The stack is sawed into a cube, and the edges of
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`the stack are interconnected by laser patterning a
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`metal layer deposited on the surface of the cube.
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`Mitsubishi stacks TSOP packages and solders the
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`leads to a pair of printed circuit boards on each
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`side of the stack [7]. For hermetic applications,
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`ceramic leadless chip carrier (LCC) packages can
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`be stacked as done by Dense-Pac Microsystems.
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`Harris has developed a low temperature cofired
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`ceramic (LTCC) tub that can hold two memory
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`chips. The tubs are stacked in such a way as to
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`hermetically seal each layer [8].
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`To increase density even further, several
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`custom packages have been developed for
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`stacking memory chips. Dense-Pac Microsystems
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`has developed a non-hermetic stackable package
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`that uses a 2-layer LTCC substrate. The IC is
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`glued to the ceramic and interconnected with wire
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`bonding [9]. This process is limited to low I/O ICS
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`such as memory chips. RTB Technology and
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`Staktek Corporation have developed similar
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`plastic packages for stacking memory chips.
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`Hitachi has developed a unique stackable chip
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`for high density memory stacking.
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`Individual TCPS are bonded to printed circuit
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`board (PCB) frames [10]. Each frame is slightly
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`larger than the chip and has a window punched
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`out of the middle such that the top surface of the
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`chip is flush with the top of the PCB. This
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`minimizes the stack height.
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`Stacked Bare Die ‘
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`Even greater density can be obtained by
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`stacking bare die. Several techniques have been
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`developed by Irvine Sensors, Texas Instruments,
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`Thomson-CSF, Matsushita Electric Industrial,
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`and Fujitsu. Irvine Sensors laminates several thin
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`chips into a cube and then uses a thin film
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`deposition and patterning process to interconnect
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`the chips along one or more faces of the cube [11].
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`The key to this technology is Irvine's ”T-connect”
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`between the thin film metal on the surface of the
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`chip and the thin film metal on the face of the
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`cube. Texas Instruments also routes the signals to
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`one edge of the IC, but uses TAB leads to create
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`metal studs that extend beyond the edge of the
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`chip. These studs are soldered to a silicon
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`substrate for interconnection. Thomson—CSF uses a
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`sacrificial TAB tape frame as a lead frame. The
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`IC is wire bonded to the tape, and then processed
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`similar to the stacked TSOP discussed above.
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`Matsushita and Fujitsu have developed stacked
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`TCP techniques. Matsushita bonds the TCP stack
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`to a PCB while Fujitsu bonds the TCPs to a copper
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`lead frame.
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`Stacked MCMs
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`Bare die can be mounted on multichip
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`modules which are then stacked vertically to
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`create high density general purpose electronics
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`systems and mass memory systems. AT&T, E-
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`Systems, General Electric, Hughes, Matra
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`Marconi Space France, Matsushita Electronic
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`Components, and Motorola have all developed
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`stacking technologies for multichip modules.
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`GE extended its chips-first HDI process into
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`the third dimension by stacking MCMs and
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`applying thin film interconnection layers along
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`one or more edges of the stack [12]. GE built a 40
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`Mbyte memory stack prototype containing twenty
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`16Mbit DRAMs using three 2-D HDI substrates.
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`Matra Marconi Space France developed a
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`hybrid bare die/MCM approach for solid state
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`SAMSUNG ET AL. EXHIBIT 1057
`Page 3 of 6
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`

`
`MCM ‘Q4 Proceedings
`
`3-D MULTICHIP PACKAGING FOR MEMORY MODULES
`
`by R.T. Crowley and EJ. Vardaman
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`recorders. Two chips are wire bonded to an MCM
`substrate, and then two more chips are laid on top
`but rotated 90 degrees.
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`Matsushita has developed a stacked MCM
`technology suitable for memory systems [13]. A
`16Mbyte DRAM module was constructed using 32
`4Mbit DRAMS. Eight glass substrate MCM layers
`were stacked to create a module measuring 26mm
`x 26mm x 19mm. Each layer contains 4 DRAMS
`and 4 chip capacitors. The MCMs are vertically
`interconnected by soldering the C-shaped QFP
`lead frames to each other.
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`Stacked Wafers
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`Wafer stacking is being investigated by at
`least three U.S. companies. Undiced wafers can
`be stacked without dicing the wafers into chips.
`Several technical issues need to be addressed
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`with this technology including electrical wafer
`feedthroughs, reliable wafer-to-wafer inter-
`connection, and fault tolerancy for defective ICs.
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`Flex Circuit Structures
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`technique involves flex
`Another novel
`circuitry. Multiple [Cs can be bonded to one piece
`of flex circuit and then folded or stacked to create
`
`a compact 3-D memory structure. At least three
`companies are investigating this today, including
`Harris, MCC, and MMS. Harris has developed a
`folded flex circuit technique suitable for memory
`stacking. Memory chips are bonded to the flex
`circuit which is then folded to create a compact
`structure. The flex circuit provides the first-level
`connection to the chip, the chip-to-chip vertical
`interconnection, and the flex connector for the
`entire stack.
`
`Volumetric Efficiency
`
`All of the bare chip and packaged chip
`stacking technologies have been used for memory
`chip stacking, while only three of the MCM
`stacking techniques have been used for memories.
`
`477
`
`I Stacked Bare Die
`
`Stacked Packaged Die
`
`k\\\\\\\\\\\\\\\\\\\‘
`
`x\\\\\\\\\\\\\\\\\\\\‘\\\\\\\\\\\\\\\\.\\\\\\‘\\\\\\\\\\‘
`
`200
`
`600
`400
`Volume (cubic mm/chip)
`
`800
`
`Figure 1. Bare chip stacks are most dense,
`followed by custom packages, multichip modules,
`and standard chip packages.
`
`Volumetric efficiency is easier to compare for
`memory circuits than for image processor or
`microprocessor circuitry. The relative volume of
`memory stacks are compared in figure 1. This
`chart was generated by dividing the volume of a
`stack by the number of chips in the stack. Most
`modules used 1Mbit SRAMS or 4Mbit DRAMS,
`
`SAMSUNG ET AL. EXHIBIT 1057
`
`Page 4 of 6
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`

`
`
`
`MCM ’94 Proceedings
`
`
`
`
`
`
`
`
`
`3-D MULTICHIP PACKAGING FOR MEMORY MODULES
`
`
`
`
`
`
`by R.T. Crowley and EJ. Vardaman
`
`
`
`
`
`
`
`
`The
`although there are a few exceptions.
`
`
`
`
`
`
`
`
`minimum volume of a technology depends on the
`
`
`
`
`
`
`
`
`size and thickness of the chip, and each company
`
`
`
`
`
`
`
`
`used different chips. Therefore, it is difficult to
`
`
`
`
`
`
`make direct comparisons between two companies.
`
`
`
`
`
`
`
`However, the figure does highlight the relative
`
`
`
`
`
`
`
`density of the different 3-D techniques. Stacked
`
`
`
`
`
`
`
`
`
`bare die is most dense, but requires the most
`
`
`
`
`complicated manufacturing process. Custom
`
`
`
`
`
`
`packages, designed for stacking, simplify the
`
`
`
`
`
`manufacturing process (test, burn-in, and
`
`
`
`
`
`
`
`handling) and can provide comparable density to
`
`
`
`
`
`
`
`bare chip stacks. Stacked MCMs require more
`
`
`
`
`
`
`
`volume per chip than custom packages. Standard
`
`
`
`
`
`
`
`packages (LCCS and TSOPS) produce the largest
`
`modules.
`
`
`
`Vertical Interconnection
`
`
`
`
`
`
`Vertical interconnection is a critical design
`
`
`
`
`
`
`
`issue for 3-D packaging. Various techniques have
`
`
`
`
`
`
`been developed including thin film metal
`
`
`
`
`
`deposition and patterning, solder dipped
`
`
`
`
`connections, laser-rnachined conductors, Z-axis
`
`
`
`
`
`conductive polymers, printed circuit boards,
`
`
`
`
`
`
`
`
`metal pins, solder balls, TAB tape, and fuzz
`
`buttons.
`
`
`
`
`
`
`Vertical interconnection techniques can be
`
`
`
`
`
`
`classified as peripheral connections or array
`
`
`
`
`
`connections. Peripheral connections require that
`
`
`
`
`
`
`
`
`
`
`
`all signals be routed to the edge of the stack and
`
`
`
`
`
`
`
`then routed from layer
`to layer. Many
`
`
`
`
`
`
`peripheral techniques are limited even further
`
`
`
`
`
`
`
`because each vertical path must be shared
`
`
`
`
`
`
`
`
`between all the layers. This is acceptable for
`
`
`
`
`
`
`stacked memory applications but not mixed
`
`
`
`
`circuitry applications.
`Array connection
`
`
`
`
`
`
`
`techniques allow for more vertical channels than
`
`
`
`
`
`peripheral connections. Furthermore, many array
`
`
`
`
`
`
`techniques allow custom placement of the
`
`
`
`
`
`
`
`vertical connections for each layer for maximum
`
`flexibility.
`
`
`Soldered Connections
`
`
`
`
`
`
`
`
`
`Soldered connections are the most common
`
`
`
`
`
`approach for stack interconnection. However,
`
`
`
`
`
`
`many different techniques have been developed.
`
`
`
`
`
`
`Dense-Pac Microsystems uses a solder dipping
`
`
`
`
`
`
`
`process to interconnect the castellated edges of
`
`
`
`
`
`
`
`
`the stack. Matsushita and Fujitsu use a hot bar
`
`
`
`
`
`
`
`soldering process to interconnect two to four layers
`
`
`
`
`
`
`of TAB—mounted memory chips. Hitachi joins
`
`
`
`
`
`PWB frames
`together with solder-filled
`
`
`
`
`
`through-holes. Matsushita solders the formed
`
`
`
`
`
`
`
`lead frames for stacked MCMS. Motorola has
`
`
`
`
`
`
`
`developed a process for stacking BGA modules
`
`
`
`
`
`
`
`
`
`using solder balls on both sides of the substrate.
`
`
`
`
`
`
`
`Staktek and RTB Technology use pins inserted
`
`
`
`
`
`
`
`
`and soldered through the leads on each package
`
`
`
`
`
`
`
`in the stack. Texas Instruments and Mitsubishi
`
`
`
`
`
`
`use 2-D interconnecting substrates (silicon MCM
`
`
`
`
`
`
`
`
`and PWB respectively) that are soldered to the
`
`
`
`
`
`
`leads from each chip or package.
`
`
`
`
`
`Thin Film Cgnnections
`
`
`
`
`
`
`
`Thin film metallization on one or more faces
`
`
`
`
`
`
`of the memory stack provides greater wiring
`
`
`
`
`
`
`density and wiring flexibility than most soldered
`
`
`
`
`
`connections. Irvine Sensors, General Electric, and
`
`
`
`
`
`
`Thomson—CSF all use forms of
`thin film
`
`interconnection.
`
`
`
`
`
`
`
`Infrastructure
`
`
`
`
`
`
`
`
`
`
`The 3-D memory module industry is still in
`
`
`
`
`
`the infancy stage. Many companies have
`
`
`
`
`
`developed technologies and are building patent
`
`
`
`
`
`
`portfolios for future protection. A few companies
`
`
`
`
`
`offer commercial memory modules or assembly
`
`
`
`
`
`
`
`services, but only in limited volume today. Many
`
`
`
`
`
`companies are offering their technology for
`
`
`
`
`
`
`
`license to other companies. While it is possible
`
`
`
`
`
`
`to buy memory modules, obtain contract assembly,
`
`
`
`
`
`
`and license technology, no applications are using
`
`
`
`
`
`memory stacks in high volume.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1057
`Page 5 of 6
`
`

`
`
`
`MCM ’94 Proceedings
`
`
`
`
`
`
`
`
`
`3-D MULTICHIP PACKAGING FOR MEMORY MODULES
`
`
`
`
`
`
`by R.T. Crowley and E.]. Vardaman
`
`Conclusion
`
`
`
`
`
`
`
`
`Memory stacking offers advantages for
`
`
`
`
`
`space, defense, and computer applications.
`
`
`
`
`
`
`
`
`
`Memory modules can be mounted onto MCMs or can
`
`
`
`
`
`
`
`
`be formed by stacking MCMs. 3-D technology is
`
`
`
`
`
`
`
`well suited to memory application since the
`
`
`
`
`
`
`
`
`
`number of I/O lines is relatively low, and most
`
`
`
`
`
`
`
`
`
`
`lines can be shared with each layer in the stack.
`
`
`
`
`
`
`
`
`
`
`This is most useful for 36-bit wide and 72-bit wide
`
`
`
`
`
`memory organizations. The most promising
`
`
`
`
`
`
`
`applications for memory stacks are cache SRAM
`
`
`
`
`
`
`
`stacks for microprocessors and stacks for PCMCIA
`
`
`
`
`
`
`memory cards. However, the technology will
`
`
`
`
`
`
`never achieve widespread adoption until the
`
`
`
`
`
`
`technology achieves cost parity with plastic
`
`packages.
`
`References
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`M. Massénat, ”High-density package,
`
`
`
`
`
`
`cofired, multichip module, 3D, a mass
`
`
`
`
`
`memory mixed technology for
`space
`
`
`
`
`
`
`
`applications,”
`9th European Hybrid
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`
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`Microelectronics Conference Proceedings, pp.
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`
`
`216-223, Iune 1993.
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`
`
`R. Bruns, W. Chase, and D. Frew, "Utilizing
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`three-dimensional memory packaging and
`
`
`
`
`silicon-on-silicon technology for next
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`
`
`
`generation recording devices," I C M C M
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`
`
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`
`Proceedings, pp. 34-40, April 1992.
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`
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`
`D. Eisenman, R.E. DeCaro, and D.W. Iurasek,
`
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`”Spacecraft on-board information extraction
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`computer (SOBEIC),” Proc. for Technology
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`2003, Dec. 1993.
`
`
`
`
`
`
`
`’’New film carrier
`K. Hatada, et al.,
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`
`
`
`assembly technology-Trasferred bump TAB,"
`
`
`
`
`
`
`IEEE CHMT, Vol. CHMT-10, No. 3, 1987.
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`R.T. Crowley, Three-dimensional electronics
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`
`packaging, Industry report published by
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`
`
`
`Techsearch International, Nov. 1993.
`I
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`
`
`”3—D stacking of TSOP plastic
`C.M. Val,
`
`
`
`
`Proc.
`Intl. Symposium on
`packages,”
`
`
`
`
`
`Microelectronics , ISHM, pp. 370-376, 1992.
`
`
`
`stacked
`"Mitsubishi Electric develops
`
`
`
`
`
`
`memory module,” Denshi Zairyo,, Iune 1993.
`
`
`
`
`
`
`"3-D
`E.G. Palmer and C.M. Newton,
`
`
`
`
`
`packaging using low temperature co-fired
`
`
`
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`
`ceramic (LTCC),” Proc. of Intl. Conf. on
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`
`Multichip Modules, pp. 307-312, Apr. 1993.
`
`
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`
`
`J. Forthum and C. Belady, ”3-D memory for
`
`
`
`
`
`improved system performance," Proc. 1992
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`
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`
`Intl Elect. Packaging Conf., pp. 667-677, 1992.
`
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`
`I. Miyano, K. Serizawa, S. Sakaguchi, T.
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`Ishida, M. Yamada, and T. Kudaishi,
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`”Fabrication and thermal analysis of 3
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`
`dimensionally located LS1 packages," 9th
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`European Hybrid Microelectronics Conference
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`Proceedings, pp. 184-191, June 1993.
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`
`. ].A. Ninaham, A. Pepe, R. Some, and M. Suer,
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`"The 3-D stack in short
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`Electronics Camp. and Tech. Conf. pp. 340-
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`344, 1992.
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`[10]
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`
`
`
`
`
`
`
`. G.A. Forrnan, et al. "GE 3-D HDI stacked
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`multichip module technology's impact on
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`
`
`
`system design," Proc. of 1993 Nepcon Conf., pp
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`
`1206-1215, Feb. 1993.
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`. Katsumi Kohzu, Takeo Yasuho, Hirofumi
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`
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`
`Tajika, ”Mega Module packaging technology:
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`The lead frame for the multichip module,”
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`Institute
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`Engineers, (in Japanese), pp. 19-24, 1993.
`
`
`
`SAMSUNG ET AL. EXHIBIT 1057
`Page 6 of 6