QT}-I SYMPOSIUM ON FUTURE ELECTRON DEVICES
`November 14-15. 1990 Makuhari. Chiba. Japan pp. 267.272
`
`EVALUATION OF CUBIC (CUMULATIVELY BONDED KC) DEVICES
`
`Yoshihiro HAYASHI
`Microelectronics Research Laboratories. NEC Corporation
`1 120, Shimolcuzawa, Sagamihanz Kanagaws 229, Japan
`
`ABSTRACT
`
`Thin film device layer bonding technology. referred as to Cumulatively
`bonded
`1C I CUBIC J
`technology, has been developed for 3D-IC fabrication.
`Advantages
`of the CUBIC technology are its ability to make device
`layers
`independently on
`the Si—substrates using a
`conventional
`IC
`fabrication
`process.
`the lack of heat damage during the device bonding process. and its
`short process turn around time.
`In this paper. concept of CUBIC technology
`and
`key process technologies involved are described in detail.
`and
`its
`application to future electron device fabrications will be discussed.
`
`;.
`
`INTRODUCTIQN
`
`In the field of system which consists of a large amount of electronic
`functional blocks.
`the packaging density has been the major impetus to
`the
`system performance improvement.
`A lot of technical approaches to attaining
`high packaging density have been proposedil-2].
`Among
`them is
`three
`dimensional
`IC fabrication. where several device layers are stacked in
`the
`vertical direction.
`
`(Silicon-On-Insulator)
`[Cs are made by repeated SDI
`Three dimensional
`To obtain the S01
`film.
`formation and device fabrication on the S01 film.
`and
`recrystallized by
`a polysilicon film on silicon dioxide is melted
`scanned laser beam or electron beam. However. serious problems in the
`SD-
`IC
`fabrication process. hereafter
`called as
`"beam
`recrystallization
`method".
`are pointed out[5.4]. First. with
`increasing the
`number
`of
`stacking layers.
`quality control
`of the
`501
`film becomes difficult.
`Second. underlying device layers suffer from hoat—damage during upper layer
`device
`fabrication.
`Furthermore. a long process turn around time { TAT
`)
`and
`low productivity also restrict mass production of
`3D-Ics
`since
`the
`number of process steps extremely increases with the device layer.
`In
`this
`paper, a new SD-IC fabrication technology.
`referred to as
`( CUmulstively Bonded IC J
`technology is proposed. and
`its
`future
`CUBIC
`applications are described.
`
`E; Concept 9; CUBIQ technology
`
`CUBIC
`The
`illustrates the concept of CUBIC technology[5].
`1
`Figure
`bonding
`involves
`the device thinning process and the device
`technology
`process. First.
`the lat. 2nd and 3rd device layers are made
`independently
`on
`bulk Si substrates using a conventional
`IC fabrication process.
`Next.
`the
`silicon crystals underlying the
`2nd
`and
`3rd
`device
`layers
`are
`eliminated to obtain thin film devices.
`Then. vertical wirings
`are made
`for
`signal
`and
`power
`transmission from the front
`surface
`to
`the
`back
`surface
`of
`the
`thin film devices. Finally.
`the thin film devices
`are
`bonded mechanically and electrically.
`The CUBIC technology has a lot of advantages superior to the ordinary
`3D—IC fabrication technology using a beam recrystallization method.
`one of
`the most attractive advantages of the CUBIC technology is its ability to
`make the device layers independently on bulk Si-substrates.
`thus shortening
`the process TAT of 3D-IC fabrication.
`The other
`advantage of
`the
`CUBIC
`technology
`is
`the
`lack of heat damage because of a
`low device
`bonding
`temperature.
`Thus.
`the CUBIC technology is expected to be
`applicable
`to
`the SD-IC fabrication having a large number of stacking device layers.
`
`SAMSUNG ET AL. EXHIBIT 1055
`Page 1 of 6
`
`

`
`9TH SYMPOSIUM ON FUTURE ELECTRON DEVICES
`November 14-15. 1990 Makuhari. Chiba. Japan pp. 357.213
`
`Q; Key technologies
`
`how to
`the key issues are
`In order to realize the CUBIC technology.
`obtain thin film devices, make electrical path from the front
`surface
`to
`the
`back
`surface of the thin film devices.
`and make device-to-device
`electrical
`interconnections in the bonded structure.
`In this section.
`the
`technologies which were developed to solve these issues are described.
`
`3-1. Device thinning
`
`polishing
`preferential
`film devices were obtained using
`Thin
`technique{B.7] as shown in Figure 2. First. a backing substrate is adhered
`to
`the
`device
`surface of the silicon wafer.
`Then. most
`of
`silicon
`underlying the device layer is eliminated by grinding. and
`the
`residual
`Dart
`(50-l00um)
`is removed by preferential polishing.
`The preferential
`polishing proceeds with the following two steps:
`(
`1
`} silicon reacts with
`the polishing liquid such as organic amine
`solution.
`producing
`silicon
`hydrate.
`and
`{
`2
`J
`the silicon hydrate is
`removed mechanically
`by
`a
`polishing pad.
`Since no reaction occurs between S102 and
`the polishing
`liquid.
`the polishing stops automatically at
`the LOCOS back surface( SiO2 J
`to give a thin film device.
`Figure 3 shows photographs of a NMOSFET formed
`on
`silicon substrate and the back-surface view of the thin
`film NMOSFET
`obtained.
`The
`thin film device layer. with the thickness
`of
`2um. was
`mechanically stable because of the backing substrate support.
`
`3-2. Back surface wiring
`
`The electrical paths from the front surface to the back surface or the
`thin film device were made using the back surface wiring technology. After
`the preferential polishing ( see Figure 3 ).
`the poly-Si
`and Mosi
`/Al
`patterns
`on
`the LOCOS front surface become visible from the
`LOCOS
`ack
`surface.
`thus
`enabling us to make the back surface patterns which
`are
`aligned with the front surface patterns. Namely.
`through-hole patterns and
`back surface w/Al wiring patterns are made on the LOCOS back surface.
`Figure
`4
`shows
`.the patterns used
`for
`confirmation of electrical
`interconnection between
`the poly-Si wirings and the
`back
`surface U/A1
`wirings.
`The through—ho1e size was 2umx2um.
`The contact
`array obtained
`revealed an ohmic-contact property. an
`the cogtact resistance between
`the
`poly-Si and the H/Al wirings was 3x10
`[ohm'cm ]
`
`3-3. Bump/pool Contact
`
`the
`interconnections were made using
`Device-to-device electrical
`as shown in Figure
`5.
`The
`bonding
`“bump/pool
`contact“
`techno1ogy[8]
`mechanism is as the follows. At first.
`tungsten bumps. which are
`a
`high
`melting point
`conductive material. are formed
`on
`the
`polyimide—coated
`device
`layer.
`Au/In pools. where the alloy with low melting point
`is
`partially plugged
`in the polyimide film. are formed on the other device
`layer.
`These
`two layers are aligned by infrared microscopy with
`the
`N
`bumps
`just over the Au/In pools.
`then heated above melting temperature of
`the Au/In alloy and put together.
`The device layers bond to each other due
`to the solid phase fixing force between the bumps and the pools. giving the
`device—to—devics electrical interconnections.
`In addition.
`the polyimide to
`polyimide
`adhesion force helps the mechanical bonding between
`the device
`layers.
`fine—pitch
`making
`for
`advantageous
`is
`contact
`bump/pool
`The
`interconnection because the molten Au/In alloy doesn't overflow during
`the
`bonding.
`The
`low bonding temperature below 400'C prevents
`the device
`layers from heat-damage.
`The third advantage is that
`the bump/Pool contact
`has
`a stable bonding structure with not only horizontal but also vertical
`bonding tolerances.
`The horizontal and vertical
`tolerances are determined
`essentially by the resolving power of infrared microscopy and by the
`bump
`height. At
`the present
`time.
`the horizontal and vertical
`tolerances are of
`:3um and :1.5um. respectively.
`electrical
`confirming
`for
`used
`Figure
`6
`shows
`the patterns
`interconnection between
`the Mosiz/Al wiring and the W/Al wiring
`by
`the
`
`SAMSUNG ET AL. EXHIBIT 1055
`Page 2 of 6
`
`

`
`9TH SYMPOSIUM ON FUTURE ELECTRON DEVICES
`November 14.15. 1990 Makuiari. Chiba. Japan 911.267-272
`
`the MoSi2/Al patterns on the one Si-
`technology. Here.
`contact
`bump/pool
`( Fig. 8(a)
`J were aligned with the W/Al patterns on
`the other
`substrste
`si—sub3trate
`( Fig. 6(b)
`).
`As shown in Figure 6(c},
`1.600
`links were
`electrically connected in the contact array with the bumps and the pools.
`The
`bump/pool contact revealed an ohmic contact pgoperty. End the
`contact
`resistance between the bump and the pool was 5x10
`[ohm cm ].
`
`14 Evaluation and gpplication
`
`layered
`active
`evaluate the CUBIC technology. a dual
`to
`In order
`layered
`device was fabricated.
`Figure 7 shows the steps for a dual active
`the
`device
`fabrication using
`CUBIC
`technology. which
`consists of
`contact
`preferential polishing.
`the back surface wiring. and the bump/pool
`technologies. First. NMOSFETs for the lat
`(
`lower ) and the 2nd ( upper
`}
`layers
`are
`fabricated independently on silicon substrates.
`and
`then
`w
`bumps.
`the size of 2umx2um and the height of 2.0um. are fabricated on
`the
`Mosiz/Al wirings. After the backing substrate adhesion on the 2nd device
`layer
`( Fig.
`7(a)
`).
`the silicon underlying
`the
`2nd device
`layer
`is
`removed
`by grinding and preferential polishing ( Fig.
`7{b)
`).
`Then.
`through-holes.
`the
`size of 3umx3um, back surface U/Al wirings
`and Au/In
`pools.
`the size of Bumxaum and the depth of 2.5um . are formed on the
`back
`surface ( Fig. ?(c) J.
`The thin film device obtained is used as a building
`block. Note that
`the pools on the back surface are electrically connected
`to
`the
`bumps. Next.
`the thin film NMOSFET for the 2nd layer
`is
`aligned
`over the bulk NMOSFET for the lat layer using infrared microscopy. and then
`pressed together
`( Fig. 7(d) J.
`The thin film NMOSFET
`is electrically
`interconnected to the bulk NMOSFET by the bump/pool contacts. Finally.
`the
`backing
`substrate
`and
`the adhesive on the 2nd
`NMOSFET
`are
`removed
`by
`etching ( Fig. 7(a)).
`active
`the dual
`photograph and schematic view of
`Figure
`8
`shows
`layered device obtained.
`The source and gate of the thin film NMOSFET
`(
`the
`End
`layer
`) were electrically interconnected to those
`of
`the
`bulk
`(
`NMOSFET
`the 1st layer )
`through the bump/pool contacts.
`The drains.
`on
`the other hand. were not connected each other.
`The drain currents of
`the
`thin film NMOSFET were lower than those of the bulk NMOSFETIQJ as shown
`in
`Figure 9. Optimization of the preferential polishing will
`improve the thin
`film NMDSFET performance by reducing stress and/or crystal defects in
`the
`active
`silicon device ares. Consequently. it is proved
`that
`the
`CUBIC
`technology
`is really applicable for making SD-IC fabrication even
`though
`minor process refining is still needed.
`to
`Figure 10 illustrates application examples of the CUBIC technology
`as
`future
`electron device
`fabrications.
`Hulti—functional
`3D-IC such
`vertical stacking of memory and processor blocks will be realized with high
`production yield by using CUBIC
`technology
`(
`Fig.
`10(a}
`).
`High
`performance multi
`layered
`IC will be fabricated by
`stacking thin film
`inter-CMOS devices as building blocks ( Figure 10(bJ
`). since
`the
`inter-
`CMOS devices.
`in which
`PMDSFET is
`located above
`NMOSFET.
`have many
`advantages of lstch—up-free structure and less photomssks required for
`ion
`implantation process steps[10].
`
`fié Summary
`
`has
`CUBIC technolofiv. which is a thin film device bonding technology.
`been developed.
`The
`thin film devices
`are made using preferential
`polishing technoloE3-
`the vertical interconnections from the front
`surface
`of
`the
`thin film device to the back surface are made using back
`surface
`wiring technology. and the device-to-device interconnections in the bonding
`structure are made by bump/pool contacts.
`The
`advantages
`of CUBIC technology are its ability to make device
`layers
`independently on bulk
`Si
`substrates
`using a
`conventional
`[C
`fabrication process.
`the lack of heat damage, and its short
`process
`TAT.
`Thus. CUBIC technology will be applicable to mass production of many kinds
`of 3D-1C possible.
`
`REFERENCES
`
`CR’-ID.."-'U"lD-‘|:3:'¢-'I#3£.I-0|!
`
`
`
`
`
`I'D‘-'""a'OCL|-'r*|'D@'-'.'l"mOl.'D@"‘a:¢DI.I:l\'-1-'.3'Wl‘D
`
`SAMSUNG ET AL. EXHIBIT 1055
`Page 3 of 6
`
`

`
`‘JTH SY-.'\-IPUSIUM ON FUTURE ELF.CTR0.‘I' DEVICES
`November H-15. 1990 hlakilhari. Chiba. Japan pp.36‘_,I_2‘,r2
`
`Kunio. Proc.
`
`345I 6
`((CKIIII
`
`S. Samukawa et. a1.. 1950 VLSI Symp.
`1)
`Digest of technical paper.
`ppl(1990}.
`J. K. Hagge.
`IEEE Trans.
`2)
`Components. Hydrides and Manufacturing. Vol.
`}MT-12. No. 2. pp170{l9B9].
`pp55(19B9).
`flth Symp. on Future Electron Devices.
`) M. Koyanagi. Proc.
`) T. Kunio. et. al.. 1989 IEDH Techn.
`pp837{198B).
`'
`Digest.
`)
`Y. Rayashi. et. 31..
`1990 Symp. on VLSI Techn . Digest of Techn. Paper.pp95
`990).
`at. 31..
`J
`T. Hamaguchi.
`1935 IEDM Techn. Digest, pp638(l985}.
`31..
`Extended Abstract of the 8th Intl.
`{7)
`S. Nada. et.
`Workshop on Future
`Electron Devices.
`pp8l(J990).
`1990);
`(3)
`Y. Hayeehi. et. el.. Extended Abstracts {The 37th Spring Heating.
`pp593(1990)_
`The Japan Society of Applied Physics and Related Society. No. 2.
`BE.
`(9)
`S. Takahashi.
`al.. Proc.
`1890 IEEE SOS/SOI Technology Conference.
`in press.
`(10)
`T.
`
`7th Symposium on Future Electron Devices.
`
`pplQ?(l9B8}.
`
`1sl device
`
`2nd device
`
`3rd device
`V
`J‘I'IN"‘‘X
`x\\\\\\\\\. ‘
`
`Zflflfifldfifi
`
`:;;g
`aaazzaaa
`nmmannwf
`
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`
`WNHHfl-
`46G2Z%92*
`
`technologies;
`
`Device thinning.
`
`vertical wiring through
`the thinned device layers.
`
`Deuice—to-device alignment
`and bonding.
`
`Concept of
`1
`Figure
`technologies involved.
`
`the
`
`CUBIC
`
`technology
`
`and
`
`the
`
`key
`
`PnHshin_
`
`Id
`
`|“““““l‘!lIl!!!Ill
`
`Mechanism:
`
`(1) Silicon reacts with
`polishing liquid such
`as amine solution,
`forming silicon hydrate.
`(2) The silicon hydrate is
`removed mechanically by
`the polishing pad.
`
`Figure 2
`
`Device thinning process using "preferential polishing”.
`
`M0812/Al
`
`Po1y—Si
`
`Po1y—Si
`
`Back surface
`
`3
`
`Figure
`Photographs of (3) NMOSFET formed on a bulk
`and
`(b)
`the back surface View of the thin film NHOSFET
`"preferential polishing“.
`
`Si-substrate
`obtained by
`
`SAMSUNG ET AL. EXHIBIT 1055
`Page 4 of 6
`
`

`
`‘.*TI{ ':i‘I’lII'0.‘§l1.'\.I{)_‘J FLVTUHF. E|I.EL“.[ROE\' LIi:'\'1CEb'
`. Nuvember 1-1-13. 199'} Mal-Iuhari. Chiba, Japan pp 351.173
`
`Sll Slffilfi
`
`_§§
`
`Pregetentiai
`- ollshing
`
`&§§fi$fi§§$
`an new mm
`
`Figure 4
`
`Sequence of back-surface wiring process steps.
`
`Device layer
`
`.
`
`§i§%§
`'
`2zzzzzaw'4naununa
`
`Device layer
`
`sectional
`cross
`Schematic
`5
`Figure
`interconnection using a bump/pool contact.
`(c)
`
`f-M0812/A1
`
`views
`
`0!‘
`
`device-to-device
`
`EEIIIIIIIIINIIIIII
`
`Au/In pool
`
`EX
`SEM photographs of‘ (a) H bumps on Mosiz/Al wiringe.
`lb) Au/In
`6
`Figure
`pools on N/A1 wirings. and (e) schematic cross sectional view and infrared-
`photograph
`of
`the
`flevice—Lo-device
`interconnections
`using
`bump/pool
`contacts.
`
`SAMSUNG ET AL. EXHIBIT 1055
`Page 5 of 6
`
`

`
`‘}'E'I—| S‘i'I\.1PUSIUM ON FUTIJRE ELECTRON DEVICES
`November 1-I-15. 1990 Mai-Luhari. Chiba. Japan pp. 261-272
`
`~ }Tnin Filrn Device
`Auiln Pool '
`
`Back surface wiringv
`Hnmnvll of
`3|°"""9
`
`Device-to-Device
`Interconnection
`
`Through hole
`33°“ 5”"fi‘j1l
`Aufln POO!
`
`_
`
`_
`
`_
`
`'
`
`'
`
`}Thin Flim Device
`}auIk 3: Device
`
`Sequence of the key process steps for a
`7
`Figure
`device fabrication using CUBIC technology.
`
`dual
`
`active
`
`layered
`
`‘lstNMOS
`
`0
`D[1st) D(2nd)
`
`.*"r."
`
`Dual active layered device in which
`Figure 8
`a thin film NMOSFET (the 2nd layer} is stacked
`on a bulk-NMOSFET {the let layer);
`(a) photograph and (b) schematic diagram.
`
`Eler_‘trj_ca[
`B
`Figure
`properties of the thin film
`NMOSFET(the 2nd layer} and
`the bulk NMOSFET {the lat
`layer): L=l.5um. w=50.oum.
`
`Thin mm Inlet-clos
`lovho
`
`Thin film lain-CIOS
`Ilovloo
`
`electron device
`10 Application of the CUBIC technology to future
`Figure
`fabrication:
`ta) Multi-functional device.
`(bl Stacked inter-CMOS device.
`
`SAMSUNG ET AL. EXHIBIT 1055
`Page 6 of 6