United States Patent
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`Itoh et al.
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`[191
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`USO0Sl60998A
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`[11] Patent Number:
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`[45] Date of Patent:
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`5,160,998
`
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`Nov. 3, 1992
`
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`
`[75]
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`[54] SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
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`
`
`
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`
`
`Inventors:
`Junichi Itoli, Inagi; Kazuyuki Kurita,
`Yokohama, both of Japan
`
`
`
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`
`
`Fujitsu Limited, Kanagawa, Japan
`[73] Assignee:
`[2]] Appl. No.2 780,564
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`
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`[22] Filed:
`Oct. 21, 1991
`
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`Related U.S. Application Data
`
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`
`
`Continuation of Ser. No. 233,108, Aug. 15, 1988, aban-
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`cloned.
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`Foreign Application Priority Data
`[30]
`Japan .
`Aug. 18, 1987 [JP]
`............................. 62-203483
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`Int. Cl.5 ............................. .. H01L 29/34
`[51]
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`257/760; 257/633
`[52) us. Cl. .......... ..
`[58] Field of Search ..................... .. 357/71, 54, 52, 40,
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`357/65
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`'
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`[63]
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`
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`
`
`try and Plasma Processing, vol. 7, No. 1 (Mar. 1987), pp.
`109-124.
`
`Machida, Katsuyuki and Hideo Oikawa. “New Planari-
`
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`
`
`
`
`
`
`
`
`
`
`
`zation Technology Using Bias-ECR Plasma Deposi-
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`
`
`
`
`
`tion.” Japanese Journal of Applied Physics. supplements
`17th Conf. on Solid State Devices and Materials Aug.
`
`
`
`
`
`
`
`
`25-27, 1985, pp. 329-332.
`
`
`
`
`
`
`
`
`
`
`
`
`Patent Abstracts of Japan, vol. 6, No. 119 (E-116) [997],
`Jul. 3 1982; and JP—A-57 45 931 (Fujitsu K. K.) Mar. 16,
`
`
`
`
`
`
`
`
`1982.
`
`138
`vol.
`Japan,
`11, No.
`Patent Abstracts of
`
`
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`
`
`
`
`
`
`
`
`
`(E—503)[2585], May 2, 1987; and JP—A-61 279 132
`
`
`
`
`(Sony Corp.) Dec. 9, 1986.
`Extended Abstracts, vol. 87-1, No. 1, Spring 1987, pp.
`
`
`
`
`
`
`
`
`366-367, No. 254, Philiadelphia, Pa. U.S.; M. Doki et
`
`
`
`
`
`
`
`
`a1.: “ECR Plasma CVD of Insulator Films-Low Tem-
`
`
`
`
`
`
`
`perature Process for Ulsi-”.
`
`
`
`
`Patent Abstracts of Japan, vol. 11, No. 390 (E-567)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`[2837], Dec. 19, 1987; and JP-A-62 154 642 (Matsushita
`Electronics Corp.) Sep. 7, 1987.
`
`
`
`
`Primary Examiner—Andrew J. James
`
`
`Assistant Examiner—Sara W. Crane
`
`
`
`Attorney, Agent, or Firm-Nikaido, Marmelstein,
`
`
`
`
`Murray & Oram
`
`
`
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`
`
`ABSTRACT
`[57]
`
`
`A semiconductor device including a semiconductor
`
`
`
`
`
`substrate; a metal wiring layer formed on the semicon-
`
`
`
`
`
`
`
`ductor substrate; a first insulation layer formed on the
`
`
`
`
`
`
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`
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`metal wiring layer,
`the first
`insulation layer being
`formed by a tensile stress insulation layer having a con-
`
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`
`
`
`tracting characteristic relative to the substrate; and a
`
`
`
`
`
`
`
`second insulation layer formed on the first insulation
`
`
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`layer, the second insulation layer being formed by a
`
`
`
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`
`
`
`
`
`
`
`
`
`
`compressive stress insulation layer having an expanding
`characteristic relative to the substrate. The tensile stress
`
`
`
`
`
`
`
`insulation layer is produced by thermal chemical vapor
`
`
`
`
`
`
`
`
`
`
`
`
`deposition or plasma assisted chemical vapor deposition
`which is performed in a discharge frequency range
`
`
`
`
`
`
`
`
`
`
`
`
`higher than 2 megahertz; and the compressive stress
`
`
`
`
`
`
`insulation layer is produced by plasma assisted chemical
`
`
`
`
`
`vapor deposition which is performed in a discharge
`frequency range lower than 2 megahertz.
`
`
`
`
`
`
`-
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`5 Claims, 6 Drawing Sheets
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`
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`
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`432
`
`
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`33
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`31
`
`
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`32
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`
`
`
`[56]
`
`
`
`
`
`
`
`
`" .. 357/54
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`
`
`
`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`.
`1/1979
`4,135,954
`
`
`
`4,365,264 12/1982 Mukai et al.
`
`
`
`4,446,194 5/1984 Candelaria et al. .
`
`
`
`
`4,455,568 6/ 1984 Shiota .............
`4,654,689 3/ 1987 Fujii .........
`.................. .. 357/54 X
`4,825,277 4/ 1989 Mattox et al.
`
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`
`8/1985 European Pat. Off.
`............ .. 357/71
`0152794
`
`
`
`
`
`
`1/1988 European Pat. Off.
`0252l79A1
`.
`
`
`
`
`
`51-117887 10/1976 Japan .
`
`
`
`52-28870
`3/1977 Japan .
`
`
`
`9/1977 Japan .
`52-115785
`
`
`
`55-19850 2/1980 Japan .
`
`
`
`3/1982 Japan .
`57-45931
`
`
`
`0190043 ll/1983 Japan ..................................... 357/71
`
`
`
`
`61-279132 12/1936 Japan .
`
`
`
`OTHER PUBLICATIONS
`
`
`Ghandhi, S. VLSI Fabrication Principles, John Wiley
`
`
`
`
`
`and Sons, 1983, pp. 582-585.
`
`
`
`
`
`Claassen, W. A. P. “Ion Bombardment—Induced Me-
`
`
`
`
`chanical Stress in Plasma—Enhanced Deposited Silicon
`
`
`
`
`
`Nitride and Silicon Oxynitride Films.” Plasma Chemis-
`
`
`
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1050
`Page 1 of 12
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`

`
`U.S. Patent
`
`
`
`
`Nov. 3, 1992
`
`
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`
`Sheet 1 of 6
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`5,160,998
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`Fig. 2
`
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`
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`
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`
`
`Fig. 6
`
`
`
`-> DISCHARGE FREQUENCY
`
`
`
`
`
`
`
`
`
`
`1MHz2MFu
`
`
`.
`
`
`
`
`
`Iowru
`
`
`
`
`
`
`xjx
`
`
`
`
`
`X
`
`"—""-" X
`
`
`__Z><
`
`
`
`
`COMPRESSIVE
`
`E3
`
`O
`
`L O
`
`
`STRESS(10”dyne/cmz) I
`
`
`
`
`
`
`B
`
`SAMSUNG ET AL. EXHIBIT 1050
`Page 2 of 12
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`

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`U.S. Patent
`
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`
`Nov. 3, 1992
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`Sheet 2 of 6
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`5,160,998
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`SAMSUNG ET AL. EXHIBIT 1050
`Page 3 of 12
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`U.S. Patent
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`Sheet 3 of 6
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`5,160,998
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`' Fig. 7(0)
`
`
`
`1
`
`
`
`31
`
`31
`
`
`
`
`F12
`Fig. 7(b)
`\Fig.7(b’)
`
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`
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`31
`
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`
`I
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`1
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`Fig. 7(C)
`
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`
`Fig. 7(c’)
`
`
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`
`31
`
`
`
`412"
`
`411"2
`
`I
`
`
`Fig. 7m’)
`
`
`
`,,
`4'2
`411"
`.2
`
`32
`
`'
`
`31
`
`I
`
`III
`
`31
`
`
`
`
`Fig. 7(d/
`
`32
`
`
`
`412’
`‘$11’
`
`1
`
`.
`2’
`41
`411’
`2
`«
`
`SAMSUNG ET AL. EXHIBIT 1050
`Page 4 of 12
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`

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`U.S. Patent
`
`Nov. 3, 1992
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`Sheet 4 of 6
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`5,160,998
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`Fig. 8(a)
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`Fig. 8 (f)
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`SAMSUNG ET AL. EXHIBIT 1050
`Page 5 of 12
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`U.S. Patent
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`Nov. 3, 1992
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`Sheet 5 of 6
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`5,160,998
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`8
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`TIME
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`( Houm
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`DEFECTGENERATION(=4)
`
`u.
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`L)
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`<
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`
`
`SAMSUNG ET AL. EXHIBIT 1050
`Page 6 of 12
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`

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`U.S. Patent
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`Nov. 3, 1992
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`Sheet 5 of 6
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`5,160,998
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`(I)
`0:
`Lu
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`SAMSUNG ET AL. EXHIBIT 1050
`Page 7 of 12
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`

`
`This application is a continuation of application Ser.
`
`
`
`
`No. 233,108 filed Aug. 15, 1988, abandoned.
`
`
`
`
`
`
`
`BACKGROUND OF THE INVENTION
`
`
`
`(1) Field of the Invention
`
`
`
`
`The present invention relates to a semiconductor
`
`
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`
`
`device and a method of manufacturing the same. More
`
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`particularly, it relates to an improvement of a semicon-
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`ductor device having metal wiring layers and insulation
`
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`layers formed on the metal wiring layers, and an im-
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`provement of the method of manufacturing the same.
`
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`(2) Description of the Related Art
`
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`Generally, in the conventional semiconductor device
`
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`of the above type, the insulation layers formed on the
`
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`metal wiring layers (e.g., aluminum wiring layers) are
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`produced by chemical vapor deposition using insulation
`material such as phosphor silicated glass (PSG).
`
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`In this method, however, during the formation of the
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`above insulation layers, problems have arisen such as a
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`disconnection of the metal wiring layers due to stress
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`migration due to the effect of stress generated in the
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`insulation layers, and cracks in the insulation layers.
`The present invention is intended to solve the above-
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`mentioned problems, and the main object of the present
`invention is to effectively prevent not only the discon-
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`nection of the metal wiring layers due to stress migra-
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`tion but also a generation of cracks in the insulation
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`layers.
`
`15
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`20
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`25
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`30
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`2
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`substrate, and thus, when the tensile stress insulation
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`layer T is formed on the semiconductor substrate 5 as
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`shown in FIG. 1, the tensile stress insulation layer T
`
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`causes the substrate S to bend in a direction such that
`
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`the insulation layer T contracts relative to the substrate
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`S (i.e., a direction such that the insulation layer T com— ,
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`presses the metal wiring layer M formed on the sub-
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`strate S).
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`On the other hand, the compressive stress insulation
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`layer has an expanding characteristic relative to the
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`substrate, and thus, when the compressive stress insula-
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`tion layer C is formed on the semiconductor substrate S
`
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`as shown in FIG. 2, the compressive stress insulation
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`layer C causes the substrate S to bend in a direction such
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`that the insulation layer C expands relative to the sub-
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`strate S (i.e., a direction such that the metal wiring layer
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`M formed on the substrate S is expanded together with
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`the insulation layer C when the metal wiring layer is
`heated by a current flowing therethrough).
`
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`Thus, according to one aspect of the present inven-
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`tion, by forming the tensile stress insulation layer T on
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`the metal wiring layer M as the first insulation layer, the
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`insulation layer T applies stress to the metal wiring
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`layer M, to compress the metal wiring layer as shown in
`
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`FIG. 3, and as a result, a disconnection of the metal
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`wiring layer due to stress migration is prevented. Also,
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`by forming the compressive stress insulation layer C on
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`the first insulation layer T as the second insulation layer,
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`as shown in FIG. 4, the compressive stress insulation
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`layer tends to expand together with the expansion of the
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`metal wiring layer when the metal wiring layer is
`heated, and thus the stress applied by the metal wiring
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`layer to the insulation layer at that time is reduced, and
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`as a result, a generation of cracks in the insulation layer
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`is prevented.
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`Also, according to another aspect of the present in-
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`vention, by forming the tensile stress insulation layers
`
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`on the respective lower side metal wiring layers having
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`a small wiring width (e.g., on the first and the second
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`metal wiring layers), a disconnection of the metal wir-
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`ing layers having a small wiring width due to stress
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`migration is prevented. Also, by forming the compres-
`sive stress insulation layers on the respective upper side
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`metal wiring layers having a large wiring width (e.g.,
`on the third and the fourth metal wiring layers), a gen-
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`eration of cracks in the insulation layers due to the
`
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`expansion of the metal wiring layers having a large
`wiring width is prevented. In this connection, with
`
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`regard to the metal wiring layers having a large wiring
`width, in disconnection thereof due to stress migration
`
`
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`
`
`need not be considered.
`
`
`
`As described in detail below, the tensile stress insula-
`
`
`
`
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`
`
`
`
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`
`
`
`
`
`tion layer may be produced by thermal chemical vapor
`deposition (thermal CVD) or plasma assisted chemical
`
`
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`
`
`
`
`
`
`
`
`vapor deposition (plasma CVD) performed in a dis-
`
`
`
`
`
`
`charge frequency range higher than 2 megahertz. On
`the other hand, the compressive stress insulation layer
`
`
`
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`
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`
`
`
`
`
`
`
`may be produced by plasma assisted chemical vapor
`
`
`
`
`
`
`deposition (plasma CVD) performed in the discharge
`frequency range lower than 2 megahertz. Also, when
`
`
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`
`
`the above tensile stress insulation layer or compressive
`
`
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`stress insulation layer is formed by a particular plasma
`assisted chemical vapor deposition such that the above
`
`
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`
`
`plasma is produced by electron cyclotron resonance
`
`
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`(ECR plasma CVD), the surface of the corresponding
`insulation layer can be made flat, and thus ensure a high
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`reliability of the metal wiring layers formed on the
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`flattened surfaces of the insulation layers.
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`1
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`SEMICONDUCTOR DEVICE AND METHOD OF
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`MANUFACTURING THE SAME
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`5,160,998
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`l0
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`SUMMARY OF THE INVENTION
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`To attain the above-mentioned object, according to
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`one aspect of the present invention, there is provided a
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`semiconductor device comprising a semiconductor sub-
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`strate; a metal wiring layer formed on the semiconduc-
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`tor substrate; a first insulation layer formed on the metal
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`wiring layer, the first insulation layer being formed by a
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`tensile stress insulation layer having a contracting char-
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`acteristic relative to the substrate; and a second insula-
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`tion layer formed on the first insulation layer, the sec-
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`ond insulation layer being formed by a compressive
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`stress insulation layer having an expanding characteris-
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`tic relative to the substrate.
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`Also, according to another aspect of the present in-
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`vention, there is provided a semiconductor device com-
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`prising a semiconductor substrate; a plurality of metal
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`wiring layers formed on the semiconductor substrate,
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`the plurality of metal wiring layers comprising one or
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`more lower side metal wiring layers having a small
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`wiring width and one or more upper side metal wiring
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`layers having a large wiring width; one or more first
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`insulation layers formed on the respective lower side
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`metal wiring layers , each of the first insulation layers
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`being formed by a tensile stress insulation layer having
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`a contracting characteristic relative to the substrate;
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`and one or more second insulation layers formed on the
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`respective upper side metal wiring layers, each of the
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`second insulation layers being formed by a compressive
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`stress insulation layer having an expanding characteris-
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`tic relative to the substrate.
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`In addition, according to the present invention, there
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`are provided methods for manufacturing the above-
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`mentioned semiconductor devices.
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`As above-mentioned,
`the tensile stress insulation
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`layer has a contracting characteristic relative to the
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`40
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`SAMSUNG ET AL. EXHIBIT 1050
`Page 8 of 12
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`3
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`In this connection, U.S. Pat. No. 4,446,194 discloses a
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`method of forming a dielectric layer having a compres-
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`sive stress (corresponding to compressive stress insula-
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`tion layer) on the metal layer and forming a dielectric
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`layer substantially free of compressive stress (corre-
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`sponding to the tensile stress insulation layer) on the
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`compressive stress insulation layer, to prevent a forma-
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`tion of voids in the metal layers.
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`But, as shown in the experimental data described in
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`detail below, a semiconductor device according to the
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`present invention (i.e., a semiconductor device compris-
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`ing a tensile stress insulation layer formed on the metal
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`layer and a compressive stress insulation layer formed
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`on the tensile stress insulation layer) effectively pre-
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`vents both a disconnection of the metal layers due to
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`stress migration and a generation of cracks in the insula-
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`tion layers, compared with the device disclosed in the
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`above U.S.P. Namely, according to present invention,
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`the above-mentioned particular advantages can be ob-
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`tained, which cannot be expected from the above
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`U.S.P.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a drawing explaining a characteristic of the
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`tensile stress insulation layer;
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`FIG. 2 is a drawing explaining a characteristic of the
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`compressive stress insulation layer;
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`FIG. 3 is a drawing showing the tensile stress insula-
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`tion layer formed on the metal wiring layer as a first
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`insulation layer;
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`FIG. 4 is a drawing showing the compressive stress
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`insulation layer fonned on the first insulation layer as
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`the second insulation layer;
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`FIGS. 5(a) to 5(e) are drawings showing a process for
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`manufacturing a semiconductor device according to a
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`first embodiment of the present invention;
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`FIG. 6 is a diagram showing how the value of the
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`stress generated in the insulation layer produced by the
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`plasma CVD is changed in accordance with the change
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`40
`of discharge frequency used in the plasma CVD system;
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`FIGS. 7(a) to 7(a") are drawings showing a process
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`for manufacturing semiconductor devices according to
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`second and third embodiments of the present invention;
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`FIGS. 8(a) to 801’) are drawings showing a process
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`for manufacturing a semiconductor device according to
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`a fourth embodiment of the present invention;
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`FIG. 9 is a diagram showing experimental data re-
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`garding the generation of stress migration in various
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`cases; and
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`FIG. 10 is a diagram showing experimental data re-
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`garding the generation of cracks in the insulation layers
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`in various cases.
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`DESCRIPTION OF THE PREFERRED
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`EMBODIMENTS
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`FIGS. 5(a) to 5(e) show a process for manufacturing
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`a semiconductor device according to a first embodi-
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`ment of the present invention. First, as shown in FIG;
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`5(a), a first metal wiring layer (e.g., aluminum wiring
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`layer) 31 is formed on a semiconductor substrate 1 (e.g.,
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`a silicon substrate) via a silicon insulation film 2 (e.g., a
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`silicon dioxide (SiO2) film). Next, as shown in FIG.
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`5(b), a tensile stress insulation layer 411 is formed as a
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`first insulation layer on the first metal wiring layer 31.
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`The tensile stress insulation layer 411 functions to com-
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`press the metal wiring layer 31, due to the contracting
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`characteristic thereof relative to the substrate, and thus
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`prevents stress migration which will cause a disconnec-
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`50
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`35
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`60
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`4
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`tion of the metal wiring layer 31. Then, as shown in
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`FIG. 5(c), a compressive stress insulation layer 412 is
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`formed as a second insulation layer on the tensile stress
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`insulation layer 411. In this connection, the compressive
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`stress insulation layer 412 expands together with the
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`metal wiring layer 31 when the metal wiring layer is
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`heated by a current flowing therethrough, due to the
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`expanding characteristic thereof relative to the sub-
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`strate, and thus stress applied by the metal wiring layer
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`to the insulation layer at that time is reduced, and as a
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`result, a generation of ‘cracks in the insulation layer is
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`"prevented.
`In this connection, the tensile stress insulation layer
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`411 can be formed by thermal chemical vapor deposi-
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`tion (thermal CVD) or plasma assisted chemical vapor
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`deposition (plasma CVD). When the thermal CVD
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`method is used, the insulation material such as phosphor
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`silicated glass (PSG) or silicon dioxide (SiOz) is depos-
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`ited on the metal wiring layer under the condition of a
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`reduced atmospheric pressure or standard atmospheric
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`pressure, and a processing temperature range higher
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`than 200° C., preferably from 300' C. to 450° C. When
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`the plasma CVD method is used, the insulation material
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`(the reaction gas) such as the above PSG, SiO2, SiON,
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`Si3N4 or BPSG (boron—phospho_r silicated glass), is de-
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`posited on the metal wiring layer by supplying a high
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`frequency power having the discharge frequency range
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`higher than 2 megahertz (e.g., 13.56 megahertz) be-
`tween flat electrodes arranged, for example, in parallel,
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`one of which electrodes is connected to the substrate,
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`under the processing temperature range of from 200' C.
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`to 450° C.
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`The plasma CVD method is used for forming the
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`compressive stress insulation layer 412, and the insula-
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`tion material (the reaction gas) such as the above PSG,
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`SiO2, SiON, Si3N4, or BPSG is deposited on the first
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`insulation layer by supplying a high frequency power
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`having a discharge frequency range lower than 2 mega-
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`hertz (e.g., 200 kilohertz) between the above electrodes,
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`under a processing temperature range of from 200' C. to
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`450“ C.
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`Note, the above plasma CVD is of a type other than
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`a plasma CVD wherein the plasma is produced by elec-
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`tron cyclotron resonance (ECR plasma CVD) as de-
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`scribed below.
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`FIG. 6 is a diagram showing how the value of the
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`stress generated in the insulation layer produced by the
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`plasma CVD is changed in accordance with a change in
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`the discharge frequency of the high frequency power
`supplied from a high frequency generator connected
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`between the above electrodes used in the plasma CVD
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`system. In FIG. 6, the abscissa corresponds to the dis-
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`charge frequency, and the ordinate corresponds to the
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`value of the stress (using 10" dyne/cm2, where n=8 for
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`PSG, and n=9 -for Si3N4, as a unit) generated in the
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`insulation layer produced by the plasma CVD. This
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`plasma CVD was performed by using the insulation
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`material (reaction gas) of the above PSG and Si3N4.
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`The value of the tensile stress generated in the insula-
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`tion layer is represented as ii positive value, and the
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`value of the compressive stress generated in the insula-
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`tion layer is represented as a negative value.
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`The value of the stress becomes zero at the point
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`where the discharge frequency is 2 megahertz, and the
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`value of above tensile stress increases in accordance
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`with the increase of the discharge frequency in the
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`frequency range higher than 2 megahertz. On the other
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`hand, the value of the above compressive stress in-
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`SAMSUNG ET AL. EXHIBIT 1050
`Page 9 of 12
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`5,160,998
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`15
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`5
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`creases in accordance with a decrease of the discharge
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`frequency in the frequency range lower than 2 mega-
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`hertz. Namely,
`the tensile stress insulation layer is
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`formed when the plasma CVD is performed at the dis-
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`charge frequency range higher than 2 megahertz, and
`the compressive stress insulation layer is formed at the
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`discharge frequency range lower than 2 megahertz.
`These conditions remain unchanged even when the
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`above ECR plasma CVD is adopted, instead of another
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`io
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`type of plasma CVD, for forming the insulation layer.
`Then, as shown in FIG. 5(d), a second metal wiring
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`layer 32 is formed on the second insulation layer 412.
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`When the above-mentioned steps are repeated, a tensile
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`stress insulation layer 421 and a compressive stress insu-
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`lation layer 422 are successively formed on the second
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`metal wiring layer 32, and a third metal wiring layer 33
`is formed on the above insulation layer 422 correspond-
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`ing to the second insulation layer.
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`the compressive
`Then,
`in the above embodiment,
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`20
`stress insulation layer 432 is formed as a cover on the
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`third metal wiring layer 33, as shown in FIG. 5(9), and
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`subsequently, an anneal processing for the semiconduc-
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`tor device is carried out for about half an hour under a
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`temperature of, for example, 450° C.
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`25
`FIGS. 7(a) to 7(d’) show a process for manufacturing
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`semiconductor devices according to second and third
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`embodiments of the present invention; the step shown in
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`FIG. 7(a) corresponds to that of the above FIG. 5(a).
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`Next, in the second embodiment of the present inven-
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`tion, as shown in FIG. 7(b), a tensile stress insulation
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`layer 411‘ is formed on the first metal layer 31 as the first
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`insulation layer. This insulation layer 411' may be
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`formed by the same means as used to form the tensile
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`stress insulation layer 411 in the first embodiment.
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`Then, as shown in FIG. 7(c), a compressive stress insu-
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`lation layer 412’ is formed as the second insulation layer
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`on the first insulation layer 411’. The insulation layer
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`412' is formed so that the surface thereof is made flat.
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`In this connection, the insulation layer 412’ having
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`40
`the flattened surface is formed by the above-mentioned
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`ECR plasma CVD method.
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`In this case, this ECR plasma CVD is carried out
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`under the condition that the microwave power for pro-
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`ducing the ECR Plasma is, for example, 800 watts, and
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`45
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`the discharge frequency and the output of the high
`frequency bias power applied between one electrode
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`connected to the substrate and the other electrode (e.g.,
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`the earth electrode) are, for example, 400 kilohertz and
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`50 to 100 watts, respectively. Namely, as shown in FIG.
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`50
`6, even when the above ECR plasma CVD is adopted,
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`the compressive stress insulation layer may be produced
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`in a discharge frequency range of the above bias power
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`which is lower than 2 megahertz. Under this condition,
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`the insulation layer 412' is produced by using an insula-
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`tion material such as Si02, PSG, SiON, Si3N4 or BPSG.
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`Accordingly, the surface of the insulation layer 412’
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`may be flattened, and then, as shown in FIG. 7(d), a
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`second metal wiring layer 32 formed on the flattened
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`surface of the insulation layer 412'. Further, the above
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`steps for forming the first and second insulation layers
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`and the metal wiring layer may be successively repeated
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`a predetermined number of times.
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`Also, in the third embodiment of the present inven-
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`tion, after the first step shown in FIG. 7(a), as shown in
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`FIG. 7(b’), a tensile stress insulation layer 411" is
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`formed as the first insulation layer on the first metal
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`wiring layer 31, in such a manner that the surface of the
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`insulation layer 411" is made flat.
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`6
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`As above-mentioned, the insulation layer 411" having
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`a flattened surface, is formed by the above ECR plasma
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`CVD method. In this case, this ECR plasma CVD is
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`carried out under the condition that the above micro-
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`wave power for producing the ECR plasma is, for ex-
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`ample, 8OO watts, and the discharge frequency and the
`output of a high frequency bias power applied between
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`the above electrodes, one of which electrodes is con-
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`nected to the substrate, are, for example, 13.56 mega-
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`hertz and 50 to 100 watts, respectively. Namely, as
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`shown in FIG. 6, even when the above ECR plasma
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`CVD is adopted, the tensile stress insulation layer may
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`be produced in the discharge frequency range of the
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`above bias power, which is higher than 2 megahertz.
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`Under this condition, the insulation layer 411" is pro-
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`duced by using the insulation material such as PSG,
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`SiO2, SiON, Si3N4 or BPSG.
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`Then, as shown in FIG. 7(c’), a compressive stress
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`insulation layer 412" is formed as the second insulation
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`layer on the flattened surface of the insulation layer
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`411". The insulation layer 412" may be formed by the
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`same means used to form the compressive stress insula-
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`tion layer 412 in the first embodiment. The surface of
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`the insulation layer 412”, which is formed on the flat-
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`tened surface of the insulation layer 411" also may be
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`flattened. Then, as shown in FIG. 7(d’), a second metal
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`wiring layer 32 is formed on the flattened surface of the
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`insulation layer 412". Further, the above steps for form-
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`ing the first and second insulation layers and the metal
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`wiring layer can be successively repeated a predeter-
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`mined number of times.
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`Thus, according to the second and third embodi-
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`ments of the present invention, since each of the metal
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`wiring layers is formed on the flattened surface of the
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`corresponding insulation layer, a high reliability of the
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`metal wiring layers is ensured.
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`FIGS. _8(t1) to 801’) show a process for manufacturing
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`a semiconductor device according to a fourth embodi-
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`ment of the present invention. In this embodiment, a
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`plurality of metal wiring layers are provided, the tensile
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`stress insulation layer is formed on each of lower side
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`metal wiring layers having a small wiring width, and
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`the compressive stress insulation layer is formed on
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`each of upper side metal wiring layers having a large
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`wiring width.
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`Namely, in this embodiment, the tensile stress insula-
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`tion interlayers 41 and 42 are formed on the first and
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`second metal wiring layers 31 and 32 having small wir-
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`ing widths hand 12, respectively, to prevent disconnec-
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`tion of the metal wiring layers having the small wiring
`widths due to stress migration. In this connection, the
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`tensile stress insulation layers may be formed by the
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`same means used to form the tensile stress insulation
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`layers in the above first embodiment.
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`Also, the compressive stress insulation