SEP-11-98 FRI 10133 All
`
`
`BUWS DOANE SHECKER
`
`
`
`
`
`
`FAX NO. 8‘3“°.338934
`
`
`
`CERTIFICATE OF FACSIMILE TRANSMISSION
`
`
`
`
`I‘HEREBY CERTIFY THAT THIS CORRESPONDENCE IS BEING FACSIMILE TRANSMITTED TO THE
`
`
`
`
`
`
`
`
`
`
`
`PATENT AND TRADEMARK OFFICE ON THE DATE SHOWN BELOW.
`
`
`
`
`
`
`
`
`
`
`
`
`Name of person signing certification:
`
`
`
`
`
`
`
`Sharon E. Ryan
`
`
`
`
`Date:
`
`(‘Z Or’
`
`Signature:
`
`"£4-«‘—v-a-—-I <2».
`
`
`
`
`Attorney‘s Docket No. _Q0_Bfifi2,;Q5_‘l
`
`
`
`
`
`
`
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`ff Z L
`
`
`
`
`
`
`
`
`In re Patent Application of
`
`
`
`Glenn 1. Leedy
`
`
`
`
`
`
`Application No.: 08/835,190
`
`
`
`
`Filed: Apl.'il4, 1997
`
`
`
`
`
`
`For: THREE DIMENSIONAL
`
`STRUCTURE MEMORY
`
`
`
`
`
`
`
`
`
`\-/\-/%/‘-—I€‘u/\-/\-v'\-/\-/
`
`
`
`
`Group An Unit: 2822
`
`
`
`
`
`Examiner: Collins, D.
`
`
`
`
`
`flSfl2
`
`
`
`
`Assistant Commissioner for Patents
`
`
`
`Washington, D.C. 20231
`
`
`
`Sir:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The following remarks are responsive to the Office Action of August 21, 1998.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The Officc Action of August 21, 1998 has been carefully considered. Reconsideration
`
`REMARKS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and allowance of the application in View of the following Remarks is respectfully requested.
`
`
`
`
`
`
`
`
`
`
`
`The Office Action states in Paragraph 5 thereof, "Applicant's arguments with respect to
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`claims 1, 3-23, 25-30, and 62-107 have been considered but are moot in view of the new
`
`
`
`
`
`
`
`
`
`ground(s) of rejection. New references disclosing multilayer interconnection systems have
`
`been added."
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In other respects the Office Action would appear to be substantially the same as the
`
`
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 1 of 9
`
`

`
`
`
`
`SEP~11*9B FRI 10133 Flil
`
`
`
`BUPNS DUANE SHECKER
`
`
`
`
`
`FAX N0. 8919338934
`
`
`
`
`
`
`
`Application Serial No. 08/835 , 190
`
`
`
`
`Attorney’s Docket No. 008442-057
`
`Page 2
`
`
`
`
`
`
`
`
`
`
`
`
`
`previous Dffice Action of Ianuary 28. 1998. Applicant submits that the newly-cited references
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of Miller and Bureau (cited by Applicant in the Disclosure Statement of September 19, 1997)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`are not especially germane to the claimed invention, nor is Finnila, cited by Applicant in a
`
`
`
`
`
`
`
`
`
`
`
`
`subsequent disclosure statement of July 23, 1998. Applicant further maintains that the claimed
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`invention is not taught or suggested by Yasumoto, for reasons set forth hereafter.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`First in regard to Miller, Miller does not relate to the stacking of integrated circuit
`
`
`
`
`
`
`
`
`
`
`
`
`
`wafers but rather relates to stacking of printed circuit board modules. Note, for example, col.
`
`
`
`
`
`
`
`3, lines 47-54:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig. 5 is a perspective view of a stack comprising identical modules 10-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1, 10-2 and 10-3 mounted on mother board 20, with connectors 50 serving both
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`as spacers and as means for interconnecting opposing connecting areas on the
`
`
`
`
`
`
`
`
`
`
`
`modules and mother board. Such connectors can be the stacking connectors or
`
`
`
`
`
`
`
`elastomeric connectors described above, or other suitable connectors.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Belting together printed circuit boards as in Miller is far afield from the claimed
`
`
`
`invention.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In regard to Bureau. Bureau discloses depositing a layer of poiyirnidc onto a substrate
`
`
`
`
`
`
`
`
`
`
`
`(column 4, last sentence). A multi—layer metal/polymer electrical interconnection system is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`then built up layer by layer. Chips are then installed to form a 2-D circuit structure. Multiple
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`2—D structures may be joined to form a 3~D circuit structure using an intervening "stencil" or
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`frame. As illustrated in the figures of Bureau, the stencil surrounds each individual chip.
`
`
`
`
`
`
`
`
`
`
`
`Although not mentioned in Bureau, typically with such a structure an underfilling technique
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`would be used in which a resin is injected so as to fill the remaining spaces between the chips
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and stencil and the polymeric substrate. Such underfilling is typically required to overcome
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the effects of CTE (coefficient of thermal expansion) mismatch. Bureau fails to teach or
`
`
`
`
`suggest the claimed invention.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Furthermore, Finnila, cited by Applicant fails to teach or suggest the claimed invention.
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 2 of 9
`
`

`
`
`
`
`SEP-11-98 FRI 10:34 F-ill
`
`
`
`BURNS DOHNE SWECKER
`
`
`
`
`
`FAX N0. 6502338934
`
`
`
`
`
`
`Application Serial No. 08/835,190
`
`
`
`Attorney’s Docket No. 008442-057
`
`Page 3
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Finnila teaches forming a silicon device layer on top of an insulating layer (so-called
`
`
`
`
`
`
`
`
`
`
`
`Si1icon—0n—Insulator, or SOI); i.e. , Finnila uses SOI substrate processing techniques to achieve
`
`
`
`
`
`
`
`
`
`
`an isolated semiconductor layer on a rigid, standard—thickncss substrate. He subsequently thins
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the substrate, but always keeps the thinned substrate bonded to a rigid substrate, such as the
`
`
`
`
`
`
`
`
`
`
`temporary substrate (26) or the permanent substrate (structure 1 or 42).
`
`
`
`
`
`processing.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In Finnila, all device processing (thermal oxide formation, doping, armealing, contact
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`drive-in, etc.) is performed before the SOI substrate is thinned. The only steps that Finnila
`
`
`
`
`
`
`
`
`
`
`
`
`performs after the S01 substrate is thinned are metallization and dielectric deposition
`
`
`
`
`
`
`
`
`
`
`
`
`It should be made clear that although he says that "conventional processing steps"
`
`
`
`
`
`
`
`
`
`
`
`
`
`(5551-36) are used, these steps are highly restricted due to the requirement that processing
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`temperatures be limited to less than 132°C, which is the melting point of Indium. Furthermore,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`based on typical characteristic of available waxes, the "wax" or bonding layer (24, 5:4-5) used
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to temporarily hold the SOI wafer for Ihinning and backside processing has a maximum
`
`temperature of 200°C. Applicant knows of no waxes that would be compatible with yacuum
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`processing of dielectric deposition or vacuum dry etching (called RIE) due to outgassing
`
`
`
`
`
`
`
`
`
`
`
`(which would cause the temporarily restrained substrate to delaminate from the holding
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`substrate 26) or temperature (typically in excess of 350°C for oxide and nitrides). Presumably,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Finnila is using spin-on glass dielectric with very low curing temperatures and wet etch
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`processing. The aluminum film of the aluminum I/O bond pads applied to the last circuit layer
`
`
`
`
`
`
`
`
`
`
`
`necessary for wiring bonding (5:34—35). however. can only be deposited through a sputtering
`
`
`
`
`
`
`
`
`
`
`
`
`
`process step which is a vacuum process step; Applicant knows of no "wax" which can
`
`
`
`
`
`
`
`
`
`withstand vacuum processing without outgassing which would dclaminate the thinned
`
`
`
`
`
`
`
`
`
`
`
`substrate.
`
`
`
`
`
`
`
`
`
`
`
`Finnila does not indicate a need to use low-stress dielectrics. Furthermore, the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`dielectrics he is using (therrnal oxide or spin-on glass) are known to have very high
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`compressive stresses in excess of 1 x 10“ dynes cm’, which would be sufficient to cause the
`
`
`
`
`
`
`
`
`
`
`
`
`
`scmiconductor layer to delaminate from the “wax" or the Indium bump with epoxy undcrfill.
`
`
`
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 3 of 9
`
`

`
`
`
`
`SE_P-l1-98 FRI 10:34 All
`
`
`
`BURMC: DOANE S1-JECKER
`
`
`
`
`
`FAX N0. 8509338934
`
`
`
`
`
`
`
`Application Serial No. 08/335,190
`
`
`
`
`Attorney's Docket No. 008442-057
`
`
`Page 4
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Serious doubt is therefore cast on the workability of Finnila.
`
`
`
`
`
`
`
`
`
`
`
`Unlike Miller and Bureau, Finnila docs teach fonning an interconnect that passes
`
`
`
`
`
`
`
`
`
`
`
`In other respects, however, the method of Finnila is far
`through a semiconductor substrate.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`different from that of the present invention. Finnila does not teach or suggest the claimed
`
`
`
`
`
`
`
`
`
`
`
`
`
`sequence of bonding two substrates by thermal diffusion bonding, thinning one of the bonded
`
`
`
`
`
`
`
`
`
`
`
`substrates. and performing backside processing of the thinned substrate to form pass—throughs
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and contacts. Moreover, Finnila contains no suggestion of forming a semiconductor memory
`
`
`
`
`
`
`
`
`
`
`
`
`controller on one substrate and a semiconductor memory array on a separate substrate as
`
`
`
`recited in Claim 1.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Hence, none of the foregoing references lends substantial strength or support to the
`
`
`
`
`
`primary reference, Yasumoto.
`
`
`
`
`
`
`
`
`
`
`
`
`
`As explained in the previous response, the bonding and interconnect methods,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`especially, of the invention of Claim 1 are far different from those of the prior art. In
`
`
`
`
`
`
`
`
`
`
`
`
`accordance with the invention, bonding occurs by thermal diffusion bonding. As described in
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the specification, various metals commonly used in semiconductor processing are particularly
`
`
`
`
`
`
`
`
`
`
`amenable to thermal diffusion bonding in which complementary surfaces are bonded together
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`through the application of heat and pressure. A requirement for thermal diffusion bonding is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`that the complementary surfaces be highly planar. This degree of planarity is achieved using a
`
`
`
`
`
`
`
`
`
`
`
`semiconductor processing technique of only recent origin known as Chemical Mechanical
`
`
`
`
`
`
`
`
`
`
`
`
`
`Polishing, or CMP. The materials and methods used to perform thermal diffusion bonding as
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`described and claimed are fully compatible with existing semiconductor processing techniques.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Hence, a bonding step may be followed by further semiconductor processing, which may in
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`turned be followed by a further bonding step, etc- A t.hree~dimcl1sional device stack having a
`
`
`
`
`
`
`
`
`
`
`
`large number of device layers may thereby be produced. Furthermore, threcndimensional
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`processing is performed at the wafer Ievel as opposed to at the chip level. The number of work
`
`
`
`
`
`
`
`
`
`
`
`
`
`pieces to be handled is therefore greatly reduced, typically several hundred-fold, as compared
`
`
`
`
`
`
`
`
`to thrcc—dimensional processing techniques performed at the chip level.
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 4 of 9
`
`

`
`
`
`
`
`SF‘P-11-98 FRI 10:35 All
`
`
`
`
`
`BURW DOHNE SHECKER
`
`
`
`
`
`FAX N0. 6509338934
`
`
`
`
`
`
`
`Application Serial No. 08/835,190
`
`
`
`
`Attorncy’s Docket No. 008442-057
`
`
`Page 5
`
`
`
`
`
`
`
`
`
`Yasumoto performs bonding together offinished chips to form three-dimensional
`
`
`
`
`
`
`
`
`
`
`
`structures. (Yasumoto, cal. 10,, lines 6-17; col. 13, lines 38-40.) Further conventional
`
`
`
`
`
`
`
`
`
`
`
`
`semiconductor processing steps (which are invariably performed in wafer form) are not
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`contemplated, but rather are precluded. In Yasumoto, bonding depends upon an adhesive resin
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`layer. This layer is intended to address the planarity problem, which could not have been
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`addressed by CMP, since the reference predates by nearly a decade the advent of CMP. (The
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`use of such adhesive resin layers would, by itself, be likely to preclude further conventional
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`semiconductor processing of a three—dirnensional structure in that such layers cannot. in
`
`
`
`
`
`
`
`
`
`
`
`general, tolerate the high levels of heat associated with typical semiconductor processes.)
`
`
`
`
`
`
`
`
`
`
`
`Also in accordance with the invention, interconnects are formed that pass entirely
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Specification, page 15. step
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`through whole substrates. This interconnect structure is referred to in the specification as fine-
`
`
`
`
`
`
`
`
`
`
`
`
`grain vertical interconnect. As further described in the specification. such fine grain vertical
`
`
`
`
`
`
`
`
`
`
`
`interconnects are formed by thinning and backside processing of a preceding substrate and
`
`
`
`
`
`
`
`complementary franrside processing of a succeeding substrate.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`3). followed by bonding of the backside and complementary frontside. This sequence may be
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`repeated an arbitrary number of times to produce a stacked IC of 10 layers, 20 layers or more.
`
`
`
`
`
`
`
`
`
`
`
`
`
`With the exception of Finnila, none of the references teach or suggests an interconnect
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`that passes through a substrate. Accordingly, all of the references are limited to two circuit
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`layers where those circuit layers are formed within a substrate. Yasumoto (col. 12. lines 60-64)
`
`
`
`
`
`
`
`
`
`
`
`
`alludes to the possibility of a three-dimensional semiconductor structure having four or more
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`multilayer structure portions obtained when two or more of the multilayer structural portions
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`118 are provided between two outer multilayer structural portions 24 and 24'- The
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`intermediate circuit layers of such a structure. however, are not formed within a substrate but
`
`
`
`
`
`
`
`
`
`
`
`
`
`rather are thin-fllm transistor layers formed or: a substrate with the substrate being
`
`
`
`
`
`
`
`
`
`
`
`
`subsequently removed. (Yasurnoto, Figure '7 and 8. Interconnects 112 and 134 pass through a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`TFT device layer but do not pass through a substrate, the substrate having been removed.)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Only in the case of the two outer multilayer structural portions 24 and 24' is the circuit layer
`
`
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 5 of 9
`
`

`
`
`SEP-11-B8 FRI
`
`
`
`
`lD:3B All
`
`
`
`BURN‘? DOHNE SHECKER
`
`
`
`
`
`FAX N0. 6502338934
`
`
`
`
`
`
`formed within the substrate.
`
`
`
`
`
`
`
`Application Serial No. 08/835,190
`
`
`
`
`Attorney's Docket No. 008442-057
`
`Page 6
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The following table identifies for each figure in Yasurnoto the substrates shown in that
`
`
`
`
`
`
`
`
`
`In no instance does an interconnect pass through the substrate.
`
`
`
`
`
`figure.
`
`
`TABLE I
`
`
`YASUMTO FIGURE
`
`
`
`M
`
`
`
`Fi re 1 f)
`
`Fiure 2
`
`Fi re 3
`
`Figure 6(g)
`
`Fi re?
`
`_ Fi res
`
`_
`
`12. 12'
`
`26, 26'
`
`84 (multilayer structure not shown:
`col. 11, lines 6-7)
`
`12 12’
`
`26,
`
`
`
`
`
`
`
`
`
`
`
`
`
`The same analysis applies equally to each of the secondary references-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`A fine—grain interconnect structure passing through a substrate can only be formed if
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the substrate is very thin. A small hole (less then 1 um) might be formed in a conventional
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`thick substrate, but the aspect ratio of the hole would be so large (e.g.. 75:1 to 350:1) as to
`
`
`
`
`
`
`
`
`
`
`
`
`
`make filling the hole with metal impossible using known techniques. Of the cited references,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Sanders was cited as disclosing a multiple chip package with thinned semiconductor chips
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`using a grinding disk to remove material. Sanders, however, teaches backside circuit thinning
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(in die form, not wafer form) for the purpose of cooling. None of the references teaches or
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`suggests the formation of a fine—gtain vertical interconnect through a substrate in the manner of
`
`
`
`
`
`
`claim 1.
`
`
`
`
`
`
`
`
`
`
`
`
`The technique of Yasumoto, besides being limited to only two device-hearing
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 6 of 9
`
`

`
`
`
`
`SEP-1l~BB FRI 10138 All
`
`
`
`BURN? DOQNE SHECKER
`
`
`
`
`
`FBX NO. 8502338934
`
`
`
`
`
`
`
`Application Serial No. 08/835,190
`
`
`
`
`Attorney’s Docket No. 0084427057
`
`Page 7
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`substrates. is limited in various other important respects. Referring to Figure 4 and 5 of
`
`
`
`
`
`
`
`
`
`
`
`
`
`Yasumoto, for example. the only way to provide for connection to a three—dimensional
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`structure of the type disclosed in Yasumoto is for one layer to have a larger extent than another
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`layer. A portion of the surface of the larger layer therefore remains exposed, allowing bond
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`pads to be formed thereon. The bond pads may be wire bonded to leads of an MCM (multi-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In the case of the present invention, as recited in claim
`chip module) package, for example.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`96, bond pads are formed on the backside of a final thinned substrate. The resulting multilayer
`
`
`
`
`
`
`
`
`
`
`
`
`structure is therefore comparable. in size and bond pad layout. to a single conventional
`
`
`
`
`
`
`
`integrated circuit, compatible with existing single-chip packages.
`
`
`
`
`
`
`
`
`
`
`
`
`Another problem not discussed in Yasumolo is that of film stress. Semiconductor films
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`are not stress-free but exhibit certain stress levels depending on many factors including
`
`
`
`
`
`
`
`
`
`
`
`
`material, deposition technique, etc. A thick film exhibits proportionally greater stress than a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`thin film. Stress is relieved either by bending or cracking -- i.e., either the substrate gives or
`
`
`
`
`
`
`
`
`
`
`
`
`the film gives. Using conventional higher-stress dielectric films of silicon dioxide and silicon
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`nitride (commonly used in conventional memory circuit fabrication), the technique of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Yasumoto would likely be limited to no more than three layers as shown in Figure 8.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Additional layers would be likely to cause peeling apart of the layers at the adhesive interface.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In the case of the present invention, on the other hand. low—sttcss dielectrics (less than
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5 x 10“ dynes (crni) are used as described on page 14 of the present specification and further
`
`
`
`
`
`
`
`
`
`
`
`
`described in U.S. Patent 5,354,695 of the present inventor. Stress buildup and consequent
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`bending or cracking is therefore avoided. The number of layers is not stress-limited.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`A summary of some of the most salient differences between Yasurnoto and the present
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`invention, together with an indication of where that difference is reflected in the claims. is
`
`
`
`
`
`
`
`
`
`presented in the following table:
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 7 of 9
`
`

`
`
`
`
`SEP-11-QB FRI 10:37 PM
`
`
`
`
`
`BUR"? DOANE SHECKER
`
`
`
`
`
`FAX N0. 8509338934
`
`
`
`
`
`
`
`Application Serial No. 08/335,190
`
`
`
`
`Attorney's Docket No. ODS442~OS7
`
`
`Page 8
`
`TABLE II
`
`
`PRESENT INVENTION
`
`
`
`
`RELEVANT CLAIM
`
`LANGUAGE
`
`
`
`
`YASUMOTO
`
`
`
`
`
`
`
`
`
`
`
`
`Begin with chip (die) having
`
`
`
`
`topmost adhesive layer. with
`
`
`
`contacts through adhesive
`
`layer.
`
`
`
`
`Begin with wafer fabricated
`
`
`
`using Iow—stress dielectrics
`
`
`
`
`
`
`Bond additional wafer
`
`
`
`(fabricated using low-stress
`
`
`
`
`dielectrics) to previous wafer
`
`
`
`
`by thermal diffusion bonding,
`
`
`
`
`e.g., metal thermal diffusion
`
`bonding.
`
`Thin backside of additional
`
`
`
`
`
`
`
`wafer, process backside to
`
`
`form contacts
`
`
`
`
`
`
`Repeat bonding and thinning
`
`
`
`
`
`
`steps for as many wafers as
`
`desired.
`
`
`
`
`
`
`
`
`
`Form bond pads on backside of
`
`
`final wafer.
`
`
`
`
`
`
`Dice wafer stack into 3D chips.
`
`
`
`
`
`
`...whereln said substrates are
`
`
`semiconductor wafers...
`
`
`
`
`
`(claims 95, 102); ...formed
`
`
`
`using low—stress dielectric...
`
`(claims 97. 104)
`
`
`
`
`
`
`
`...saicl bonding is thermal
`
`
`
`
`diffusion bonding of the first
`
`
`
`
`substrate to the second
`
`
`
`substrate... (claims 1, 62)
`
`
`
`
`
`
`.. .the backside of one of said
`
`
`
`
`
`
`
`
`
`
`
`substrates is thinned and then
`
`
`
`processed to f0rl'l‘l
`
`
`
`interconnections that pass
`
`
`
`
`
`through said substrate and to
`form contacts on the backside
`
`
`
`
`
`
`
`
`
`of said substrate... (claims 1.
`
`62)
`3
`
`
`
`
`
`
`
`
`
`.. Jnonding at least one
`
`
`
`
`additional substrate to the
`
`
`
`stacked IC substrate. .. (claims
`
`
`
`14 and 65)
`
`
`
`
`
`
`
`
`...forming bond pads on the
`
`
`
`
`backside of the final
`
`
`
`substrate... (claims 98, 105)
`
`
`
`
`
`
`
`
`
`
`...dicing a resulting stacked
`wafer into individual stacked
`
`
`
`
`
`ICs... (claims 96, 103)
`
`
`
`
`
`
`
`
`
`
`
`Prepare additional chip (die)
`
`
`
`having adhesive layer, device
`
`
`
`
`layer. then substrate, with
`
`
`
`
`contacts through adhesive layer
`
`
`
`
`
`and device layer; band together
`
`
`
`
`with previous chip, adhesive
`
`
`layer first.
`
`Remove substrate
`
`
`
`
`
`
`
`Repeat preparing. bonding and
`
`
`
`
`
`removing steps for as many
`
`
`
`chips as technology constraints
`
`
`
`(stress, adhesive degradation
`
`
`
`from heat) allow.
`
`
`
`
`
`
`
`
`
`
`
`Bond additional chip (die).
`
`
`
`
`leave substrate; either first chip
`
`
`
`
`
`
`or last chip must have larger
`
`
`
`
`
`
`area to allow for bond pads.
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 8 of 9
`
`

`
`
`
`SEP-11~98 FRI 10:37 fill
`
`
`
`BURNS DUANE SNECKER
`
`
`
`
`
`FHX N0. 8502338834
`
`
`
`
`
`
`Application Serial No. 08/835,190
`
`
`
`Attorney’s Docket No. 008442-057
`
`Page 9
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Claim 62 has previously been amended to recite thinning substrates on which integrated
`
`
`
`
`
`
`
`
`
`
`
`circuits are formed to form thinned substrates, facilitating formation of interconnects. and
`
`
`
`
`
`
`
`
`
`
`
`
`performing backside processing of the substrates. Thinning of a substrate is technically very
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`different from removing a substrate. As recited in claim 75. in the preferred embodiment of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`present invention, a substrate is thinned such that a thin device layer remains. Devices within
`
`
`
`
`
`
`
`
`
`
`
`
`
`this device layer are formed within a portion of the substrate, which may be monocrystalline
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`silicon, for example. High—quality transistors result. Where devices are formed on (not within)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a substrate which is later removed, as in Yasumoto, the device layer, because it is not part of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the substrate, remains when the substrate is removed. However, the quality of the transistors
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`that may be formed in such a layer suffers. While the quality of such transistors may suffice
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`for purposes of an LCD display, for example, the quality does not generally suffice for
`
`
`
`
`
`
`
`
`
`realizing a memory or memory controller.
`
`
`
`
`
`
`
`
`
`
`
`
`
`Again, none of the prior art references teaches or suggests the combination of features
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of claim 62. New claims 92-106 have been previously added, drawn to various other
`
`
`
`
`significant features of the invention.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Accordingly, Claims 1 and 62 are believed to patentably define over the cited
`
`
`
`
`
`
`
`
`
`
`
`
`references, as is newly—aclded independent claim 106. Claims 230 and 63-103 are also
`
`
`
`
`
`
`
`
`
`
`
`
`believed to add novel and patentable subject matter to their respective independent claims.
`
`
`
`
`
`
`
`
`
`
`
`Withdrawal of the rejection and allowance of Claims 1-30 and 62-106 is therefore respectfully
`
`
`
`
`
`
`
`M
`
`
`
`requested.
`
`
`
`
`Respectfully submitted,
`
`
`
`
`
`
`
`
`BURNS, DOANE. SWECKER 8: MATHIS, LLP
`
`
`
`Post Office Box 1404
`
`
`
`
`
`
`Alexandria, Virginia 22313-1404
`
`
`(650) 854-7400
`
`
`
`Date: September 8, 1998
`
`
`
`
`
`By;
`
`
`
`JL—1_._.
`
`Michael J.
`
`c
`
`
`
`Registration No. 33,089
`
`
`
`SAMSUNG ET AL. EXHIBIT 1025
`Page 9 of 9