United States Patent
`
`[19]
`
`USOO5354695A
`[11] Patent Number:
`
`5,354,695
`
` .
`
`Leedy
`
`[45] Date of Patent:
`
`Oct. 11, 1994
`
`[54] MEMBRANE DIELECIRIC ISOLATION IC
`FABRICATION
`Inventor: Glenn J. Leedy, 1061 E. Mountain
`Dr., Montecito, Calif. 93108
`
`[76]
`
`Assistant Examiner—-Trung Dang
`Attorney, Agent, or Fz'rm—Blakely, Sokoloff, Taylor &
`Zafma”
`[57]
`
`ABSTRACI‘
`
`General purpose methods for the fabrication of inte-
`grated circuits from flexible membranes formed of very
`thin low stress dielectric materials, such as silicon diox-
`ide or silicon nitride, and semiconductor layers. Semi-
`conductor devices are formed in a semiconductor layer
`of the membrane. The semiconductor membrane layer
`is initially formed from a substrate of standard thick-
`ness, and all but a thin surface layer of the substrate is
`then etched or polished away. In another version, the
`flexible membrane is used as support and electrical in-
`terconnect
`for conventional
`integrated circuit die
`bonded thereto, with the interconnect formed in multi-
`P13 layers in the membrane- M“1‘iP1e die Can be °°“'
`nected to one such membrane, which is then packaged
`as a multi-chip module. Other applications are based on
`(circuit) membrane processing for bipolar and MOS-
`FET transistor fabrication, low impedance conductor
`interconnecting fabrication, flat panel displays, maskless
`(dim W“‘*°> “‘h°g‘aPhY~ and 391“ ‘ab“°a“°"-
`16 Claims, 64 Drawing Sheets
`
`SAMSUNG ET AL. EXHIBIT 1006
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`PAGE 1 OF 89
`
`[21] Appl. No.: 865,412
`.
`_
`Apr’ 8’ 1992
`[22] Bled‘
`[5l]
`Int. Cl.5 ............................................. H01L 21/00
`[52] U.S. Cl. ...................................... .. 437/7; 437/974;
`437/62; 437/238; 437/241; 437/907; 148/DIG.
`135
`[58] Field of Search ................... 437/974, 7, 8, 62, 66,
`437/238, 241; 156/662; 148/DIG. 135
`
`References Cited
`U-S- PATENT DOCUMENTS
`4,070,230
`1/1978 Stein ...................................... 437/66
`4,131,985
`1/1979 Greenwood et al.
`__ 437/62
`437/3
`4,618,397 10/1986 Shimizu et al.
`4,702,936 10/1987 Maeda et al.
`437/241
`4,721,938
`1/1988 Stevenson ..
`156/662
`‘£952,445 3/1990 Lee et 31-
`--------
`437/974
`§:?ié:§%‘§ ‘£233: §};‘3;:i°.‘.f?:..::................:::: 133233
`Primary Examiner—Bria.n Heam
`
`
`
`[56]
`
`SAMSUNG ET AL. EXHIBIT 1006
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`U.S. Patent"
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`Oct. 11, 1994
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`Sheet 1 of 64
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`U.S. Patent
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`Oct. 11, 1994
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`U.S. Patent
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`Oct. 11, 1994
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`Oct. 11 1994
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`US. Patent
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`Oct. 11, 1994
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`1
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`5,354,695
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`MEMBRANE DIELECTRIC ISOLATION IC
`FABRICATION
`
`BACKGROUND OF THE INVENTION
`
`5
`
`1. Field of the Invention
`
`This invention relates to methods for fabricating inte-
`grated circuits on and in flexible membranes, and to
`structures fabricated using such methods.
`2. Description of Related Art
`Mechanically and thermally durable free standing
`dielectric and semiconductor membranes have been
`
`10
`
`15
`
`20
`
`disclosed with thicknesses of less than 2 pm. (See com-
`monly invented U.S. Pat. No. 4,924,589, and U.S. patent
`application Ser. No. 07/482,135, filed Feb. 16, 1990,
`now U.S. Pat. No. 5,103,557, both incorporated herein
`by reference). This disclosure combines the novel use of
`these technologies and other integrated circuit (IC)
`processing techniques to form ICs as membranes typi-
`cally less than 8 pm thick. This approach to IC fabrica-
`tion falls under the generic industry-established title
`known as Dielectric Isolation (DI), and is inclusive of
`subject areas such as Silicon-on-Insulator (S01) and
`Silicon-on-Sapphire (SOS). ICs formed from dielectric 25
`and semiconductor membranes can reduce significantly
`the number and complexity of processing steps pres-
`ently used to provide complete IC device isolation;
`dielectric isolation techniques that provide dielectric
`isolation on all surfaces of the individual circuit devices
`
`30
`
`comprising the complete IC are not as yet widely used
`in volume IC fabrication. Integrated Circuits are de-
`fined as commonly understood today when referring to
`SSI, MSI, LSI, VLSI, ULSI, etc. levels of circuit com-
`
`plexity.
`
`35
`
`SUMMARY OF THE INVENTION
`
`This invention is directed to a general method for the
`fabrication of integrated circuits and interconnect met-
`allization structures from membranes of dielectric and
`
`semiconductor materials. The fabrication technology in
`accordance with this invention is referred to herein as
`
`Membrane Dielectric Isolation (MDI), and the circuits
`made from it as circuit membranes. The novel use of
`materials and processing techniques provides for the 45
`fabrication of high temperature, mechanically durable,
`large area free standing membranes (greater than 1
`square cm in area) from low stress dielectric and/or
`semiconductor films. These membranes permit the ap-
`plication (continued use) of most of the established 50
`integrated processing methods for the fabrication of
`circuit devices and interconnect metallization.
`
`In accordance with the invention, an integrated cir-
`cuit is formed on a tensile low stress dielectric mem-
`
`55
`
`brane comprised of one layer or a partial layer of semi-
`conductor material in which are formed circuit devices
`and several layers of dielectric and interconnect metalli-
`zation. Also, a structure in accordance with the inven-
`tion is a tensile membrane of semiconductor material in
`which are formed circuit devices with multiple layers of 60
`tensile low stress dielectric and metallization intercon-
`nect on either side of the semiconductor membrane.
`The membrane structure is a processing or manufac-
`turing structure for enabling the manufacture of novel
`and more cost effective integrated circuits. This is in
`addition to an objective to manufacture an integrated
`circuit, or portion thereof, in a membrane or thin film
`form.
`’
`
`65
`
`2
`The general categories of circuit membranes that can
`be made by this invention are:
`1. Large scale dielectric isolated integrated circuits
`formed on or from semiconductor or non-semiconduc-
`tor substrates.
`interconnect metallization circuits
`2. Multi-layer
`formed on or from semiconductor or non-semiconduc-
`tor substrates.
`The primary objectives of the MDI fabrication tech-
`nology disclosed herein are the cost effective manufac-
`ture of high performance, high density integrated cir-
`cuits and integrated circuit interconnect with the elimi-
`nation or reduction of detrimental electrical effects on
`the operation of individual circuit devices (e.g. diodes,
`transistors, etc.) by completely isolating with a dielec-
`tric material each such circuit device from the common
`substrate upon which they are initially fabricated, and
`therefore, from each other, and to provide a more ver-
`satile and efficient physical form factor for the applica-
`tion of integrate circuits. Some of the benefits of the
`MDI IC fabrication process are the elimination or re-
`duction of substrate current leakage, capacitive cou-
`pling and parasitic transistor effects between adjoining
`circuit devices. The MDI IC fabrication process bene-
`fits extend to several other categories of IC fabrication
`such as lower IC processing costs due to fewer IC isola-
`tion processing steps, greater IC transistor densities
`through the capability to use established IC processing
`techniques to fabricate interconnect metallization on
`both sides of a MDI IC circuit membrane, and greater
`IC performance through novel transistor structures.
`The strength of the MDI processes is primarily
`drawn from two areas:
`
`(1) The ability to make a large area flexible thin film
`free standing dielectric membrane, typically framed or
`suspended or constrained at its edges by a substrate
`frame or ring, or bonded frame or ring. This membrane
`is able to withstand a wide range of IC processing tech-
`niques and processing temperatures (of at least 400° C.)
`without noticeable deficiency in performance. The
`present dielectric materials that meet these require-
`ments are silicon dioxide and silicon nitride films when
`
`prepared with specific low stress film deposition recipes
`for instance on equipment supplied by Novellus Sys-
`tems, Inc. Dielectric free standing films created by
`CVD process methods such as silicon carbide, boron
`nitride, boron carbon nitride aluminum oxide, alumi-
`num nitride, tantalum pentoxide, germanium nitride,
`calcium fluoride, and diamond have been produced, and
`can potentially be used as one of the dielectric materials
`in a MDI circuit membrane when deposited at an appro-
`priate level of surface stress. Advances in the technol-
`ogy for making low stress dielectric films will likely
`produce additional free standing films that can be used
`as described herein.
`
`(2) The ability to form a uniform thin film single
`crystal semiconductor substrate either as the primary
`substrate of semiconductor devices or as a carrier sub-
`strate upon which semiconductor devices could be
`grown epitaxially. Several methods toward this end are
`disclosed herein, and other techniques which are modi-
`fications thereof exist. Further, in certain applications
`polycrystalline semiconductor membranes
`such as
`polysilicon can be used in substitution for monocrystal-
`line material.
`It is the combination of the use of low stress free
`
`standing dielectric films with the appropriate process-
`ing qualities and membrane or thin film single crystal-
`
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`3
`line (monocrystalline), polycrystalline or amorphous
`semiconductor substrate formation that provides much
`of the advantage of the MDI IC fabrication process.
`The following methods are encompassed within the
`present disclosure:
`1. Methods for the fabrication of low stress free stand-
`
`ing (thin film) dielectric membranes that encapsulate
`each semiconductor device that comprises an IC.
`2. Methods for the formation of uniform thickness
`
`semiconductor membrane (thin film) substrates for use
`in combination with low stress dielectric materials.
`3. Methods for the fabrication of semiconductor de-
`vices within and on a dielectric membrane that com-
`
`4
`6. Application of interconnect metallization to both
`sides of the IC.
`
`7. Through-membrane (substrate) interconnect metalli-
`zation routing.
`8. Three dimensional IC structures through the bonding
`of circuit membrane IC layers.
`9. Efficient conductive or radiant cooling of IC compo-
`nents of circuit membrane.
`
`10
`
`10. Direct optical (laser) based communication between
`parallel positioned membrane ICs.
`11. Higher performance ICs.
`12. Vertical semiconductor device structure formation.
`13. Novel selective epitaxial device formation.
`
`prises a circuit membrane.
`4. Methods for the formation of interconnect metalli-
`
`15
`
`zation structures within and on a dielectric membrane
`that comprises a circuit membrane.
`The MDI circuit fabrication process in one embodi-
`ment starts with a semiconductor wafer substrate, and
`results in an IC in the form of a circuit membrane where
`
`20
`
`each transistor or semiconductor device (SD) in the IC
`has complete dielectric isolation from every other such
`semiconductor device in the IC. Only interconnect at
`the specific electrode contact sites of the semiconductor
`devices provides electrical continuity between the semi-
`conductor devices. The primary feature of the MDI
`process is complete electrical isolation of all semicon-
`ductor devices of an IC from all of the intervening
`semiconductor substrate on which or in which they
`were initially formed and to do so at lower cost and
`process complexity than existing bulk IC processing
`methods. Other features of the MDI process are vertical
`electrode contact (backside interconnect metallization),
`confined lateral selective epitaxial growth, non-sym-
`metric dopant profiles, and the use of a MDI circuit
`membrane to serve as a conformal or projection mask
`for lithography processing. Even if the initial substrate
`with which MDI processing begins with is the most
`commonly used semiconductor silicon, the resulting IC
`need not be composed of silicon-based devices, but
`could be of any semiconductor device material such as
`GaAs, InP, HgCdTe, InSb or a combination of technol-
`ogies such as silicon and GaAs grown on a silicon sub-
`strate through epitaxial means. Silicon is an inexpensive
`and well understood semiconductor substrate material
`
`with superior mechanical handling properties relative
`to most other presently established semiconductor ma-
`terials. The MDI process is not limited to starting with
`a silicon substrate and the process definition of MDI is
`not dependent on use of silicon; however, there are
`presently clear advantages to using silicon as a starting
`semiconductor substrate, and the chief embodiment
`disclosed herein of MDI uses a starting semiconductor
`substrate material of silicon.
`
`The benefits to fabricating an IC with the MDI pro-
`cess are significant over prior art methods, some of
`these benefits being:
`1. Complete electrical isolation of semiconductor de-
`vices.
`2. Vertical semiconductor device structures.
`
`3. Lower processing costs through lower processing
`complexity or
`fewer device isolation processing
`steps.
`4. Conformal mask lithography through the membrane
`substrate.
`
`5. Control of depth of focus during lithography expo-
`sure due to control of substrate thickness.
`
`In some semiconductor technologies it is not neces-
`sary to have complete isolation between each transistor
`or semiconductor device, such as certain applications
`using polycrystalline or amorphous TFTs (thin film
`transistors). This is not a limitation on the MDI process,
`because semiconductor device side wall isolation is an
`
`option in the MDI process. What is novel is that the
`MDI process provides general methods by which thin
`films or membranes of dielectric and semiconductor
`
`25
`
`materials can be formed into a free standing IC or cir-
`cuit membrane.
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`FIGS. 1a to lj show a dielectric and semiconductor
`membrane substrate in cross-section.
`FIG. 2 shows an etched silicon substrate membrane in
`cross-section.
`FIGS. 3a, 3b show dielectric membranes with semi-
`conductor devices.
`
`FIG. 4 shows an alignment mark of a circuit mem-
`brane in cross-section.
`FIG. 5 shows support structures for a membrane
`structure isolation structure.
`FIG. 6a to 61' show a circuit membrane Air Tunnel
`structure.
`
`FIG. 7 shows stacked circuit membranes with optical
`input/output.
`FIG. 8 shows a three dimensional circuit membrane.
`
`FIGS. 9a to 9j show fabrication of a MOSFET in a
`membrane.
`FIGS. 10a to 10d show fabrication of a transistor by
`lateral epitaxial growth on a membrane.
`FIGS. 11a to 11fshow vertical MOSFET and bipolar
`transistors formed on a membrane.
`FIG. 12a to 12g show transistor fabrication on a
`membrane using confined laterally doped epitaxy.
`FIGS. 12h to 12j show cross-sections of selective
`epitaxial growth on a membrane.
`FIGS. 13:: to 13:1 show cross-sections of multi-chip
`modules.
`FIG. 14 shows a cross-section of a membrane formed
`on a reusable substrate.
`FIG. 15 shows a cross-section of the membrane of
`
`FIG. 14 with a support frame attached.
`FIGS. 16a, 16b show multi-chip modules in packages.
`FIGS. 17a to 17¢ show soldering of bond pads of a
`circuit membrane to a die.
`
`FIG. 18 shows bond pads on a die.
`FIGS. 19a, 19b show bonding and de-bonding of a die
`to a circuit membrane.
`FIGS. 20, 21 show two sides of a circuit membrane.
`FIGS. 22a to 226 show formation of a metal trace in
`
`a circuit membrane by a lift-off process.
`
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`5
`FIGS. 23a, 23b show use of a buried etch stop layer
`to form a circuit membrane having a thinner inner por-
`tion.
`
`FIGS. 24, 25 show a source-integrated light valve for
`direct write lithography.
`FIGS. 26, 27 are cross-sections of X-ray sources for
`the device of FIGS. 24, 25.
`FIGS. 28a to 28b show a coil for the device of FIG.
`24.
`
`FIGS. 29a to 29k show portions of a source-external
`radiation valve for direct write lithography device.
`FIGS. 291 to 29p show use of fixed freestanding mem-
`brane lithography masks.
`.
`FIG. 30 shows a cross-section of a lithographic tool.
`FIGS. 31:: to 31c show cross-sections of a display
`formed on a membrane.
`FIGS. 32a, 32b show bonding of two circuit mem-
`branes.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The MDI process is the formation of an IC or inter-
`connect metallization circuit as a free standing dielec-
`tric and/or semiconductor circuit membrane. Each
`semiconductor device comprising an IC circuit mem-
`brane is a semiconductor device optionally isolated
`from adjoining semiconductor devices, and where each
`semiconductor device is formed on or in a membrane of
`
`5
`
`10
`
`15
`
`20
`
`25
`
`semiconductor material typically less than 8 pm in
`thickness. The overall thickness of a circuit membrane
`
`30
`
`is typically less than 50 pun and preferably less than 8
`pm. The dielectric membrane is compatible with most
`higher temperature IC processing techniques.
`MDI Fabrication Process
`
`Several process variations can be used to form the
`thin film or membrane of semiconductor material for
`use in the MDI process. Additional related methods for
`forming semiconductor membranes may exist or come
`into existence and are included in the MDI technology.
`Examples of some of the methods that can be used for
`forming silicon single crystal thin films are:
`1. Heavily boron doped (typically greater than 1013
`atoms/cmz) etch stop layer (formed by diffusion, im-
`plant or epitaxy) with optional epitaxial SiGe (less than
`20% Ge) anti—autodoping overlayer layer and optional
`epitaxial layer.
`2. 02 (oxide) and N2 (Nitride) implant etch stop bar-
`rier layer. Implant concentrations are typically between
`10 to 100 times less for formation of an etch stop barrier
`layer than that required to form a buried oxide or nitride
`dielectric isolation layer as presently done with a stan-
`dard thickness silicon substrate.
`3. Buried oxide etch stop barrier layer formed from a
`porous silicon layer.
`4. High precision double sided polished substrate and
`masked timed chemical etch back of back-side.
`5. Electro-chemical etch stop.
`6. Buried etch stop layer formation through anodic or
`thermal wafer bonding in combination with precision
`substrate polishing and chemical etching.
`There are many established methods for forming thin
`semiconductor substrates or membranes. The MDI
`process requires that
`the semiconductor membrane
`forming process (thinning process) produce a highly
`uniform membrane typically less than 2 pm thick and
`that the surface tension of the semiconductor membrane
`be in low tensile stress. If the membrane is not in tensile
`
`35
`
`45
`
`50
`
`55
`
`65
`
`6
`stress, but in compressive stress, surface flatness and
`membrane structural integrity will in many cases be
`inadequate for subsequent device fabrication steps or
`the ability to form a sufficiently durable free standing
`membrane.
`
`The use of highly doped layers on the surface or near
`the surface of the substrate formed by diffusion, implant
`or epitaxial means is an established method for forming
`a barrier etch stop layer. A heavily doped boron layer
`will etch 10 to 100 times slower than the rest of the
`substrate. However, if it is to form an effective uniform
`membrane surface, autodoping to the lower substrate
`and to the upper device layer must be prevented or
`minimized. This is accomplished in one method by epi-
`taxially growing a SiGe layer of less than 4,000./ii
`(1A=10-1°m) and less than 25% Ge on either side of
`the barrier etch stop. The SiGe layers and the barrier
`etch stop layers are subsequently removed after forma-
`tion of the membrane in order to complete device di-
`electric isolation.
`
`The MDI process for forming a dielectric membrane
`requires that the dielectric material be deposited in net
`surface tensile stress and that the tensile surface stress
`level be 2 to 100 times less than the fracture strength of
`the dielectric. Consideration is also given to matching
`the coefficient of thermal expansion of the semiconduc-
`tor material and the various dielectric materials being
`used in order to minimize the extrinsic net surface stress
`of the membrane. Thermally formed silicon dioxide
`forms as a strongly compressive film and most depos-
`ited dielectrics currently in use form typically with
`compressive surface stress. High temperature silicon
`dioxide and silicon nitride dielectric deposited films
`with tensile surface stress levels 100 times less than their
`fracture strength have been demonstrated as large area
`free standing membranes consistent with the require-
`ments of the MDI process.
`It is not a requirement of the MDI process that if a
`semiconductor material is used in the fabrication of a
`circuit membrane, that the semiconductor material be
`capable of forming a free standing membrane. The di-
`electric materials that are optionally used to isolate any
`semiconductor devices in the circuit membrane can
`
`provide the primary structural means of the resulting
`circuit membrane as implied by the general fabrication
`methods presented below.
`The ability to form large durable temperature toler-
`ant low tensile stress films of both semiconductor and
`
`dielectric materials as components or layers of a sub-
`strate for the fabrication of integrated circuits and inter-
`connect structures is unique to the MDI process. The
`large free standing semiconductor and dielectric mem-
`brane substrates of the MDI process provide unique
`structural advantages to lower the cost and complexity
`of circuit fabrication and enhance the performance of
`circuit operation.
`The MDI process can be broadly described as two
`methods, depending on which method of forming the
`semiconductor substrate thin film is selected. The se-
`
`quence of steps of the two process methods presented
`below may be utilized in a different order depending on
`processing efficiencies. Formation of polysilicon or a-Si
`(amorphous silicon) circuit devices on a dielectric mem-
`brane without the starting use of a semiconductor sub-
`strate is disclosed below, but is not categorized as a
`method.
`
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`7
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`Method #1
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`5,354,695
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