PAUL D. FRANZON
`
`
`B. BRIEF RESUME
`
`1. Education
`
`
`• Doctor of Philosophy, Electrical and Electronic Engineering 1989, University of
`Adelaide, Australia . Advisor: Kamran Eshraghian.
`• Bachelor of Engineering with First Class Honours, Electrical and Electronic En-
`gineering: 1984, University of Adelaide, Australia
`• Bachelor of Science, Physics and Mathematics: 1983, University of Adelaide,
`Australia.
`
`
`2. Professional Experience
`
`
`• Assistant Professor, Associate Professor, and Professor, North Carolina State
`University, Department of Electrical and Computer Engineering, Raleigh, North
`Carolina, January 1989 - present
`• Cofounder, LightSpin Technologies Inc., 2001-. Vice-President of Engineering,
`2001-2002, Raleigh NC.
`• PhD Candidate, University of Adelaide, Department of Electrical and Electronic
` Engineering, Adelaide, South Australia, Australia, April 1987 - December 1988.
`• Director and Co-Founder, Network Communications Pty. Ltd., Adelaide, South
`Australia, Australia, April 1987 - April 1989.
`• Consultant, AT&T Bell Laboratories, Holmdel NJ, January 1986 - April 1987.
`• PhD Candidate, University of Adelaide, Department of Electrical and Electronic
`Engineering, Adelaide, South Australia, Australia, August 1984-December 1985.
`• Engineer, Defence Science and Technology Organization, Salisbury, South Aus-
` tralia, Australia, January 1984--July 1984
`Intern, Defense Science and Technology Organization, Salisbury, South Austra-
`•
`lia, Australia, December 1982--March 1983.
`Intern, Telecom Australia, Adelaide, South Australia, Australia, December 1981-
`•
` March 1982.
`Infantry Soldier and Officer, (Ranks held: Private - Captain), Royal Australian
`•
` Infantry Corps, Australian Army Reserve, December 1979 - December 1991.
`
`
`3. Scholarly and Creative activities
`
`
`
`Number
`
`
`
`Type
`-------------------------------------------------------
`Books
`
`
`
`3
`Solution Manuals
`
`
`1
`Edited Book
`
`
`
`11
`Refereed Journal article
`
`78
`Other Journal (submitted)
`
`2
`
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`

`
`192
`17
`38 conference + 56 other
`
`Conference Paper (refereed)
`Patents filed
`
`
`
`Research Presentations, Invited
`
`4. Membership in professional organizations
`
`Fellow, Institute of Electrical and Electronic Engineers, 1984-
`Member, IMAPS
`Member, SPIE
`Member, Association of Computing Machinery
`
`5. Scholarly and professional honors
`
`
`• NRL Alan Berman Research Publication Award, 2008
`• Babbage Award, Synopsys, 2008
`• Fellow of the IEEE, 2006
`• Alcoa Research Award, 2005
`• ECE Graduate Teacher of the year award, 2007
`• ECE Most Helpful Teacher of the year award, 2007
`• ECE Teacher of the year award, 2006
`• ECE Graduate Advisor of the year award, 2006
`• Alumni Undergraduate Distinguished Professor, 2003-2005.
`• Graduate teacher of the year, ECE department, 2005
`• NSW Australia Expatriate Scientist Award, 2003
`• Selected to the NCSU Academy of Outstanding Teachers, 2001
`• First round prize winner, SRC copper challenge, 2000.
`• Teacher of the Year Award, presented by the IEEE Student Branch, 1997
`• National Science Foundation Young Investigator's Award, 1993.
`• 13 prizes while a student at the University of Adelaide
`
`
`6. Professional service on campus
`
`
`• Member, STRAG 2003-2005
`Instructor, PE preparation course 1995-2000
`•
`
`
`7. Professional service off campus
`• Consultant to Lerner, David, Littenberg, Kruholz and Mentlik, 2013, Patent issues
`• Consultant to DARPA, thermal evaluation, 2012-13
`• Consultant to DARPA, Exascale Computing Study, 2007-9.
`• Consultant to Rambus, Semiconductors, 2009-
`• Consultant to Techsearch, 2008.
`• Consultant, NTU, 2004-9. ASIC Design.
`• Consultant to Tessera, 2009. 3DIC advising.
`• Consultant, Irvine Sensors, 2006. Secure chip design.
`• Consultant, Cisco Systems, 2006, Signal Integrity.
`
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`
`• Consultant, Talon Logic, 2005. Secure system Design.
`• Consultant to O'Malveny and Meyers, 2000-2002, Patent issues.
`• Consultant to Venture 2000, 2000, Due Diligance.
`• Consultant to CAPPS, 1999-2000, IP Development.
`• Consultant to Sofrent, 1999-2000, IP Development.
`• Consultant to Ericsson, 1997, Synthesis Methodology.
`• Consultant to Cadence, 1996. Evaluated possible company acquisition.
`• Consultant to Polychip, 1994 - 2000. Circuit Design.
`• Consultant to Square-D, 1996. Interconnect Design.
`• Consultant to Mentor Graphics, 1995, 1996. Technical advisory board.
`• Consultant to Cadence Design Systems, 1992, 1996. Technical advisory board.
`• Consultant to DCT, 1995-1996. ASIC Design.
`• Consultant to Techsearch International, 1989-1991. Report Preparation.
`• Consultant to BNR, HP, Sun. 1992-4. Interconnect Design.
`• Consultant to MCNC, 1989. CAD
`
`
`When
`
`Enrollment
`
`Sum ‘12
`ECE 520-651 ASIC Design
`S 2012
`ECE 733 Digital Electronics
`S 2012
`ECE 520-601
`S 2012
`ECE 520-001 ASIC Design
`S 2012
`ECE 464 ASIC Design
`ECE 406 Des. Complex Systems F 2011
`ECE 520-651 ASIC Design
`Sum ‘11
`ECE 733 Digital Electronics
`S 2011
`ECE 520-601
`S 2011
`ECE 520-001 ASIC Design
`S 2011
`ECE 464 ASIC Design
`S 2011
`ECE 406 Des Complex Systems
`F 2010
`ECE 733 Digital Circuits 001
`S 2010
`ECE 733 Digital Circuits 601
`S 2010
`ECE 520 ASIC Design 001
`S 2010
`ECE 520 ASIC Design 601
`S 2010
`ECE 464 ASIC Design
`S 2010
`ECE 733 Digital Circuits 001
`S 2009
`
`18
`52
`12
`116
`14
`58
`13
`18
`12
`75
`25
`75
`36
`3
`57
`17
`9
`57
`
`
`II. TEACHING AND MENTORING OF UNDERGRADUATE AND
`GRADUATE STUDENTS
`
`A. TEACHING EFFECTIVENESS
`
`1. Courses Taught
`
`Course
`
`Instructor
`effectiveness
`
`4.2
`4.3
`4.3
`4.3
`4.6
`4.2
`4.5
`4.3
`4.5
`4.5
`4.6
`4.3
`5.0
`4.3
`4.2
`4.3
`4.6
`
`Course
`excellence
`
`4.2
`4.2
`4.3
`4.3
`4.6
`4.2
`4.5
`4.2
`4.5
`4.5
`4.6
`4.2
`5.0
`4.4
`4.4
`4.4
`4.5
`
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`

`
`7
`128
`17
`1
`16
`67
`2
`101
`15
`27
`58
`129
`6
`17
`20
`43
`65
`8
`17
`30
`5
`44
`34
`2
`15
`13
`45
`76
`17
`69
`84
`81
`30
`63
`167
`239
`
`39
`
`S 2009
`ECE 733 Digital Circuits 601
`S 2009
`ECE 520 ASIC Design 001
`S 2009
`ECE 520 ASIC Design 601
`S 2009
`ECE 520 ASIC Design 620
`S 2009
`ECE 464 ASIC Design
`S 2008
`ECE 733 Digital Circuits 001
`S 2008
`ECE 733 Digital Circuits 601
`S 2008
`ECE 520 ASIC Design 001
`S 2008
`ECE 520 ASIC Design 601
`S 2008
`ECE 464 ASIC Design
`S 2007
`ECE 733
`S 2007
`ECE 520 ASIC Design 001
`S 2007
`ECE 520 ASIC Design 601
`S 2007
`ECE 464 ASIC Design
`F 2006
`ECE 745 ASIC Verification
`S 2006
`ECE 733 Digital Circuits 001
`S 2006
`ECE 520 ASIC Design 001
`S 2006
`ECE 520 ASIC Design 601
`S 2006
`ECE 464 ASIC Design 001
`S 2005
`ECE 733 Digital Circuits 001
`S 2005
`ECE 733 Digital Circuits 601
`S 2005
`ECE 520 ASIC Design 001
`S 2005
`ECE 520 ASIC Design 002
`S 2005
`ECE 520 ASIC Design 601
`S 2005
`ECE 464 ASIC Design 001
`S 2005
`ECE 464 ASIC Design 002
`S 2004
`ECE 733 Digital circuits
`S 2004
`ECE 520 ASIC Design
`S 2004
`ECE 520 ASIC Design 601
`S 2004
`ECE 464 ASIC Design
`S 2003
`ECE 733 Digital Circuits
`S 2003
`ECE 520 ASIC Design
`S 2003
`ECE 520 ASIC Design 601
`S 2003
`ECE 464 ASIC Design
`F 2002
`ECE 406 Design Complex DS
`S 2002
`ECE 520 ASIC Design
`S 2002
`ECE 520 ASIC Design 601
`S 2002
`ECE 464 ASIC Design
`ECE 406 Des. Complex Dig Sys F 2000
`ECE 704 Design For Test
`F 2000
`ECE 520 ASIC Design 001
`S 2000
`ECE 520 ASIC Design 002
`S 2000
`ECE 520 ASIC Design 601
`S 2000
`ECE 492B ASIC Design
`S 2000
`ECE 342 Des. Complex Dig Sys F 1999
`
`
`
`
`
`
`
`
`
`4.4
`4.6
`4.5
`
`4.6
`4.64
`
`4.76
`4.5
`4.76
`4.64
`4.75
`
`4.75
`
`4.5
`
`
`4.4
`4.5
`
`4.6
`4.6
`
`4.9
`4.9
`4.2 (4.1)
`4.4 (4.1)
`
`4.5 (4.1)
`4.3 (4.0)
`4.2 (4.0)
`
`3.9 (4.0)
`4.2 (4.1)
`4.4 (4.1)
`
`4.1 (4.1)
`4.7 (4.0)
`4.6 (4.0)
`4.5 (4.1)
`4.6 (4.1)
`
`4.5 (4.1)
`4.4 (4.1)
`
`
`
`
`
`4.2
`4.4
`4.20
`
`4.4
`4.64
`
`4.59
`4.20
`4.59
`4.46
`4.68
`
`4.68
`4.6
`4.6
`
`
`4.1
`4.6
`
`4.3
`4.5
`
`4.1
`4.1
`4.2 (3.9)
`4.3 (3.9)
`
`4.0 (3.9)
`4.2 (3.8)
`3.9 (3.8)
`
`3.5 (3.8)
`3.8 (3.9)
`4.2 (3.9)
`
`3.6 (3.9)
`4.5 (3.7)
`4 (3.8)
`4.4 (3.9)
`4.3 (3.9)
`
`4.3 (3.9)
`4 (3.9)
`
`
`
`
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`
`
`
`
`
`
`
`
`
`4.6 (4.2)
`4.5 (4.2)
`4.3 (4.1)
`4.6 (4.1)
`4.7 (4.1)
`4.6 (4.0)
`4.7 (4.1)
`4.7 (4.1)
`
`
`4.5 (4.0)
`4.3 (4.0)
`4.1 (3.9)
`4.4 (3.9)
`4.8 (4.1)
`4.4 (4.0)
`4.7 (3.9)
`4.4 (3.9)
`
`
`S 1999
`ECE 520 ASIC Design 005
`S 1999
`ECE 520 ASIC Design 006
`ECE 342 Des. Complex Dig Sys F 1998
`ECE 520 ASIC Design
`S 1998
`ECE 492B ASIC Design
`S 1998
`ECE 342 Des. Complex Dig Sys F 1997
`ECE 520 ASIC Design
`S 1997
`ECE 492B ASIC Design
`S 1997
`
`AVERAGE
`
` •
`
` ECE 342 Design of Complex Digital Systems, Fall 1996, Overall Rating: 4.6/5.0.
`• ECE 592B ASIC Design, Spring 1996, Overall Rating: 4.75/5.0. (With Dr. Liu.)
`• ECE 492B ASIC Design, Spring 1996, Overall Rating: 4.00/5.0. (With Dr. Liu.)
`• ECE 544, Design of Electronic Packaging and Interconnects, Spring 1999, Overall
`Rating : 4.60/5.0.
`• ECE 520, Fundamentals of Logic Systems, Fall 1995, Overall Rating: 4.50/5.0.
`• ECE 218, Computer Organization and Microprocessors, Both Sections, Spring,
`1995: Section 001: 4.45/5.0; Section 002: 4.62/5.0.
`• ECE 592V, VLSI Microprocessor Project, Spring 1995. (13 students but not rated).
`• ECE 681/693A, Computer Engineering Seminar. Spring 1996 and Fall 1996.
`• ECE 521 Computer Design and Technology, Fall 1994, Overall Rating: 4.24/5.0.
`• ECE 691F, High Speed VLSI, Fall 1994, Overall Rating: 4.45/5.0.
`• ECE 691P, Superscalar Processor Design, Spring 1994, Overall Rating: 4.67/5.0.
`• ECE 591F, Design of Electronic Packaging and Interconnects, Spring 1994, Overall
`Rating: 4.60/5.0.
`
`
`
`B. INSTRUCTIONAL DEVELOPMENT
`
`
`
`1. NSF-funded CISE Infrastructure effort, “Experimental High Performance
`Computing and Communications Systems''. (Total: $1,338,283 including $503,046 in
`matching.) Approximately $283,000 of this funding went towards outfitting the ECE
`Design Center.
`
`2. CAD Tools. Modern design is done with sosphisticated Computer – Aided Design
`Tools, not with pencil and paper. I have spent considerable effort bringing such tools
`into the Unity environment, gaining the `corporate knowledge' about how to use these
`tools effectively and obtaining additional computers for use with these tools. Students tell
`me that knowledge of these tools is highly regarded by potential employers. In fact one
`student stated that `Dr. Franzon teaches courses that gets jobs'. In addition , in 1999,
`we won the Cadence University Alliance Best Web site Awards. Through my funded
`research efforts and Corporate Donations introduced the following Computer Aided
`Design Tools into the curricula:
`
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`•
`
`• Cadence Design Systems. A complete suite of over 4 GB of executables
`that facilitate chip, board and system design, with a retail value of over
`$100,000,000. Cadence donates these tools because of the widespread
`recognition of our contributions to CAD. (i.e. It waives the $5,000 fee.)
`• Synopsys. The industry leading chip (ASIC) synthesis tool,with a retail
`value of over $7,000,000.
`In 2008, NCSU won the “Babbage Award” from Sun and Synopsys, in
`recognition of our contributions towards lab infrastructure. The award comes
`in the form of $15,000 of computers.
`• Mentor. We integrate some mentor graphics tools with the other tools above.
`The tools have a retail value of over $5,000,000. Mentor donates these tools
`because of the widespread recognition of our contributions to CAD.
`• In 2010/2011 and 2011/2012 Mentor donated $30,000 to the University to
`assist in CAD infrastructure development.
`As well as obtaining these tools, my group has spent considerable effort making these
`tools useful to us by writing integration scripts and generating `know-how'. Much of this
``know-how' has been published on the Web and in our own lockers. Most of this learning
`was conducted driven by research needs and serves as an excellent example of the
`integration of research and teaching. This work is ongoing. For example, over 2000
`organizations world-wide, use our “Physical Design Kit”..
`
`3. ECE 745. ASIC Verification. I introduced this course in 2007, though it was taught by
`Meeta Yadav.
`
` 4. ECE 342, Design of Complex Digital System, Fall 1996:
`• Completely redesigned and updated course to reflect modern design practices,
`and use of modern Hardware Description Languages and Design Tools.
`• Completed a new laboratory course ECE 342L for use with this course.
`
` 5. ECE 520 ASIC Design (formerly `Fundamentals of Logic Systems'), Spring 1997:
`• Based on my teaching of ECE592B in Spring 1995, this course has been
`completely updated to reflect modern design practices, modern tools, and
`emphasize an understanding of algorithms used in modern tools. (`ASIC'
`stands for `Application Specific Integrated Circuit'. For example the chips in
`a satellite dish receiver are ASICs. ASIC engineering is the fastest growing
`area of ECE today.)
`• Once the course action forms are approved, this course will be taught concurr-
`ently with ECE 420 ASIC Design.
`
`
`
`
`
`
`
`6. ECE 544, Design of Electronic Packaging and Interconnects, Spring 1995. New c-
`ourse emphasizing `transmission line effects' in electronic packages and how to design
``deep sub-micron interconnect'. I receive tremendous demand from ind-
` ustry
`for graduates from this course.
`
`7. ECE 691/693A, Computer Engineering Graduate Seminar
`
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`
`• Created new seminar course (with Dr. Tom Conte) for computer engineering
`students.
`• Recruited and scheduled weekly speakers.
`
`
`8. ECE CAD Lab. $75,000. Provost Office, 1995.
`
`C. MENTORING ACTIVITIES
`
`UNDERGRADUATE STUDENT SUPERVISION
`1. 2012. Spring advisor to two undergraduates.
`2. 2010. Summer REU supervisor to three Undergraduates
`3. 2009. Summer REU supervisor to one Undergraduate.
`4. 2009. Supervised Senior Design Team
`5. 2008. Summer REU supervisor to two Undergraduates.
`6. 2005 Andrew Pita, SRC Undergraduate Research Fellowship
`7. 1999 Ecoh Oh, NSF Undergraduate Research Award
`8. 1999 Ben Hughes, NSF Undergraduate Research Award
`9. 1993- Numerous Senior Design projects
`
`
`GRADUATE STUDENT SUPERVISION
`
`GRADUATE COMMITTEES
`
`Currently member of 20+ PhD and 10+ MS committees. Advisor to 20+ non-thesis MS
`students. (I don’t track the exact numbers.)
`
`GRADUATE COMMITTEES
`
`For a list of graduate committees I chair, see below. I am on numerous committees as a
`member, but I do not track the numbers.
`
`D. MASTER’S AND DOCTORAL THESES DIRECTED AND BEING
`DIRECTED
`
`
`
` I
`
` am actively directing the theses of 21 Ph.D. students and 4 Master with thesis option
`(MST) students. I have graduated 33 Ph.D. students and 43 MST students.
`
`Masters and Doctoral Theses under direction
`
`
`Student Name
`
`Zhou Yan
`Weiyi Qui
`Josh Ledford
`
`Degree [date]
`
`PhD [12/14]
`MS [08/13]
`PhD [12/15]
`
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`
`PhD [08/13]
`PhD [12/13]
`PhD [12/13]
`PhD [12/13]
`PhD [03/12]
`PhD [06/13]
`PhD [10812]
`PhD [12/12]
`PhD [12/14]
`PhD [12/14]
`PhD [12/14]
`MS [10513]
`PhD [12/12]
`MS [05/12]
`MS [12/14]
`MS [12/14]
`MS [12/14]
`
`Shivam Priyadarshi
`Evan Erickson
`Shep Pitts
`David Winick
`Eric Wyers
`Gary Charles
`Peter Gadfort
`Akalu Lentiro
`Marcus Tshibangu
`Randy Widialaksono
`Zenquian Zhang
`Wenxu Zhao
`Jon Beom Park
`Ataul Karim
`Luther Blackwood
`Len Rousch
`Mo Chen
`
`Doctoral Theses Directed
`
`1. Eric Wyers, “Direct Search Calibration Algorithms for Digitally Reconfigurable
`Radio Frequency Integrated Circuits,” March 2013.
`2. Ojas Ashok BOpat, “A Generic Scalable Architecture For a Large Acoustic Model
`and Large Vocabularly Speech Recognition Accelerator,” October, 2012.
`3. Won Hao Choi, “System Level Power Prediction Methodology for Mobile 3-D
`Graphic Engines,” May 2012.
`4. Hsuan-Jung Su, “Continuous-Time Fractionally Spaced Equalization and Its
`Application in Capacitively Coupled Chip-To-Chip Interconnect,” May, 2012.
`5. Hsuan-Jung Su, “Continuous-Time Fractionally Spaced Equalizatoin and its
`Application to Capactively Coupled Chip-TO-Chip Interconnect”, January 2012.
`6. Matthew Hamlett, “A Novel Approach to IP Protection Using Automated
`Hardware Techniques to Secure a Design,” March 2012.
`7. Mustafa Berke Yelten, “Variability and Reliability in Nanoscale Circuits:
`Simulation, Desgin, Monitoring and Characterization,” January, 2012.
`8. Hoon Seok Kim, “Advanced Multi Mode Interconnect,” December, 2011.
`9. Xiangzhong Xue, “Electronic System Optimization Via Convex Programming,”
`December, 2011.
`10. Tsing Zhu, A Surrogae Model-based Framework for Design and Macromodeling
`of Self-calibrated Analog Circuits,” October, 2011.
`for High-Density Links:
`“Multimode
`Interconnect
`11. Chanyoun Won,
`Implementation, Design Methodology and New Crosstalk Cencallation Scheme,”
`July 2011
`12. Thor Thorolfsson, “Three Dimensional Integration of Synthetic Aperture Radar
`Processors,” April 2011
`13. Daniel Schinke, “Computing with Novel Floating Gate Devices,” April 2011
`
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`14. Yongjin Choi, “Design of Multimodel Signaling Transceiver for High-Density and
`High-Speed Links,” May 2010.
`15. Eun Chu Julie Oh, Ph.D. Dissertation, “Design and Applications of Three-
`Dimensional Circuits”, December, 2009.
`16. Karthik Chandrashekhar, Ph.D. Dissertation, “Inductively Coupled Connectors,”
`December, 2008
`17. Dhruba Chandra, Ph.D. Dissertation, Speech Recognition CoProccessor,
`December, 2007.
`18. Meeta Yadav, “Hardware Architecture of behavior Modeling Coprocessor for
`Network Intrusion Detection,” Ph.D. Dissertation, March, 2007.
`19. Ullas Pazhayaveetil, “Hardware Implementation of a Low Power Speech
`Recognition System,” Ph.D. Dissertation, February, 2007.
`20. Jian Xu, “AC Coupled Interconnect for Inter-Chip Communications,” Ph.D.
`Dissertation, December, 2006.
`21. Ambrish Varma, “Improved behavioral modeling based on Input Output Buffer
`Information Specification,” Ph.D. Dissertation, NCSU, October, 2006.
`22. Sachin Sonkusale, “Planar edge defined alternate layer process (PEDAL) – an
`unconventional technique for the fabrication of wafer scale sub-25 nm nanowires
`and nanowire template,” PhD, October, 2006.
`23. Liang Zhang, “Driver Pre-emphasis Signaling for on-chip global interconnects,”
`Ph.D. Dissertation, September, 2006.
`24. Monther Al Dwairi, “Hardware Efficient Pattern Matching Algorithms and
`Architectures for Fast Intrusion Detection,” Ph.D., November, 2006.
`25. John Damiano, “Active body bias for low-power silicon-on-insulator design,”
`Ph.D., March 2006.
`26. Neil DiSpigna, “Electronic Devices and Interface Strategies for Nanotechnology,”
`Ph.D., April 2006.
`27. Christian Amsinck, “Molecular Electronic Memories,” Ph.D., March 2006.
`28. Lei Luo, “Capacitively Coupled Chip to Chip Interconnect Design, Ph.D.,
`December, 2005.
`29. Leon Zhang, “Driver pre-emphasis signaling for on-chip global interconnects,”
`Ph.D., December, 2005.
`30. Steve Lipa, “Phase Noise Analysis of Rotary Oscillators,” Ph.D. May 24, 2005
`31. David Nackashi, Circuit and Integration Technologies for Molecular Electronics,
`Ph.D. 2004
`32. Stephen Mick, AC Coupled Interconnect, Ph.D. 200
`33. John Wilson, Linearly Tunable RF MEMS Capacitors Implemented Using an
`Integrated Removable Self-Masking Technique, Ph.D. 2004
`34. Andrew Stanaski, Sensor Circuits for Flip Chip Debug, Ph.D. 2004
`35. Pronita Mehrotra, High Performance Hardware Memory Algorithms, Ph.D. 2003
`36. Bruce Duewer, MEMS Switch Fabric, Ph.D.
`37. Toby Schaffer, Chip-package Codesign, Ph.D.
`38. Mouna Nakkar, Dynamically Programmable Cache, Ph.D.
`39. Mir Azam, Custom CMOS Design and Architecture for Low-Power High-
`Performance Circuits, PhD.
`40. Debu Ghosh (co-chair), Synthesis of Benchmarking Expiriments, Ph.D.
`
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`
`41. Chris Harvatis, Performance Driven Partitioning for MCMs, PhD.
`42. Slobodan Simovich, Computer-Aided Analysis of Interconnect,PhD.
`43. Scott Washabaugh, Low energy FSM Design, PhD.
`44. Sharad Mehrotra, Automated Synthesis of High Speed Digital Circuits and
`Package-Level Interconnect, PhD.
`45. Todd Cook, Instruction Set Architecture Specification, PhD.
`46. Robert Evans, Energy Consumption for Modeling and Optimization of SRAMs,
`PhD.
`
`Masters Theses directed
`
`1. Vinod Kotipllai, “Impact of Process Variations on 16-nm Dual Floating Gate FET
`using TCAD simulations,” December 2012.
`2. Shiney Gupta, “Multi-Storey Stacked Driver Topolo9gy for Reduced Swing and
`Low Power Bus Operation,”, May 2012.
`3. Pattabhiraman Ravindran, “Harvesting Thermal Energy to Power Agricultural
`Sensors,” October, 2011.
`4. Alex Leaonard, “Implementation of a System-on-Chip for self-healing of analog
`receiver components in a 65 nm CMOS process”, May 2011
`5. Seema Kumar, “Memory Diesgn for Sensor IC,” May 2010.
`6. Mihir Shiveshwarkar, “A Nanocrystal Floating Gate Flash Analog to Digital
`Converter,” December, 2009.
`7. Ojas Bapat. “Design of DDR2 Interface for Tezzaron TSC8200A Octupus
`Memory intended for Chip Stacking Applications,” April 2009.
`8. Peter Gadfort, “Low power driver for silicon carrier interconnects,” April 2009.
`Interconnect
`for Chip
`to Chip
`9. Chintan Shah, “Inductively Coupled
`Commmunication over Transmission Line,” Feb 2009.
`10. Kiran Gonsalves, “Memory Design for FFT Processor in 3DIC Technology,”
`March, 2009.
`11. Vinay Honnavara, “Cost optimization by method of allocating software component
`units to electronic control units for model-driven designs,” October, 2008.
`12. Wei Cao, “Design of temperature sensors for validation of aseptic food
`processing,” Sept. 2008.
`13. Akalu Lentiro, “Implemention of AC Coupled Interconnect Test Vehicle,” May,
`2008.
`14. Vinayak Devasthali, “Application of body biasing and supply voltage scaling
`techniques for leakage reduction and performance improvement of CMOS
`Circuits,” December 2007.
`15. Paul Fernando, “Adding scalability to IBIS using AMS Languages,” September
`2007.
`16. Vivek Jayadav, “Hardware-Software Codesign of a Large Vocabularly Speech
`Recognition System,” February, 2007.
`17. Srivatsan Parthasarathy, “Interfacing AC Coupled Interconnect Design with
`Rocket I/O compatible FPGA Systems,” December 2006.
`18. Janani Mukundan, “Instruction Cache Checkpoints Using Phase Tracking and
`Prediction,” June 2006.
`
`SAMSUNG ET AL. EXHIBIT 1003
`Page 10 of 54
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`

`
`19. Yasaswini Sudarsanam, “Implementatin of Double Precision Floating Point
`Arithmetic for Matrix Multiplication,” October 2006
`20. Itisha Tyagi, “Design of array based row decoders and self-referencing sense
`amplifier for large scale resistance change style molecular memories,” June 2006.
`21. Indraneel Kelkar, “Tradeoffs involved in the design of SRAMs,” December 2005.
`22. Wallace Pitts, “Partially depleted silicon on insulator phase lock loop design,”
`January, 2006.
`23. Janani Mukundan, “Instruction cache checkpoints using phase tracking and
`prediction,” December 2006.
`24. Deepak Kumar, ”Design of fully integrated wireless CMOS MEMS device for
`intraocular pressure measurement,” March 2006.
`25. Manav Shah, “Design of a self-test vehicle for AC Coupled Interconnect
`Technology,” May 2006.
`26. Andrew Morgan, Design Flow based on Sensitivity Analysis for High Speed
`Digital Circuits, MS, 2004
`27. Brian Phelp, Hardware Realization and Implementation Issues for the Sliding
`Window Packet Switch, MS, 2004
`28. Ishdeep Sawhney, Hardware Forwarding for IPV6, MS, 2003
`29. Kaustabh Bhate, MEMS Design for textiles sensor, MS
`30. Praveen Prasad, Reconfigurable Computing for Network Security, MS
`31. Patrick Lall, Verification of a Network Processor, MS
`32. Ambrish Varma, SHOCC Design Tools, MS
`33. Karthik Chandrasekhar, Hardware to support multicast in all-optical networks,
`34. M.V. Parameshawara (co-chair), Enhancement of NC Agricultural Automated
`Weather Network and Development of Advanced Communication, Data
`Acquisitions amd Dissemation System, MS.
`35. Jeremy Palmer, Design and Analysis of a VLSI-MEMS-Based Diffractive Optical
`Beam Steering System, MS.
`36. Som Chaudry, MEMS devices for laser radar, MS.
`37. Srisai Rao, Design, place and route of an IDEA processor, MS.
`38. Kevin Mock, IDEA Implementation, MS.
`39. Sibi Kuruvilli, Synthesized SAND Issue Unit, MS
`40. Tom Mills, Macromodelling of high speed digital drivers and receivers, MS.
`41. Matreiya Sengupta, Managing Crosstalk in Interconnect Design, MS.
`42. Andrew Stanaski, Optimizing Memory Design for Packagability, MS.
`43. Jonathon Schaeffer, A 400 MHz CMOS Multiplier, MS.
`44. Harsh Deshmane, MCM Extractor in Magic, MS.
`45. Sha Ma, Circuits for Low Energy Computing, MS.
`46. Shauki Elassaad, Placement tools for multi-chip modules, MS.
`47. Alex Dalal, CAD tools for yield estimation, MS.
`
`
`Committee Memberships: Do not track
`
`III. SCHOLARSHIP IN THE REALMS OF FACULTY
`RESPONSIBILITY
`
`
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`

`
`A. PUBLICATIONS AND AWARDS
`
`BOOKS
`
`1. Smith and P. Franzon: Verilog Styles for Synthesis of Digital Systems, 2000, by
`Prentice Hall.
`
`2. D. Doane and P. Franzon: Multichip Modules: Basics and Alternatives, 1993, by
`Van Nostrand Rheinhold.
`
`3. J-D Cho and P.D. Franzon, High Performance Design Automation for Multi-Chip
`Modules and Packages, 1996, World Scientific.
`
`
`BOOK CHAPTERS
`
`1. P. Franzon, “Use of AC Coupled Interconnect in Contactless Packaging,” appear in
`“Coupled Data Communications,” Ron Ho (ed), Springer-Verlag, Fall 2009
`
`
`2. P. Franzon, Design for 3-D Integration, 3-D IC Integration: Technology and
`Applications, P. Garrou, P. Ramm, C. Bower, (editors), Wiley VCH, May 2008.
`
`
`3. P. D. Franzon, D. Nackashi, C. Amsinck, N. DiSpigna, S. Sonkulale, “Molecular
`Electronics – Devices and Circuits Technology”, in Vlsi-Soc: From Systems To
`Silicon, (Springer Boston), Oct. 2007.
`
`
`4. P. Franzon, Chip-Package Codesign, in The Handbook for EDA of Electronic
`Circuits, Lou Scheffer, Luciano Lavagno and Grant Martin (editors), CRC Press,
`2005.
`
`
`5. P. Franzon, Multichip Module Technology, to appear in the The Electronic Handbook,
`J. Whitaker (editor), (CRC Press), 1996.
`
`
`6. S. Mehrotra and P. Franzon, Performance Driven Global Routing and Wiring Rule
` Generation for High Speed PCBs and MCMs , in Advanced Routing of Electronic
` Modules, M. Pecht (editor), (Kluwer), 1995.
`
`7. P. Franzon and Michael Steer: Tools and Techniques for the Design of High Speed
`Multichip Modules}, Chapter 7 in Electronics Packaging Forum,Volume 3, J. Mor-
`ris (ed), 1993 by IEEE Press.
`
`8. P. Franzon, Comparison of Reconfiguration Schemes for Defect Tolerant Mesh
`
`Arrays , in Defect and Fault Tolerance in VLSI Systems, Volume 2, V.K. Jain
`
`(editor), (Plenum), 1989.
`
`
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`

`
`9. M. Hatamian, L.A. Hornak, T. Little, S.K. Tewksbury and P. Franzon: Fundamen-
`tal interconnection issues in, Electronic Materials Handbook,Volume 1:Packaging,
`
` Article 1BA (ASM International), 1989, pages 1-11.
`
`
`10. P. Franzon and S.K. Tewksbury: ‘Chip Frame’ scheme for reconfigurable mesh-
`
`connected arrays, in Wafer Scale Integration II, R.M. Lea (editor), (North Holl-
`
`and), 1988.
`
`
`11. P.D. Franzon: Yield Modeling for Fault Tolerant VLSI ,in Systolic Arrays, W.
` Moore, A. McCabe and R. Urquhart (editors), (Adam Hilger), 1987.
`
`
`JOURNAL PUBLICATIONS
`
`
`
`1. W. H. Kim, C. Won, and P. Franzon, “Crosstalk cancelling multi-mode interconnect
`using transmitter encoding,” in Proc. IEEE TVLSI, Vol. PP, No. 99, 2013.
`
`2. T. Zhu, M. Steer, P. Franzon, “Surrogate model-baseed self-calibrated design for
`process and temperature compensation in Analog/RF circuits,” in IEEE Design and
`Test, Vol. PP, No. 99, 2013.
`
`3. M.B. Yelten, P.D. Franzon, M.B. Steer, “Analog Negative Bias Temperature
`Instability Monitoring Circuit,” in IEEE Trans. Device and Materials Reliability, Vol.
`12., No. 1, 2012, pp. 177-179.
`
`
`
`4. R.T. Harris. S. Priyadarshi, S. Melamed, C. Ortega, M. Rajit, S. Doorly, N. Kriplani,
`W. Davis, P. Franzon, M. Steer, “A transient electrothermal analysis of three-
`dimensional integrated circuits,” in IEEE Trans. CPMT, Vol. 2, No. 4, 2012, pp. 660-
`667.
`
`5. S. Priyadarshi, C. Saundrs, N Kriplani, H. Demiricoglu, W. Davis, P. Franzon, M.B.
`Steer, “Parallel transient simulation of multiphysics circuits using delay-based
`partitioning,” in IEEE Tran. CAD, Vol. 31, No. 10, 2012, pp. 1522-1535.
`
`6. S. Melamed, T. Thorolfsson, R.T. Harris, S. Priyadarshi, P.D. Franzon, M.B. Steer,
`W.R. Davis, “Junction level thermal analysis of 3-D integrated circuits using high
`definition power blurring,” in IEEE Trans CAD, Vol. 31, No. 5, 2012, pp. 676-689.
`
`
`7. M.B. Yelten, T. Zhu, S. Koziel, P.D. Franzon, M.B. Steer, “Demystifying Surrogate
`Modeling for Circuits and Systems,” in IEEE Circuits and Systems Magazine, VOl.
`12, No. 1, 2012, pp. 45-63.
`
`
`8. S. Priyadarshi, T.R. Harris, S. Melamed, C. Otero, N.M. Kriplani, C.E. Christoffersen,
`R. Manohar, S.R. Dooley, W.R.Davis, P.D. Franzon, M.B. Steer, “Dynamic
`Electrothermal Simulation of Three-Dimensional Circuits Using Standard Cell
`
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`
`Macromodels,” in IET Circuits, Devices, and Systems, Vol. 6., No. 1., 2012, pp. 35-
`44.
`
`
`9. M.B. Yelten, P.D. Franzon, M.B. Steer, “Analog Negative Bias Temperature
`Instability Monitoring Circuit,” in IEEE Trans. Devices and Materials Reliability, Vol.
`12, No. 1, 2012, pp. 177-179.
`
`10. P. Chakraborti, H. Topraki, P. Yand, N. DiSpigna, P. Franzon, T. Ghosh, “A compact
`dielectric elastomer tubular actuator for refereshable Braille displays,” in Sensors and
`Actuators A:Physical, V> 179, p. 151-157, June 2012.
`
`11. T.R. Harris, S. Priyadarshi, S. Melamed, C. Ortega, R. Manohar, S.R. Dooley, N.M.
`Kriplani, W.R. Davis, P.D. Franzon, M.B. Steer, “A Transient Electrothermal Analysis
`of Three-Dimensional Integrated Circuits,” in IEEE Trans CPMT, Vol. P, Issue 99,
`2012, pp. 1.
`
`12. T. Zhu, M.B. Steer, and P.D. Franzon, “Accurate and Scalable IO Buffer Macromodle
`Based on Surrogate Modeling,” in IEEE Transactions CPMT, VOl. 1, Issue 8, 2011,
`pp. 1240-1249.
`
`13. M.B. Yelten, P.D. Franzon and M.B. Steer, “Surrogate Model-Based Analysis of
`Analog Circuits – Part I. Variability Analysis,” in IEEE Trans. Device and Materials
`Reliability, Vol. PP, Issue 99, 2011.
`
`
`14. M.B. Yelten, P.D. Franzon and M.B. Steer, “Surrogate Model-Based Analysis of
`Analog Circuits – Part II. Reliability Analysis,” in IEEE Trans. Device and Materials
`Reliability, Vol. PP, Issue 99, 2011.
`
`15. D. Schinke, N. DiSpigna, M. Shiveshwarkar, and P. Franzon, “Computing With Novel
`Floating Gate Devices”, in IEEE Computer, Vol. 44, No. 2, 2011, pp. 29-36.
`
`16. D. Schinke, S. Priyadarshi, W.S. Pitts, N.H. DiSpigna, P.D. Franzon, “SPICE-
`compatible Physical Model of Nanocrystal Floating Gate Devices for Circuit
`Simulation,” in IET Circuits, Devices and Systems, Vol. 5, No. 6, 2011, pp. 477-483.
`
`17. D. Schinke, N. DiSpigna, M. Shiveshwarkar, P.Franzon, “Computing with Novel
`Floating Gate Devices,” in Computer, Vol. 44, No. 2, 2011, pp. 29-36.
`
`18. T. Thorolffson, N. Moezzi-Madani, P.D. Franzon, “Reconfigurable five-layer three-
`dimensional integrated memory on logic synthetic aperture radar processor, in IET
`Computers and Digital Techniques, Vol. 5, Issue 3, 2011, pp. 198-204.
`
`19. L. Zhang, J.M. Wilson, R. Bashirullah, L. Luo, J. Xu, P. Franzon, “A 32-Gb/s on-chip
`Bus with Driver Pre-Emphasis Signaling,” in Trans. VLSI, Vol. 17, No. 9, Sept. 2010,
`pp. 1267-74.
`
`
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`
`20. H. Tao, D. Corley, M. Lu, N. DiSpigna, D. Nackashi, P. Franzon, J. Tour,
`“Controllable Molecular Modulation of Conductivity in Silicon Based Devices,” in
`Journal of the American Chemical Society, 131(29), 2009, pp. 10023-30.
`
`
`21. W. Davis, E. Oh, A. Sule, T. Thorolfsson, and P.D. Franzon, “Application Exploration
`for 3-D Integrated Circuis: TCAM, FIFO and FFT Case Studies,” in IEEE Trans. On
`VLSI, Vol. 17, No. 4, April 2009, pp. 496-506.
`
`
`22. A. Varma, M.B. Steer, and P.D. Franzon, “Improving Behavioral IO Buffer Modeling
`Based on IBIS,” in IEEE Trans. Adv. Pack., VOl. 31, No. 4, Nov. 2008, pp. 711-721.
`
`
`23. K. Cha