IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`12/497,652
`
`Application
`Number:
`Filing or 371 (c)
`07-04-2009
`Date,
`Application
`Type:
`Examiner
`Name:
`Group Art Unit: 2896
`
`Utility
`
`JOY, JEREMY J
`
`Confirmation
`Number:
`
`6944
`
`Attorney Docket 0907043DSA3L.US
`Number:
`
`Class / Subclass: 257/773
`
`First Named
`Inventor:
`
`Glenn J. Leedy , Parkland,
`FL (US)
`- 1 -1i~
`
`iii ............... .......... ...............
`
`..............
`
`Customer
`.Number:
`
`Status:
`
`Final Rejection Mailed
`
`Status Date:
`
`02-17-2012
`
`Location:
`
`ELECTRONIC
`
`US 2010-0171224 Al
`
`i07-08-2010
`
`Location Date: -
`Earliest
`Publication
`No:
`Earliest
`Publication
`Date:
`Patent
`Number:
`Issue Date of
`Patent:
`
`Title of Invention:
`
`Three dimensional structure memory
`
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`RESPONSE
`
`Responsive to the prior Office Action, please amend this application as follows.
`
`Elm Exhibit 2167
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`
`
`12/497,652
`
`Application
`Number:
`Filing or 371 (c)
`07-04-2009
`Date,
`Application
`Type:
`Examiner
`Name:
`Group Art Unit: 2896
`
`Utility
`
`JOY, JEREMY J
`
`Confirmation
`Number:
`
`6944
`
`Attorney Docket 0907043DSA3L.US
`Number:
`
`Class / Subclass: 257/773
`
`First Named
`Inventor:
`
`Glenn J. Leedy , Parkland,
`FL (US)
`- 1 -1i~
`
`iii ............... .......... ...............
`
`..............
`
`Customer
`.Number:
`
`Status:
`
`Final Rejection Mailed
`
`Status Date:
`
`02-17-2012
`
`Location:
`
`ELECTRONIC
`
`US 2010-0171224 Al
`
`i07-08-2010
`
`Location Date: -
`Earliest
`Publication
`No:
`Earliest
`Publication
`Date:
`Patent
`Number:
`Issue Date of
`Patent:
`
`Title of Invention:
`
`Three dimensional structure memory
`
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`RESPONSE
`
`Responsive to the prior Office Action, please amend this application as follows.
`
`Elm Exhibit 2167
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`
`
`IN THE CLAIMS
`
`1. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate, eomprL isiga first surface having
`
`interconnect contacts, and a second surface oposite the first surface, and a second circuit
`
`layer comprising a second substrate eemprifing-and a first surface and a second surface
`
`each having interconnect contacts, wherein the second surface is opposite the first
`
`surface;
`
`wherein at least one of the first and second circuit layers is substantially flexible,
`
`and the substrate thereof is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface, and wherein the at least one of the first
`
`and second WbStFMOSircuit layers comprisesing at least one vertical interconnect
`
`extending from a the first surface thereof to at the eppeiecond surface thereof and
`
`formed within a via etched into the semiconductor substrate to accommodate the vertical
`
`interconnect, the vertical interconnect comprising a conductive center portion and an
`
`insulating portion surrounding the conductive center portion and adjoining sides of the
`
`via, wherein sa:at last
`o ne. .
`
`the first.
`
`seondsubstrates is fermed from a
`.and.
`
`Semficonductor Wafer or porticni thereot;.
`
`a third circuit layer comprising a third substrate eempri-eig- and a first surface
`
`having interconnect contacts; and
`
`a plurality of bonds forming signal paths between the interconnect contacts of the
`
`surfaces of the second SibSt atecircuit layer and the interconnect contacts of the first
`
`surfaces of the first and third substatescircuit layers.
`
`Elm Exhibit 2167, Page 2
`
`
`
`Whrin at least one of the substrates is thinned to provide at least onle thinnd
`
`substrate, and wherein a seecond surface oppoSitO the firt SUfrfae of said at least one
`
`thinned substrate is a polished surface.
`
`2. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate and having topside and bottomside
`
`surfaces, wherein the topside surface of the first s.bsti-ate-circuit layer has interconnect
`
`contacts, and a second circuit layer comprising a second substrate and having topside and
`
`bottomside surfaces, wherein the topside and the bottomside surfaces of the second
`
`WbStffite ircuit layer have interconnect contacts;
`
`wherein at least one of the first and second circuit layers is substantially flexible
`
`and the substrate thereof is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface, and wherein the at least one of the first
`
`and second s',bstrates circuit layers comprissi*ng at least one vertical interconnect
`
`extending from a-fi-sthe topside surface thereof to an epp
`
`ethe bottomside surface
`
`thereof and formed within a via etched into the semiconductor substrate to accommodate
`
`the vertical interconnect, the vertical interconnect comprising a conductive center portion
`
`and an insulating portion surrounding the conductive center portion and adioining sides
`
`of the via, wherein said at least one
`
`,fthe first nd second SUbstratas s formed. A
`froA
`
`semficonduc5tr wafer Or portion thereOff,
`
`a third circuit layer comprising athird substrate having topside and bottomside
`
`surfaces, wherein the bottomside surface of the third St bState
`
`ircuit layer has
`
`interconnect contacts;
`
`/
`
`Elm Exhibit 2167, Page 3
`
`
`
`a plurality of bonds between the bottomside surface of the second SubStatecircuit
`
`lyer and the topside surface of the first S*b tateircuit layer;
`
`conductive paths formed between the interconnect contacts of the topside of the
`
`first substweircuit layer and the interconnect contacts of the bottomside of the second
`
`S*bSFtecircuit layer, and conductive paths formed between the interconnect contacts of
`
`the topside of the second *ustatecircuit layer and the interconnect contacts of the
`
`bottomside of the third S*bSt.ate ircuit layer, the conductive paths providing electrical
`
`connections between at least two of the first, second and third sbst
`
`ircuit laers
`
`w.herein at least onc 3f the the substrates is thinned to provide at least one thind
`
`substrate, and wherein the boftcmside surface of said at least ono thinnled-substrata s
`
`polished-SUFfare.
`
`3. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate and having a first and a second
`
`surface, wherein said second surface is opposite to said first surface, and a second circuit
`
`layer comprising a second substrate and having a first and a second surface, wherein said
`
`second surface is opposite to said first surface;
`
`wherein at least one of the first and second circuit layers is substantially flexible
`
`and the substrate thereof is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface, and wherein the at least one of the first
`
`and second SUbStFatescircuit layers comprisesig at least one vertical interconnect
`
`extending from a-the first surface thereof to an-Eppesitethe second surface thereof and
`
`Elm Exhibit 2167, Page 4
`
`
`
`formed within a via etched into the semiconductor substrate to accommodate the vertical
`
`interconnect, the vertical interconnect comprising a conductive center portion and an
`
`insulating portion surrounding the conductive center portion and adioining sides of the
`
`via, wherein said at least ene 3f the first and seeend substrates is for-med from a
`
`OEImodco Wafer Or pertien thereot
`
`a third circuit layer comprising a third substrate and having a first and a second
`
`surface, wherein said second surface is opposite to said first surface;
`
`a plurality of bondformed contacts between the first surface of the first substate
`
`circuit layer and the first surface of the second substrte-circuit layer and between the
`
`second surface of the second subStFMO-ircuit layer and the first surface of the third
`
`subtratecircuit layer; wherein at least two of said contacts are selected from a group
`
`consisting of: a conductive signal path; a conductive contact; and a non-conductive
`
`contact.
`
`w'herein at least cne of the substrates is thinned to prcevide at least one thinned
`
`4. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate and having a first and a second
`
`surface, wherein said second surface is opposite to said first surface, and a second circuit
`
`layer comprising a second substrate and having a first and a second surface, wherein said
`
`second surface is opposite to said first surface;
`
`wherein at least one of the first and second circuit layers is substantially flexible,
`
`and the substrate thereof is a substantially flexible semiconductor substrate made from a
`
`Elm Exhibit 2167, Page 5
`
`
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface, and wherein the at least one of the first
`
`and second subStrateS-circuit layers comprises ig at least one vertical interconnect
`
`extending from a-the first surface thereof to an eppetthe second surface thereof and
`
`formed within a via etched into the semiconductor substrate to accommodate the vertical
`
`interconnect, the vertical interconnect comprising a conductive center portion and an
`
`insulating portion surrounding the conductive center portion and adjoining sides of the
`
`via, whefein said at least one ef the first and seeond subStraitoS is formed from a
`
`semieendiwteir ,a,,
`
`POWO^ i.heFeef
`
`a third circuit layer comprising a third substrate and having a first and a second
`
`surface, wherein said second surface is opposite to said first surface;
`
`a plurality of bondformed contacts between the second surface of the first
`
`sbstate ircuit layer and the first surface of the second substrFat, circuit layer and
`
`between the second surface of the second subState
`
`ircuit layer and the first surface of
`
`the third substratecircuit layer; wherein at least two of said contacts are selected from a
`
`group consisting of: a conductive signal path; a conductive contact; and a non-conductive
`
`contact;
`
`W.hOr~in at least one of the substrates is thinned to proVide at least one thinned
`
`Sutrtate, and wherein the second surfacse of said at least eno thinned substrate is a
`
`polished SUFfae
`
`wherein the at least one of the first and second circuit layers comprises dielectric
`
`material having stress of 5 x 108 dynes/cm 2 or less, and wherein the at least one of the
`
`first and second circuit layers comprises integrated circuitry defining an integrated circuit
`
`6,
`
`Elm Exhibit 2167, Page 6
`
`
`
`die having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`5. (Currently amended) The integrated circuit structure of elaim 1-,!jaim 37 wherein the
`
`at least one of the first and second substrates is at least t+o .f.the
`
`fcllowig:. less than
`
`about 10 microns in thickness; substantially fl
`
`ible; .GFpriSS a dielec rc. layff Wiha
`
`stross of about 5 x 104 d~yfiesema~e~es
`
`6. (Currently amended) The integrated circuit structure of el.a.m 2-,clair m39 wherein the
`
`at least one of the first and second substrates is at least twc ofthe fellewing: less than
`
`about 10 microns in thickness; substantially flexible; cmris
`S a dielectr.c layer wit"
`O
`
`stres o abot 5x 10 OdyfleShmaef ls. 1.
`
`7. (Currently amended) The integrated circuit structure of elaim, 3-, claim 41, wherein the
`
`at least one of the first and second substrates is at least two o
`
`f the fllo.wifg less than
`
`about 10 microns in thickness; substantially flexible; comprises a dieletrc layer with a
`
`.
`sto
`
`fc
`.
`
`x-les.
`,× lOut
`
`8. (Previously presented) The integrated circuit structure of claim 4, wherein the at least
`
`one of the first and second substrates is at least two of the following: less than about 10
`
`microns in thickness; substantially fleible; compr:ises a diele.tri layer With a SteSS o
`
`eyh-ew-
`
`5 1- eeml'eG. s
`
`Elm Exhibit 2167, Page 7
`
`
`
`9. (Currently amended) The integrated circuit structure of elaim !-,claim 37, wherein, the
`
`polished surface is a CMP polished surface.
`
`10. (Currently amended) The integrated circuit structure of eaim--2-lai 39., wherein
`
`the polished surface is a CMP polished surface.
`
`11. (Currently amended) The integrated circuit structure of elam 2, claim 41, wherein
`
`the polished surface is a CMP polished surface.
`
`12. (Previously presented) The integrated circuit structure of claim 4, wherein the
`
`polished surface is a CMP polished surface.
`
`13-16. (Canceled)
`
`17. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate rempiisiWg-and a first.surface
`
`having interconnect contacts, and a second circuit layer comprising a second substrate
`
`eempr4~i.tg-and a first surface and a second surface each having interconnect contacts,
`
`wherein the second surface is opposite the first surface;
`
`a third circuit layer comprising a third substrate eempriskg-and a first surface
`
`having interconnect contacts;
`
`Elm Exhibit 2167, Page 8
`
`
`
`a plurality of bonds forming signal paths between the interconnect contacts of the
`
`surfaces of the second sUbstte-circuit layer and the interconnect contacts of the first
`
`surfaces of the first and third SUbS-Fatescircuit layers;
`
`wherein:
`
`at least one of the first and second circuit layers is substantially flexible, and the
`
`substrate thereof is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface. at least one of the SUbStrates is thinned
`
`tc prcvidc at least one thinned substrate, wherein a second surfase opposite the firSt
`
`SUrfa6e of said at least one thinined substrate is a polished sur-faee, -Wherfein Said at least
`
`one of the SUbstrateS iS formled from a semiconductor ' &afeF Or portion thercof, and
`
`the at least one of the first and second .. b.ates. ircuit layers is at least one of the
`
`following: less than about 10 microns in thickness; substantially flexible; comprises a
`
`dielectric layer with a stress of about 5 x 108 dynes/cm2 or less.
`
`.18. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate and having topside and bottomside
`
`surfaces, wherein the topside surface of the first substrate circuit layer has interconnect
`
`contacts, and a second circuit layer comprising a second substrate and having topside and
`
`bottomside surfaces, wherein the topside and the bottomside surfaces of the second
`
`sbS.ate ircuit layer have interconnect contacts;
`
`Elm Exhibit 2167, Page 9
`
`
`
`a third circuit layer comprising a third substrate and having topside and
`
`bottomside surfaces, wherein the bottomside surface of the third substFateircuit layer
`
`has interconnect contacts;
`
`a plurality of bonds between the bottomside surface of the second s.bsti.te -rcuit
`
`layer and the topside surface of the first su"'-at circuit layer;
`
`conductive paths formed between the interconnect contacts of the topside of the
`
`first substrate circuit layer and the interconnect contacts of the bottomside of the second
`
`substratecircuit layer, and conductive paths formed between the interconnect contacts of
`
`the topside of the second substratecircuit layer and the interconnect contacts of the
`
`bottomside of the third substFatecircuit layer, the conductive paths providing electrical
`
`connections between at least two of the first, second and third si-bstratescircuit layers;
`
`wherein:
`
`at least one of the first and second circuit layers is substantially flexible, and the
`
`substrate thereof is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface at least one the 'fthe
`
`substr-ates is
`
`thinned to ProN'*de at least ene thinned substrae, Wherein said at least one of the
`
`sbStrat s is formed from a semicondutcr wafer o portion thereof;
`
`the bonoemside sur-face of said at least one thinned substrae is a polished surae
`
`and
`
`the at least one of the first and second substrates is at least one of the following:
`
`less than about 10 microns in thickness; u't'" l flexible; comprises a dielectric
`
`layer with a stress of about 5 x 108 dynes/cm2 or less.
`
`Elm Exhibit 2167, Page 10
`
`
`
`19. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate and having a first and a second
`
`surface, wherein said second surface is opposite to said first surface, and a second circuit
`
`layer comprising a second substrate and having a first and a second surface, wherein said
`
`second surface is opposite to said first surface;
`
`a third circuit layer comprising a third substrate having a first and a second
`
`surface, wherein said second.surface is opposite to said first surface;
`
`a plurality of bondformed contacts between the first surface of the first suabstrate
`
`circuit layer and the first surface of the second substra~te -ircuit layer and between the
`
`second surface of the second substr-ate-circuit layer and the first surface of the third
`
`substfateircuit layer; wherein at least two of said contacts are selected from a group
`
`consisting of: a conductive signal path; a conductive contact; and a non-conductive
`
`contact;
`
`wherein:
`
`at least one of the first and second circuit layers is substantially flexible, and the
`
`substrate thereof is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface; at least one f the substratez i thnned
`
`to pr-vide at least ene thinned substrato, wherein said at least
`
`fne of the substrates is
`
`formed from a sem iendutr
`,afeF
`
`o pin therof; and
`
`Elm Exhibit 2167, Page 11
`
`
`
`the at least one of the first and second substratesircuit layers is at least one of the
`
`following: less than about 10 microns in thickness; substantially flexible; comprises a
`
`dielectric layer with a stress of about 5 x 108 dynes/cm 2 or less.
`
`20. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate and having a first and a second
`
`surface, wherein said second surface is opposite to said first surface, and a second circuit
`
`layer comprising a Second substrate and having a first and a second surface, wherein said
`
`second surface is opposite to said first surface;
`
`a third circuit layer comprising a third substrate and having a first and a second
`
`surface, wherein said second surface is opposite to said first surface;
`
`a plurality of bondformed contacts between the second surface of the first
`
`subtraec ircuit layer and the first surface of the second st.btrftec ircuit layer and
`
`between the second surface of the second SUb tiateircuit layer and the first surface of
`
`the third So"...ate ircuit layer; wherein at least two of said contacts are selected from a
`
`group consisting of: a conductive signal path; a conductive contact; and a non-conductive
`
`contact;
`
`whe~effl
`
`at least one .f the substrates is thinned to provide at least one hinned su1,bStrate,
`
`--h---i- Said at cast ne ofthe substrates is form.. ed from a semionduct
`
`c Wafer o-
`r
`
`
`
`peftie thefeeP;
`
`t e-eer.On" rfacc of said at least one hinned substrate is a po lished SUrface; and
`
`Elm Exhibit 2167, Page 12
`
`
`
`at least onle Ofi e ist and seecnd suastrates is at least efnc otthe
`
`|
`
`|
`
`~A~l
`
`I.
`
`followinig: less then about 10 mfiffrn
`
`in9 thicknEOSS; SUbztantfially flexible; comprises a
`
`dieleetO
`
`layer with a stress of about 5 Y, 10
`
`dynes/em-e 8ess wherein the at least one of
`--
`
`the first and second circuit layers comprises dielectric material having stress of 5 x 10s
`
`dynes/cm 2 or less, and wherein the at least one of the first and second circuit layers
`
`comprises integrated circuitry defining an integrated circuit die having an area, wherein
`
`the substrate of the at least one of the first and second circuit layers extends throughout at
`
`least a substantial portion of the area of the integrated circuit die.
`
`21. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate
`
`.
`
`. . _ -and a first surface
`
`having interconnect contacts, and a second circuit layer comprising a second substrate
`eempi stg and a first surface having interconnect contacts;
`
`wherein at least one of the first and second circuit layers is substantially flexible,
`
`and the substrate thereof is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting and
`
`subsequently polished to form a polished surface, and wherein the at least one of the first
`
`and second s*bst ates circuit layers comprisesig at least one vertical interconnect
`
`extending from a first surface thereof to an opposite surface thereof and formed within a
`
`via etched into the semiconductor substrate to accommodate the vertical interconnect, the
`
`vertical interconnect comprising a conductive center portion and an insulating portion
`
`surrounding the conductive center portion and adoining sides of the via; and
`
`Elm Exhibit 2167, Page 13
`
`
`
`a plurality of bonds forming signal paths between the interconnect contacts of the
`
`first surface of the second subSt~ae-ircuit layer and the interconnect contacts of the first
`
`surface of the first subStatecircuit layert
`
`at least ane
`
`the substrates is thinned to po
`
`'ide 8t least ne thinned substrate,
`
`Wherin said At least onAecf the substrates is formed from a semicon9ductor Wafer or:
`
`peotief thereOfA and
`
`a sersond surfase opposite the first surface of said at least once thinned substrate is
`
`a pelished suffaee.
`
`22. (Currently amended) The integrated circuit of slair 1-l,jaim 49, wherein the at least
`
`one of the first and second substrates is at least one f.the fllowing..: ess than about 10
`
`microns in thickness; substantially fle.ible; comprises a dieletric layer -with a stress oe
`°a'"d5 y !eskmae/m-4ss
`
`23.-25. (Canceled)
`
`26. (Currently amended) The integrated circuit structure of Mlaim 1-,claim 37, wherein at
`
`least two of the following: the at least one of the first and second substrates is at least-one
`
`of
`
`
`
`..he e
`
`.lewig
`.less than about 10 microns in thickness; substantially flexible;
`
`compriSes a dieleatr . layer with a stress of about 5 x 10 dynes
`
`e-r-less; the polished
`
`surface is a CMP polished surface; at least one of the S..Stats is substantially flexible;
`
`the second surface of said at least one thinned substrate is a polished surface, ausing said
`
`14
`
`Elm Exhibit 2167, Page 14
`
`
`
`at least one thinned substrate to be substantially flexible; at least one of the subtates
`
`circuit layers comprises ECC circuitry; at least one of the substFMes-circuit layers
`
`comprises memory refresh circuitry; at least one of the substr-eescircuit layers comprises
`
`test circuitry for testing circuitry on a different substiateircuit layer; at-leatne ofthe
`
`.ubStrates c
`
`o
`
`redundant Vertiaal intercon... tion.. at least one of the subStiteS
`
`circuit layers comprises reconfiguration circuitry.
`
`27.-34. (Canceled)
`
`35. (Currently amended) An integrated circuit structure comprising:
`
`a first circuit layer comprising a first substrate eempffisiRg-and a first surface
`
`having interconnect contacts;
`
`a second circuit layer comprising a thinned and flexible second substrate
`
`eeRmprfng anda first surface and a second surface each having interconnect contacts,
`
`wherein the first and second surfaces of the second substrate are opposite each other.
`
`wherein the second circuit layers is substantially flexible, and the substrate thereof
`
`is a substantially flexible semiconductor substrate made from a semiconductor wafer
`
`thinned by at least one of abrasion, etching and parting and subsequently polished to form
`
`a polished surface, and wherein the the second substrate circuit layer further
`
`comprisesig vertical interconnects extending through the semindue -
`
`ayer from a the
`
`first surface thereof to the second surface thereof and extending through the
`
`semiconductor substrate, each vertical interconnect being formed within a via etched into
`
`the semiconductor substrate to accommodate the vertical interconnect and comprising a
`
`Elm Exhibit 2167, Page 15
`
`
`
`conductive center. portion and a low stress dielectric insulating portion surrounding the
`
`conductive center portion and adjoining walls of the via, afKI-the dielectric insulating
`
`portion having a stress of about 5 x 108 dynes/cm 2 or less;
`
`a third circuit layer comprising a third substrate eempFisng-and a first surface
`
`having interconnect contacts;
`
`a first plurality of bonds between the interconnect contacts of the first surface of
`
`the second StIb.trate circuit layer and the interconnect contacts of the first surface of the
`
`first s "StFate
`
`ircuit layer and forming electrical connections there between; and
`
`a second plurality of bonds between the interconnect contacts of the second
`
`surface of the second substIe-,ircuit layer and the interconnect contacts of the first
`
`surface of the third subSt aW
`
`ircuit layer and forming electrical connections there
`
`between.
`
`36. (New) The integrated circuit structure of claim I, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm 2
`
`or less.
`
`37. (New) The integrated circuit structure of claim 36, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`Elm Exhibit 2167, Page 16
`
`
`
`38. (New) The integrated circuit structure of claim 2, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm2
`
`or less.
`
`39. (New) The integrated circuit structure of claim 38, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`40. (New) The integrated circuit structure of claim 3, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm 2
`
`orless.
`
`41. (New) The integrated circuit structure of claim 40, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`42. (New) The integrated circuit structure of claim 17, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm 2
`
`or less.
`
`Elm Exhibit 2167, Page 17
`
`
`
`43. (New) The integrated circuit structure of claim 42, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`44. (New) The integrated circuit structure of claim 18, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm 2
`
`or less.
`
`45. (New) The integrated circuit structure of claim 44, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`46. (New) The integrated circuit structure of claim 19, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm 2
`
`or less.
`
`47. (New) The integrated circuit structure of claim 46, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`Elm Exhibit 2167, Page 18
`
`
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`48. (New) The integrated circuit structure of claim 21, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm 2
`
`or less.
`
`49. (New) The integrated circuit structure of claim 48, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`50. (New) The integrated circuit structure of claim 35, wherein the at least one of the first
`and second circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm 2
`
`or less.
`
`51. (New) The integrated circuit structure of claim 50, wherein the at least one of the first
`
`and second circuit layers comprises integrated circuitry defining an integrated circuit die
`
`having an area, wherein the substrate of the at least one of the first and second circuit
`
`layers extends throughout at least a substantial portion of the area of the integrated circuit
`
`die.
`
`1 1 C19
`
`Elm Exhibit 2167, Page 19
`
`
`
`52. (New) The integrated circuit structure of claim 37, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`53. (New) The integrated circuit structure of claim 39, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`54. (New) The integrated circuit structure of claim 41, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`55. (New) The integrated circuit structure of claim 4, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`56. (New) The integrated circuit structure of claim 43, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`Elm Exhibit 2167, Page 20
`
`
`
`57. (New) The integrated circuit structure of claim 45, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`58. (New) The integrated circuit structure of claim 47, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`59. (New) The integrated circuit structure of claim 20, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`60. (New) The integrated circuit structure of claim 49, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric..
`
`61. (New) The integrated circuit structure of claim 51, wherein areas that are bonded
`
`together define a bond layer, the bond layer being comprised predominantly of metal, or
`
`predominantly of metal and silicon-based dielectric.
`
`62. (New) The integrated circuit structure of claim 37, comprising a dense array 4 x 4 or
`
`greater array of vertical interconnects, wherein adjacent vertical interconnects are
`
`positioned at a pitch of 1 micron or less.
`
`Elm Exhibit 2167, Page 21
`
`
`
`63. (New) The integrated circuit structure of claim 62, comprising redundant vertical
`
`interconnects.
`
`64. (New) The integrated circuit structure of claim 39, comprising a dense array 4 x 4 or
`
`greater array of vertical interconnects, wherein adjacent vertical interconnects are
`
`positioned at a pitch of I micron or less.
`
`65. (New) The integrated circuit structure of claim 64, comprising redundant vertical
`
`interconnects.
`
`66. (New) The integrated circuit structure of claim 41, comprising a dense array 4 x 4 or
`
`greater array of vertical interconnects, wherein adjacent vertical interconnects are
`
`positioned at a pitch of I micron or less.
`
`67. (New) The integrated circuit structure of claim 66, comprising redundant vertical
`
`interconnects.
`
`68. (Nev) The inte
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