' UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`12/497,652
`
`FILING DATE
`
`07/04/2009
`
`FIRST NAMED INVENTOR
`
`ATITORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`Glenn J. Leedy
`
`0907043DSA3L.US
`
`6944
`
`05/20/2014
`
`30232
`7590
`USEFUL ARTS IP
`MICHAEL J. URE
`10518 PHIL PLACE
`CUPERTINO, CA 95014
`
`EXAM ER
`
`JOY, JEREMY J
`
`ART UNIT
`
`PAPER NUMBER
`
`2896
`
`MAIL DATE
`
`05/20/2014
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`Elm Exhibit 2168
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`

`
`Office Action Summary
`
`Applicant(s)
`LEEDY, GLENN J.
`Art Unit
`2896
`
`Application No.
`12/497,652
`Examiner
`AIA (First Inventor to File)
`Statu
`JEREMY JOY
`-1No
`-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address -
`Period for Reply
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTHS FROM THE MAILING DATE OF
`THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`In no event, however, may a reply be timely filed
`
`Status
`1)Z Responsive to communication(s) filed on 09/26/2013.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`This action is FINAL.
`2a)[
`2b)El This action is non-final.
`3)F] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
`_
`4)- Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11,453 O.G. 213.
`Disposition of Claims*
`5)[D Claim(s) 1-12,17-22,26 and 35-99 is/are pending in the application.
`5a) Of the above claim(s) _
`is/are withdrawn from consideration.
`6)1 Claim(s) _
`is/are allowed.
`7)Z Claim(s) 1-12, 17-22, 26, and35-99 is/are rejected.
`8)11 Claim(s) _
`is/are objected to.
`9)"- Claim(s) _
`are subject to restriction and/or election requirement.
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init events/pphiindex.sp or send an inquiry to PPHfeedback~uspto.gov.
`Application Papers
`10)EI The specification is objected to by the Examiner.
`11)EJ The drawing(s) filed on _
`is/are: a)EI accepted or b)LI objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`Priority under 35 U.S.C. § 119
`12)11 Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 11 9(a)-(d) or (f).
`Certified copies:
`a)ElI All
`b)El Some** c)E None of the:
`1 .[
`Certified copies of the priority documents have been received.
`2.E] Certified copies of the priority documents have been received in Application No.
`3.[] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau ,(PCT Rule 17.2(a)).
`See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`1) [ Notice of References Cited (PTO-892)
`
`2) [
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date 07/17/2013, 10/18/2013, 10/18/2013, 10/18/2013.
`U.S. Patent and Trademark Office
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`3) El Interview Summary (PTO-413)
`Paper No(s)/Mail Date.
`
`Part of Paper No./Mail Date 20140515
`
`Elm Exhibit 2168, Page 2
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 2
`
`The present application is being examined under the pre-AIA first to invent
`
`provisions.
`
`DETAILED ACTION
`
`Response to Arguments
`
`1.
`
`Applicant's arguments, filed on 09/26/2013, with respect to the rejections of the
`
`claims have been fully considered and are persuasive. Therefore, the rejection has
`
`been withdrawn. However, upon further consideration, a new ground(s) of rejection is
`
`made below.
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`2.
`
`Claims 1-12, 17-22, 26, and 35-89 are rejected under 35 U.S.C. 103(a) as being
`
`unpatentable over Bertin et aL (U.S. Patent No. 5,202,754, from hereinafter "Bertin") in
`
`view of Kato et aL (U.S. Patent No. 4.939.568, from hereinafter "Kato") in view of Leedy
`
`(U.S. Patent No. 5,354,695).
`
`Regarding Claim 1, Bertin teaches a first circuit layer comprising a first
`
`substrate, a first surface having interconnect contacts, and a second surface opposite
`
`the first surface (Fig. 3, circuit layer 50, substrate 52, first/second surfaces 56/58 (not
`
`necessarily respectively), interconnect contacts 68/82) and a second circuit layer
`
`Elm Exhibit 2168, Page 3
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 3
`
`comprising a second substrate and a first surface and a second surface each having
`
`interconnect contacts, wherein the second surface is opposite the first surface (Fig. 3,
`
`circuit layer 50, substrate 52, first/second surfaces 56/58 (not necessarily respectively);
`
`interconnect contacts 68/82); wherein at least one of the first and second circuit layers
`
`comprises a substrate thereof that is a substantially flexible semiconductor substrate
`
`made from a semiconductor wafer thinned by at least one of abrasion, etching and
`
`parting (Fig. 2, y to y' in which substrate is thinned to 5-201pm and thinning specifically
`
`shown in Fig. 3f-3g), and wherein the at least one of the first and second circuit layers
`
`comprising at least one vertical interconnect extending from a the first surface thereof to
`
`an the-second surface thereof and formed within a via etched into the semiconductor
`
`substrate to accommodate the vertical interconnect, the vertical interconnect comprising
`
`a conductive center portion and an insulating portion surrounding the conductive center
`
`portion and adjoining sides of the via (Fig 3, vertical interconnects 66, insulated by
`
`silicon oxide), a third circuit layer comprising a third substrate and a first surface having
`
`interconnect contacts; and a plurality of bonds forming signal paths between the
`
`interconnect contacts of the surfaces of the second circuit layer and the interconnect
`
`contacts of the first surfaces of the first and third circuit layers (Fig. 3, third substrate not
`
`shown but the steps repeat as described; bonds are shown specifically in Fig. 3i
`
`between interconnect contacts 68/82; Col. 3-5).
`
`Bertin fails to specifically teach the at least one of the first and second circuit
`
`layers is subsequently polished to form a polished surface after thinning.
`
`Kato teaches using CMP to polish a surface to expose signal paths on a second
`
`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
`
`Elm Exhibit 2168, Page 4
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 4
`
`In view of the teachings of Kato, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
`
`above to include the polishing the surface using CMP because CMP is a well-known
`
`method to expose contacts on a substrate as it will provide a smooth flat surface for
`
`bonding as exemplified by Kato.
`
`Bertin also fails to specifically teach wherein at least one of the first and second
`
`circuit layers is substantially flexible. In particular, since Bertin teaches forming the
`
`insulation portion of the vertical interconnects by thermal oxidation resulting in high
`
`stress insulation layer, it fails to teach flexible circuit layers (Note: the flexible circuit
`
`layer must possess a low stress dielectric in order for it to be flexible).
`
`Leedy teaches an IC circuit structure comprising substantially flexible circuit
`
`layers wherein each of the circuit layers comprise an insulating low stress dielectric that
`
`insulates electrical elements and through-substrate conductors wherein said low stress
`
`dielectric layers are formed by an alternative dielectric deposition (Fig. 3 and 8, Col. 9,
`
`lines 15-49 and Col. 16, lines 38-56).
`
`In view of the teachings of Leedy, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin to
`
`include that the insulating dielectric used in the IC structure and the circuit layers is a
`
`low stress dielectric layer (by using the formation technique of Leedy rather than Bertin)
`
`such that the circuit layers, including the flexible substrate, will then too be flexible
`
`circuit layers due to the inclusion of the low stress dielectric and the thinned
`
`semiconductor wafer because low stress dielectrics are desirable to form flexible circuit
`
`layers such that they may be able to withstand external stresses and furthermore still
`
`Elm Exhibit 2168, Page 5
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 5
`
`include a dielectric that can insulate the conductors formed therein from each other and
`
`other elements. Furthermore, as shown by Leedy, depositing the dielectric materials
`
`through the deposition process as taught results in a dielectric layers that have much
`
`lower stress as compared to the high stress films formed through oxidation. Also, Leedy
`
`teaches that these low stress dielectrics may be formed to match the coefficient of
`
`thermal expansion of the semiconductor material of the substrate which will help to
`
`minimize the extrinsic overall stress of the circuit layers. Furthermore, Leedy teaches
`
`that using the low stress dielectric provide advantages to lower the cost and complexity
`
`of circuit fabrication and will enhance the performance of the circuit operation (Col. 6,
`
`lines 22-58).
`
`Regarding Claim 2, Bertin teaches a first circuit layer comprising a first
`
`substrate and having topside and bottomside surfaces, wherein the topside surface of
`
`the first circuit layer has interconnect contacts surface (Fig. 3, circuit layer 50, substrate
`
`52, topside/bottomside surfaces 56/58 (not necessarily respectively), interconnect
`
`contacts 68/82), and a second circuit layer comprising a second substrate and having
`
`topside and bottomside surfaces, wherein the topside and the bottomside surfaces of
`
`the second circuit layer have interconnect contacts surface (Fig. 3, circuit layer 50,
`
`substrate 52, topside/bottomside surfaces 56/58 (not necessarily respectively),
`
`interconnect contacts 68/82); wherein at least one of the first and second circuit layers
`
`comprise a substantially flexible semiconductor substrate made from a semiconductor
`
`wafer thinned by at least one of abrasion, etching and parting (Fig. 2, y to y' in which
`
`substrate is thinned to 5-20pm and thinning specifically shown in Fig. 3f-3g), and
`
`wherein the at least one of the first and second circuit layers comprising at least one
`
`Elm Exhibit 2168, Page 6
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 6
`
`vertical interconnect extending from the topside surface thereof to opposite the
`
`bottomside surface thereof and formed within a via etched into the semiconductor
`
`substrate to accommodate the vertical interconnect, the vertical interconnect comprising
`
`a conductive center portion and an insulating portion surrounding the conductive center
`
`portion and adjoining sides of the via (Fig 3, vertical interconnects 66, insulated by
`
`silicon oxide), a third circuit layer comprising a third substrate having topside and
`
`bottomside surfaces, wherein the bottomside surface of the third circuit laver has
`
`interconnect contacts; a plurality of bonds between the bottomside surface of the
`
`second circuit layer and the topside surface of the first circuit layer; conductive paths
`
`formed between the interconnect contacts of the topside of the first substrate circuit
`
`layer and the interconnect contacts of the bottomside of the second circuit layer, and
`
`conductive paths formed between the interconnect contacts of the topside of the second
`
`circuit layer and the interconnect contacts of the bottomside of the third circuit layer, the
`
`conductive paths providing electrical connections between at least two of the first,
`
`second and third circuit layers (Fig. 3, third substrate not shown but the steps repeat as
`
`described; bonds and conductive paths (vias) are shown specifically in Fig. 3i between
`
`interconnect contacts 68/82 and through-substrate interconnects 66; Col. 3-5).
`
`Bertin fails to specifically teach the at least one of the first and second circuit
`
`layers is subsequently polished to form a polished surface after thinning.
`
`Kato teaches using CMP to polish a surface to expose signal paths on a second
`
`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
`
`In view of the teachings of Kato, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
`
`Elm Exhibit 2168, Page 7
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 7
`
`above to include the polishing the surface using CMP because CMP is a well-known
`
`method to expose contacts on a substrate as it will provide a smooth flat surface for
`
`bonding as exemplified by Kato.
`
`Bertin also fails to specifically teach wherein at least one of the first and second
`
`circuit layers is substantially flexible. In particular, since Bertin teaches forming the
`
`insulation portion of the vertical interconnects by thermal oxidation resulting in high
`
`stress insulation layer, it fails to teach flexible circuit layers (Note: the flexible circuit
`
`layer must possess a low stress dielectric in order for it to be flexible).
`
`Leedy teaches an IC circuit structure comprising substantially flexible circuit
`
`layers wherein each of the circuit layers comprise an insulating low stress dielectric that
`
`insulates electrical elements and through-substrate conductors wherein said low stress
`
`dielectric layers are formed by an alternative dielectric deposition (Fig. 3 and 8, Col. 9,
`
`lines 15-49 and Col. 16, lines 38-56).
`
`In view of the teachings of Leedy, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin to
`
`include that the insulating dielectric used in the IC structure and the circuit layers is a
`
`low stress dielectric layer (by using the formation technique of Leedy rather than Bertin)
`
`such that the circuit layers including the flexible substrate will then too be flexible circuit
`
`layers due to the inclusion of the low stress dielectric and the thinned semiconductor
`
`wafer because low stress dielectrics are desirable to form flexible circuit layers such that
`
`they may be able to withstand external stresses and furthermore still include a dielectric
`
`that can insulate the conductors formed therein from each other and other elements.
`
`Furthermore, as shown by Leedy, depositing the dielectric materials through the
`
`Elm Exhibit 2168, Page 8
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 8
`
`deposition process as taught results in a dielectric layers that have much lower stress
`
`as compared to the high stress films formed through oxidation. Also, Leedy teaches that
`
`these low stress dielectrics may be formed to match the coefficient of thermal expansion
`
`of the semiconductor material of the substrate which will help to minimize the extrinsic
`
`overall stress of the circuit layers. Furthermore, Leedyteaches that using the low stress
`
`dielectric provide advantages to lower the cost and complexity of circuit fabrication and
`
`will enhance the performance of the circuit operation (Col. 6, lines 22-58).
`
`Regarding Claim 3, Bertin a first circuit layer comprising a first substrate and
`
`having a first and a second surface, wherein said second surface is opposite to said first
`
`surface(Fig. 3, circuit layer 50, substrate 52, first/second surfaces 56/58 (not necessarily
`
`respectively), interconnect contacts 68/82) and a second circuit layer comprising a
`
`second substrate and a first surface and a second surface each having interconnect
`
`contacts, wherein the second surface is opposite the first surface (Fig. 3, circuit layer
`
`50, substrate 52, first/second surfaces 56/58 (not necessarily respectively); interconnect
`
`contacts 68/82); wherein at least one of the first and second circuit layers comprises a
`
`substrate thereof that is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting (Fig. 2, y
`
`to y' in which substrate is thinned to 5-20pm and thinning specifically shown in Fig. 3f-
`
`3g), and wherein the at least one of the first and second circuit layers comprising at
`
`least one vertical interconnect extending from a the first surface thereof to an the
`
`second surface thereof and formed within a via etched into the semiconductor substrate
`
`to accommodate the vertical interconnect, the vertical interconnect comprising a
`
`conductive center portion and an insulating portion surrounding the conductive center
`
`Elm Exhibit 2168, Page 9
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 9
`
`portion and adjoining sides of the via (Fig 3, vertical interconnects 66, insulated by
`
`silicon oxide); a third circuit layer comprising a third substrate and having a first and a
`
`second surface, wherein said second surface is opposite to said first surface; a plurality
`
`of bond formed contacts between the first surface of the first circuit layer and the first
`
`surface of the second circuit layer and between the second surface of the second circuit
`
`layer and the first surface of the third substrate circuit layer; wherein at least two of said
`
`contacts are selected from a group consisting of: a conductive signal path; a conductive
`
`contact; and a non-conductive contact (Fig. 3, third substrate not shown but the steps
`
`repeat as described; bonds are shown specifically in Fig. 3i between interconnect
`
`contacts 68/82; Col. 3-5).
`
`Bertin fails to specifically teach the at least one of the first and second circuit
`
`layers is subsequently polished to form a polished surface after thinning.
`
`Kato teaches using CMP to polish a surface to expose signal paths on a second
`
`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
`
`In view of the teachings of Kato, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
`
`above to include the polishing the surface using CMP because CMP is a well-known
`
`method to expose contacts on a substrate as it will provide a smooth flat surface for
`
`bonding as exemplified by Kato.
`
`Bertin also fails to specifically teach wherein at least one of the first and second
`
`circuit layers is substantially flexible. In particular, since Bertin teaches forming the
`
`insulation portion of the vertical interconnects by thermal oxidation resulting in high
`
`Elm Exhibit 2168, Page 10
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 10
`
`stress insulation layer, it fails to teach flexible circuit layers (Note: the flexible circuit
`
`layer must possess a low stress dielectric in order for it to be flexible).
`
`Leedy teaches an IC circuit structure comprising substantially flexible circuit
`
`layers wherein each of the circuit layers comprise an insulating low stress dielectric that
`
`insulates electrical elements and through-substrate conductors wherein said low stress
`
`dielectric layers are formed by an alternative dielectric deposition (Fig. 3 and 8, Col. 9,
`
`lines 15-49 and Col. 16, lines 38-56).
`
`In view of the teachings of Leedy, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin to
`
`include that the insulating dielectric used in the IC structure and the circuit layers is a
`
`low stress dielectric layer (by using the formation technique of Leedy rather than Bertin)
`
`such that the circuit layers including the flexible substrate will then too be flexible circuit
`
`layers due to the inclusion of the low stress dielectric and the thinned semiconductor
`
`wafer because low stress dielectrics are desirable to form flexible circuit layers such that
`
`they may be able to withstand external stresses and furthermore still include a dielectric
`
`that can insulate the conductors formed therein from each other and other elements.
`
`Furthermore, as shown by Leedy, depositing the dielectric materials through the
`
`deposition process as taught results in a dielectric layers that have much lower stress
`
`as compared to the high stress films formed through oxidation. Also, Leedy teaches that
`
`these low stress dielectrics may be formed to match the coefficient of thermal expansion
`
`of the semiconductor material of the substrate which will help to minimize the extrinsic
`
`overall stress of the circuit layers. Furthermore, Leedyteaches that using the low stress
`
`Elm Exhibit 2168, Page 11
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`*Page 11
`
`dielectric provide advantages to lower the cost and complexity of circuit fabrication and
`
`will enhance the performance of the circuit operation (Col. 6, lines 22-58).
`
`Regarding Claims 4, Bertin teaches a first circuit layer comprising a first
`
`substrate and having a first and a second surface, wherein said second surface is
`
`opposite to said first surface (Fig. 3, circuit layer 50, substrate 52, first/second surfaces
`
`56/58 (not necessarily respectively), interconnect contacts 68/82) and a second circuit
`
`layer comprising a second substrate and a first surface and a second surface each
`
`having interconnect contacts, wherein the second surface is opposite the first surface
`
`(Fig. 3, circuit layer 50, substrate 52, first/second surfaces 56/58 (not necessarily
`
`respectively); interconnect contacts 68/82); wherein at least one of the first and second
`
`circuit layers comprises a substrate thereof that is a substantially flexible semiconductor
`
`substrate made from a semiconductor wafer thinned by at least one of abrasion, etching
`
`and parting (Fig. 2, y to y' in which substrate is thinned to 5-20pm and thinning
`
`specifically shown in Fig. 3f-3g), and wherein the at least one of the first and second
`
`circuit layers comprising at least one vertical interconnect extending from a the first
`
`surface thereof to an the-second surface thereof and formed within a via etched into the
`
`semiconductor substrate to accommodate the vertical interconnect, the vertical
`
`interconnect comprising a conductive center portion and an insulating portion
`
`surrounding the conductive center portion and adjoining sides of the via (Fig 3, vertical
`
`interconnects 66, insulated by silicon oxide); a third circuit layer comprising a third
`
`substrate and having a first and a second surface, wherein said second surface is
`
`opposite to said first surface; a plurality of bond formed contacts between the first
`
`surface of the first circuit layer and the first surface of the second circuit layer and
`
`Elm Exhibit 2168, Page 12
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 12
`
`between the second surface of the second circuit layer and the first surface of the third
`
`substrate circuit layer; wherein at least two of said contacts are selected from a group
`
`consisting of: a conductive signal path; a conductive contact; and a non-conductive
`
`contact; wherein the at least one of the first and second circuit layers comprises
`
`integrated circuitry defining an integrated circuit die having an area, wherein the
`
`substrate of the at least one of the first and second circuit layers extends throughout at
`
`least a substantial portion of the area of the integrated circuit die. (Fig. 3, third substrate
`
`not shown but the steps repeat as described; bonds are shown specifically in Fig. 3i
`
`between interconnect contacts 68/82; Col. 3-5; vias are insulated with silicon dioxide).
`
`Bertin fails to specifically teach the at least one of the first and second circuit
`
`layers is subsequently polished to form a polished surface after thinning.
`
`Kato teaches using CMP to polish a surface to expose signal paths on a second
`
`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
`
`In view of the teachings of Kato, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
`
`above to include the polishing the surface using CMP because CMP is a well-known
`
`method to expose contacts on a substrate as it will provide a smooth flat surface for
`
`bonding as exemplified by Kato.
`
`Bertin fails to specifically teach wherein the at least one of the first and second
`
`circuit layers comprises dielectric material having stress of 5 x 108 dynes/cm2 or less
`
`and therefore fails to teach that at least one of the first and second circuit layers are
`
`substantially flexible, but however does teach using silicon oxide to insulate the metal
`
`interconnections in the integrated circuit layers (Col. 4, lines 11-40). In particular, since
`
`Elm Exhibit 2168, Page 13
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 13
`
`Bertin teaches forming the insulation portion of the vertical interconnects by thermal
`
`oxidation resulting in high stress insulation layer, it fails to teach flexible circuit layers
`
`(Note: the flexible circuit layer must possess a low stress dielectric in order for it to be
`
`flexible).
`
`Leedy teaches an IC circuit structure comprising substantially flexible circuit
`
`layers wherein each of the circuit layers comprise an insulating low stress dielectric that
`
`insulates electrical elements and through-substrate conductors wherein said low stress
`
`dielectric layers are formed by an alternative dielectric deposition and have a stress in
`
`the range as disclosed or less (Fig. 3 and 8, Col. 9, lines 15-49 and Col. 16, lines 38-
`
`56).
`
`In view of the teachings of Leedy, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin to
`
`include that the insulating dielectric used in the IC structure and the circuit layers is a
`
`low stress dielectric layer in the range as claimed or less (by using the formation
`
`technique of Leedy rather than Bertin) such that the circuit layers including the flexible
`
`substrate will then too be flexible circuit layers due to the inclusion of the low stress
`
`dielectric and the thinned semiconductor wafer because low stress dielectrics are
`
`desirable to form flexible circuit layers such that they may be able to withstand external
`
`stresses and furthermore still include a dielectric that can insulate the conductors
`
`formed therein from each other and other elements. Furthermore, as shown by Leedy,
`
`depositing the dielectric materials through the deposition process as taught results in a
`
`dielectric layers that have much lower stress as compared to the high stress films
`
`formed through oxidation. Also, Leedy teaches that these low stress dielectrics may be
`
`Elm Exhibit 2168, Page 14
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 14
`
`formed to match the coefficient of thermal expansion of the semiconductor material of
`
`the substrate which will help to minimize the extrinsic overall stress of the circuit layers.
`
`Furthermore, Leedy teaches that using the low stress dielectric provide advantages to
`
`lower the cost and complexity of circuit fabrication and will enhance the performance of
`
`the circuit operation (Col. 6, lines 22-58).
`
`Regarding Claim 5-8, Bertin teaches wherein the at least one of the first and
`
`second substrates is less than about 10 microns in thickness (Fig. 2 and Col. 3, lines 1-
`
`46).
`
`Regarding Claim 9-12, as in the combination of Bertin as modified by Kato
`
`above, Kato teaches said polished surface is caused to be a CMP polished surface (Fig.
`
`4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
`
`Regarding Claim 17, Bertin teaches a first circuit layer comprising a first
`
`substrate and having a first and a second surface, wherein said second surface is
`
`opposite to said first surface(Fig. 3, circuit layer 50, substrate 52, first/second surfaces
`
`56/58 (not necessarily respectively), interconnect contacts 68/82) and a second circuit
`
`layer comprising a second substrate and a first surface and a second surface each
`
`having interconnect contacts, wherein the second surface is opposite the first surface
`
`(Fig. 3, circuit layer 50, substrate 52, first/second surfaces 56/58 (not necessarily
`
`respectively); interconnect contacts 68/82); a third circuit layer comprising a third
`
`substrate and a first surface having interconnect contacts (Fig. 3, third substrate not
`
`shown but the steps repeat as described (Fig. 3i); circuit layer 50, substrate 52,
`
`first/second surfaces 56/58 (not necessarily respectively), interconnect contacts 68/82);
`
`a plurality of bonds forming signal paths between the interconnect contacts of the
`
`Elm Exhibit 2168, Page 15
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 15
`
`surfaces of the second circuit layer and the interconnect contacts of the first surfaces of
`
`the first and third circuit layers (bonds are shown specifically in Fig. 3i between
`
`interconnect contacts 68/82 of each circuit layer); at least one of the first and second
`
`circuit layers comprises substrate thereof that is a substantially flexible semiconductor
`
`substrate made from a semiconductor wafer thinned by at least one of abrasion, etching
`
`and parting (Fig. 2, y to y' in which substrate is thinned to 5-20pm and thinning
`
`specifically shown in Fig. 3f-3g); the at least one of the first and second circuit layers is
`
`at least one of the following: less than about 10 microns in thickness;-comprises a
`
`dielectric layer with a stress of about 5 x 108 dynes/cm2 or less (Fig. 2 and Col. 3, lines
`
`1-46) (Col. 3-5).
`
`Bertin fails to specifically teach the at least one of the first and second circuit
`
`layers is subsequently polished to form a polished surface after thinning.
`
`Kato teaches using CMP to polish a surface to expose signal paths on a second
`
`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
`
`In view of the teachings of Kato, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
`
`above to include the polishing the surface using CMP because CMP is a well-known
`
`method to expose contacts on a substrate as it will provide a smooth flat surface for
`
`bonding as exemplified by Kato.
`
`Bertin also fails to specifically teach wherein at least one of the first and second
`
`circuit layers is substantially flexible. In particular, since Bertin teaches forming the
`
`insulation portion of the vertical interconnects by thermal oxidation resulting in high
`
`Elm Exhibit 2168, Page 16
`
`

`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`Page 16
`
`stress insulation layer, it fails to teach flexible circuit layers (Note: the flexible circuit
`
`layer must possess a low stress di