TAPE AUfOMATED BONDING 425
`
`This makes simple, cost effective, and one step (gang) removal virtually
`impossible. Due to some of the inherent problems associated with tin tape,
`however, and the need for a fine pitch TAB assembly technology using gold
`tape, some companies are currently developing removal and repair processes for
`gold to gold bonds. Mechanical OLB bonds, a recent development, offer a great
`potential for rework and repair.
`
`9.4.10 Manufacturing Issues and Costs
`
`The manufacturing of TAB devices, regardless of the packaging scheme, depends
`on an industry infrastructure that provides the proper materials (TAB tape) and
`processing equipment (bonders, tooling etc.) to form a reliable and robust
`process. Historically, the capabilities of TAB equipment vendors have focused
`on low lead count devices for consumer electronic products. This focus has
`limited the application of the equipment in areas of high lead count, fme pitch
`TAB assembly, needed for multichip applications. As a result, the infrastructure
`for advanced TAB materials and assembly equipment needs further development,
`particularly in the United States. Equipment suppliers, tape manufacturers and
`contract assembly houses must cooperate
`to fill
`this
`technology gap.
`Consideration of the manufacturing processes, material choices and temperature
`exposures are issues needing attention in the successful implementation of TAB.
`This section will highlight a few issues and costs that should be given some
`attention.
`
`TAB Tape
`The major issues associated with TAB tape include consistent tape quality, the
`cost for advanced circuits and shelf life for tin tape.
`The most crucial aspect of a robust TAB process rests on the material
`consistency of the TAB tape. Dimensional requirements must be met repeatably
`and depend upon the design of the tape as well as on the material selection and
`tape processing practices. Fine pitch tapes, for example, with long, unsupported
`cantilevers can cause dimensional problems during tape processing and handling.
`Consistent plating is required to enable the ILB and OLB processes to maintain
`controlled process windows.
`The cost of the TAB leadframe influences the decision to pursue a TAB
`application and greatly depends on the design of the leadframe and the
`challenges it presents to the tape manufacturer. Tape costs range from $5.00 per
`frame to over $50.00 per frame (1992 dollars), depending on the complexity of
`the design (one metal layer tape versus multi-metal layer tape) and the volumes
`ordered.
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 451
`
`

`
`426 CIDP-TO-SUBSTRATE (FIRST LEVEL) CONNECllON TECHNOLOGY OPTIONS
`
`The shelf life of the tape is a determination factor for the low volume user.
`These users must balance the low volume versus cost versus shelf life to justify
`the use of TAB. One possible option is the use of a JIT approach to receiving
`the tape material.
`Bumping. The cost of wafer bumping can have a negative impact on the
`implementation of a TAB process, as this cost is concentrated only on the
`yielding die. As a result, large, low yielding die can bear the burden of wafer
`bumping costs totaling as much as $100 per wafer. Wafer bumping also requires
`expensive semiconductor processing equipment and cleanroom facilities.
`Many users, buying die from merchant semiconductor companies, do not
`have the option of having them bumped. This, along with cost issues, has led
`to bumping alternatives requiring less capital intensive methods, such as transfer
`bump TAB (TBT AB), gold ball bumping etc. These methods, however, may not
`have the ultra-fine pitch and reliability capabilities of wafer bumping and are,
`therefore, limited in application.
`Inner Lead Bonding. Inner lead bonding equipment costs can total anywhere
`from $200,000 to $400,000 (1992 dollars), depending on the level of automation
`and the type of bonder. As mentioned earlier, single point bond technology has
`yet to realize full automation and use of this equipment can result in slower
`production times. Automated gang bonders have limited application to larger,
`fine pitch die and require die specific tooling.
`Outer Lead Bonding. The cost of setting up an OLB process can be as
`much as $500,000 (1992 dollars), depending on the desired bonding technology
`and level of TAB complexity. Fine pitch applications require very accurate
`placement systems which contribute the bulk of the cost. Single point bonding
`systems may require the purchase of separate placement and bonding systems,
`whereas gang bonders usually have the bonder and placement functions
`integrated. Custom tooling is also a cost concern, as the TAB standards do not
`take full advantage of the density attributes of TAB.
`Package quality is an important consideration and is reflected in the choice
`of bonding technology. Critical among these considerations is metallurgy
`consistency and flatness ( for gang bonding). Flux contamination may be a
`reliability issue. Cleaning the flux is also, currently, a major environmental
`issue.
`Temperature Hierarchy. Encapsulation, test on tapelbum-in and repair are
`other steps in a TAB assembly process that should be looked at closely,
`especially from a temperature exposure perspective. Each of the TAB processes
`affect both previous and future processes. Bum-in can be detrimental to the
`solderability of tin plated tapes by causing accelerated growth in copper-tin
`intermetallics. The OLB process temperatures can have an effect on the
`encapsulation materials. These issues force the broad consideration of the entire
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 452
`
`

`
`TAPE AUTOMATED BONDING 427
`
`process flow and the effects it may have on materials and other processes. A
`coordinated approach with design, development and manufacturing is necessary.
`
`9.4.11 Comparison with Other Connection Technologies
`
`The choice of which connection technology (wire bond, TAB or flip chip) to use
`on MCM applications is based on a balance between cost and performance.
`TAB is most cost effective in high volume, low product mix environments. At
`lower volumes and higher part mixes, TAB becomes an expensive alternative.
`This expense can be justified where performance (electrical, thermal, etc.) of
`TAB justifies the use of a more expensive alternative.
`TAB inherently adds cost to the assembly process. The additional step of
`wafer bumping, the cost of each TAB frame and custom tooling all contribute
`to a higher assembly cost for TAB. These costs can make TAB unattractive
`unless the user has a high volume product
`Cost considerations have lead to the development of new materials and
`methods that may enable TAB to compete with the other chip connection
`technologies. Developments in single point and laser bonding techniques help
`eliminate rr...B and OLB pattern specific gang bond tooling. TAB standards help
`minimize the number of excise and form tools needed, as well as the hard
`tooling for tape fabrication.
`Electrical performance is improved through the use of TAB assembly. As
`the number of 1I0s on the die increase, the corresponding pad pitches decrease.
`This leads to the use of finer wire in wire bond applications that eventually limit
`electrical performance, TAB leads, at these pitches, using fine pitch, peripheral
`leaded die can achieve the desired electrical performance. These designs,
`however, must be carefully tailored to the electrical environment and may
`necessitate flip TAB configurations with short TAB leads or two metal layer
`tapes to attain the desired electrical goals. The result can be a balancing of high
`performance needs versus cost requirements since the use of short TAB leads
`goes against the current TAB standards and would require expensive custom tape
`designs and tooling. Likewise, two metal layer TAB tape is more costly than
`single metal layer tape.
`Thermal management issues also affect the connection decision. While
`conventional TAB configurations conduct heat through the substrate, as with wire
`bond, flip TAB designs require novel heat removal designs. Flip TAB designs
`also incorporate shorter lead lengths that help electrical performance and increase
`density. Again, the extra cost must be balanced against performance issues.
`Reliability studies of TAB assemblies indicate failures unique to TAB, while
`other concerns are common to all connection methods. These unique failures
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 453
`
`

`
`428 CIDP-TO-SUBSTRATE (FIRST LEVEL) CONNECTION TECHNOLOGY OPTIONS
`
`include TAB lead and solder joint failure which is controlled or eliminated with
`proper TAB design and material choices.
`Testability, and burn-in and repair are important attributes of TAB,
`especially for the MCM user, and constitute more advantages of TAB over the
`other connection methods. An inner lead bonded die can be tested or burned-in
`prior to committing that die to an expensive module, enabling the user to screen
`bad die out of the assembly flow. Die that do fail after attachment to the MCM
`can be removed and replaced at the OLB level, depending on the metallurgy.
`This process is difficult, if not impossible with wire bonded devices and is not
`a trivial process with flip chip.
`Flip chip applications are natural and, probably, inevitable extensions of
`packaging connection assembly. While the flip chip eliminates the tape frame
`and custom tooling required by TAB, bumping still is required. Presently, the
`infrastructure and assembly know-how for this technology is immature to the
`world at large. This makes TAB, especially flip TAB, a natural alternative.
`When the flip chip infrastructure has matured sufficiently to handle the advanced
`assembly needs of the MCM user, knowledge gained from flip TAB may be
`applied to future flip chip applications.
`
`9.4.12 Summary
`
`TAB assembly for MCM applications offers the multichip designer an
`opportunity to utilize high lead count, fme pitch semiconductors and create
`densely packed modules with superior electrical performance. The inner lead
`bonded die also can be tested or burned-in prior to bonding to the package,
`enabling the user to screen out bad die prior to their commitment to an expensive
`MCM. Die also can be removed at the OLB level and replaced with new die,
`preventing the loss of an expensive assembly.
`Materials and equipment for implementing a TAB process are available,
`allowing the use of TAB in design and manufacturing.
`the
`Tape material and assembly method options have presented
`manufacturing engineer with a variety of process options, enabling a tailoring of
`designs for different uses and environments. Reliability data for high
`performance TAB applications, a relatively young practice, has begun to filter
`through the electronic packaging industry.
`The choice of assembly methods for multichip applications, TAB, wire bond
`or flip chip, depends on the balance between cost and the desired performance.
`New methods and materials allow TAB to reduce its cost structure and compete,
`favorably, with the other assembly technologies.
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 454
`
`

`
`9.5 FLIP CHIP CONNECTION TECHNOLOGY
`
`FUP CIDP CONNECTION TECHNOLOGY 429
`
`Chee C. Wong
`
`9.5.1
`
`Introduction
`
`Flip chip connection technology as a ftrst level chip to package connection
`option traditionally is regarded as being synonymous with the Controlled
`Collapse Chip Connection (C4) process pioneered by IBM more than 20 years
`ago. The C4 process has set the highest record in I/O density, chip packing
`density and electrical performance, and establishes the industrial benchmark in
`fteld reliability. Details of the C4 process are presented in Section 9.6.
`This section presents the flip chip connection technology as a generic
`technology with the C4 process as a subset example of one particular application.
`Emphasis is placed on the concepts behind the design of the flip chip connection
`couftguration, the material options for the connection medium, the processing
`options in implementing flip chip and the cost and manufacturability issues in the
`context of inherent process limitations and existing infrastructure. The objective
`here is to introduce an overall perspective on flip chip connection technology
`beyond the C4 process to enable a judicious comparison to be made between the
`several flip chip variants and between flip chip connection and other chip
`connection options.
`This is a section on concepts rather than details. It offers an organized
`format of questions to be asked and provides a framework for answering those
`questions on an individual basis. Hopefully, it will stimulate the reader to
`evaluate the applicability of flip chip technology for his or her product goals.
`
`9.5.2 The Basics
`
`Definitions
`Flip chip is deftned by the schematic in Figure 9-25 which shows a bare IC
`device flipped upside down with its active area or I/O side attached to a substrate
`via a connecting medium.
`In this generic description, the device may be a
`silicon microelectronic IC or any other monolithically integrated active functional
`block. The substrate in Figure 9-25 may be any of the MCM substrates
`providing an interconnection network between the flipped active device and other
`active, or even passive devices. The connecting medium may be any suitable
`interface serving the various needs of the matchmaking between the flipped
`device and the underlying structure. Each member of this flip chip ensemble is
`examined in later sections.
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 455
`
`

`
`430 CIDP-TO-SUBSlRATE (FIRST LEVEL) CONNECTION TECHNOLOGY OPTIONS
`
`Figure 9-25 Flip chip configuration consisting of chip, connection medium, and substrate.
`
`MCM Substrate
`
`Why Flip a Chip?
`What is the greatest distinction of the flip chip configuration? Why a flip chip?
`Flip chip is the only connection configuration that allows assembled active chips
`to approach the fonn in which they were originally created, namely, the fonn of
`a wafer. This is an advantage because it provides superior electrical and thermal
`performance.
`To understand this point one must realize that the goal of any packaging
`scheme is to allow each chip to perform at its peak and to allow the system as
`a whole to take full advantage of the peak performance of each individual
`component. Circuit speed on the bare chip level is the highest speed achievable.
`As soon as the chip leaves its original wafer fonn and enters the first level of
`packaging, its perfonnance begins to suffer. Why then don't we build entire
`systems or subsystems on a single wafer? This approach, called "wafer scale
`integration," has met with little success. The problem is poor yield. While most
`parts of the system may function as designed, functional failure of a single part
`can "doom" the entire system. Hence, the current approach in hybrid
`microelectronics follows the modular concept, namely, to break a big system into
`smaller systems, build many small systems on a wafer, isolate and package the
`functioning small systems (IC chips) and reassemble them back into a big
`system. Figure 9-26 shows a schematic comparison between monolithic wafer
`scale integration and two modular alternatives, an unpackaged flip chip version
`and a packaged surface mount version.
`Since wafer scale integration has proven to be impractical because of yield
`issues, the next best thing in tenns of performance is to build a separate
`interconnection structure of commensurate interconnection density (such as an
`MCM) and to assemble the unpackaged IC chips back onto the MCM substrate
`so as to resemble their original wafer fonn as closely as possible. This translates
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 456
`
`

`
`I ~ -
`~ ;
`
`~
`
`density achievable by flip chip MCMs.
`Figure 9-26 Comparison of wafer scale integration and modular approaches to multichip packaging, highlighting the packing
`
`£;~~I
`
`(2) packaged chips
`
`(AsseMBLY)
`
`(1) flip chip MCM
`
`-. ~/
`
`I~ _ =========::::::=-==~
`
`rgooa-J ~ f'iOOclI f"iOciCT1
`
`g
`
`~~~~~~ L
`M-t f8OOCll.
`
`Interconnection substrate
`fabncate separate product-specific
`
`separate good chips
`
`modular alternatives:
`
`monolithic 51 IC wafer
`
`msgalica@mintz.com
`
`wafer scale Integration 1 EE L=:J [];] c=J c=:r ~ I, (fabdcatod on top of)
`
`b d
`
`Interconnection
`
`go
`~ ~ multilevel
`
`wafer-specific
`
`Elm Exhibit 2162, Page 457
`
`

`
`432 ClllP-TO-SUBSTRATE (FIRST LEVEL) CONNECTION TECHNOLOGY OPTIONS
`
`into a requirement for a connection technique which permits the closest possible
`chip proximity and a connection medium whose dimensions are contained within
`the area of the chip. Also, the connection medium should be amenable to short
`connection lengths to minimize electrical parasitics. By flipping a chip and
`directly attaching its I/Os via a connecting bump of controllable height onto the
`substrate as shown in Figure 9-25, the maximum footprint that the chip requires
`is that of its own. No fanout is required. This constitutes the distinct advantage
`of flipping a chip. As shown in Figure 9-26, the packing density of a flip chip
`MCM could, in principle, approach that achieved in wafer scale integration.
`
`Members of the Ensemble
`The characteristics of the individual members in a flip chip ensemble are
`presented as follows:
`
`1.
`
`IC Chips. Most silicon IC chips presently are designed for perimeter
`wire bonding. The I/O pads, on the order of 4 mils, are fmished with
`an Al metallization and surrounded by a passivating layer of dielectric.
`The degree of perfection of this passivation layer is inadequate in
`providing mechanical and environmental protection 'for the chip. The
`number of I/O pads on IC chips could range from several tens to
`several hundreds. There is no industrial standard in the spatial
`arrangement of 110 pads. Silicon chips generally are not readily
`available in bare wafer form. Instead, they are readily available only
`in die form.
`
`2. Substrate. The substrates for MCMs could be in the form of coftred
`or thin ftlm ceramics, thin ftlm silicon, printed boards or flex circuits.
`These various structures are reviewed in Chapters 1,5,6 and 7. MCM
`substrate design, being considerably less mature compared to chip
`design, is more tolerant of the needs of chip connection. To make full
`use of any chosen MCM platform, design of the substrate and design of
`chip connection need to be carried out in parallel.
`
`3. Connection Medium. The connecting medium couples the chips to the
`substrate to form a functional and reliable MCM. TAB and wire
`bonding techniques achieve connection using leads which fanout from
`the chip I/O to the corresponding pad on the substrate. Flip chip
`bonding achieves electrical and thermal connectivity using bumps
`(before joining), called joints after joining. These joints provide
`mechanical support for the flipped chip on the substrate. The C4
`process uses bumps made of solder or solder-coated copper balls.
`Organic conductors are new candidates for the connection medium.
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 458
`
`

`
`FllP CIDP CONNECTION TECHNOLOGY 433
`
`Note that out of the several functions of the IC chip package discussed in
`Chapter 1, flip chip connection has fulftlled only the functions of electrical and
`thermal connection. Mechanical protection generally is delayed until the module
`packaging level. If the module level package is not considered adequate for
`environmental protection, then chip encapsulation techniques are used to protect
`the chip from operating ambients. The issue of chip testability in its bare chip
`or wafer form prior to module level assembly is considered a major inadequacy
`of flip chip technology.
`Mechanical support of the chip itself, which was not an issue in the case of
`unflipped IC chips die bonded onto the package, is now provided by the joints
`and introduces an important new variable in fatigue-related reliability. Hence,
`to complete the picture of using flip chip as a connection technique for MCMs,
`at least three new members have to be added to the ensemble depicted in Figure
`9-25: a chip testing capability for the bare or bumped die prior to assembly, an
`encapsulation technology after assembly [55], and proper designs for minimizing
`susceptibility to thermal fatigue [56]-[57].
`
`Why flip a chip revisited
`As mentioned, flipping a chip onto an MCM could achieve wafer level packing
`density by eliminating fanout. There is another feature unique to having the
`active side of the chip face the top of the interconnecting substrate. Since the
`I/O pads on the chip also are fabricated on the active side, the layout of these
`pads easily can be expanded into an array covering the entire inner area of the
`chip, rather than being confined onto the perimeter. Area arrays offer a way of
`increasing I/O density without taxing other technologies for a finer I/O pitch.
`For example, for a chip size of 5 mm and a constant I/O pad spacing of 1 00 ~,
`a perimeter array could accommodate about 200 I/Os while an area array could
`accommodate about 2000 I/Os, a tenfold increase. Only the flip chip
`configuration provides the ability to achieve higher I/O density without
`decreasing I/O pitch.
`By having the active side down, flip chip bonding also offers the shortest
`possible leads with the lowest inductance, maximizing the operating frequency.
`This consideration alone could justify the usage of flip chips in high performance
`systems. The actual length of the lead, or, in this case, the standoff height of the
`joint, could be controlled by any of the flip chip techniques in use, and is usually
`chosen to optimize other criteria rather than being predicated by the geometry of
`the unflipped chip. Joint height is usually designed for better fatigue endurance
`and chip underside cleaning.
`Flip chip assembly is inherently a batch bonding process. This contrasts
`with wire bonding which proceeds serially. The throughput advantage of batch
`bonding is obvious at high I/O densities. Batch bonding also is offered in beam
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 459
`
`

`
`434 CIDP-TO-SUBSTRATE (FIRST LEVEL) CONNECTION TECHNOLOGY omONS
`
`lead bonding and gang bonding versions of TAB. While TAB could sidestep the
`high tooling cost of TAB gang bonding techniques by temporarily employing
`single point bonding techniques, the flip chip technique has to confront the
`assembly issue of high speed batch bonding directly. Once the initial barriers of
`developing versatile and cost effective flip chip batch bonding machines are
`overcome, batch bonding could become the bonding method of choice for most
`current chip sizes. As maximum chip size increases, tooling for batch bonding
`becomes more difficult because of issues in planarity, heat distribution and wider
`disparity in chip sizes. At that stage, the benefits of batch bonding can be
`realized only by investing in more costly tooling.
`The robustness of flip chip connections has set the reliability benchmark in
`the connection industry. The absence of leads makes the IC chip rugged and
`easier to handle. Issues of thermal fatigue have so far been adequately addressed
`by proper joint design (see Section 9.6). As chip sizes increase, issues of fatigue
`life again will dominate the question of joint mechanical integrity. This point
`argues in favor of using silicon MCM substrates for flipped silicon chips to
`circumvent the detrimental effects of coefficient of thermal expansion (CTE)
`mismatches and the resultant fatigue phenomenon.
`
`9.5.3 Connection Medium (I): Solder Bumps
`
`The connection medium between the flipped silicon chips and the underlying
`MCM substrate is the key in realizing any flip chip technology. This is where
`the issues of manufacturability and cost are defmed. The material and
`fabrication method chosen for the connection medium influence chip and
`substrate reliability, yield and throughput in assembly.
`The two connection media currently in use for flip chip MCMs are solder
`and organic conductors. This section presents an overview of solder bumping
`(bumping using organic conductors is deferred to another section), with emphasis
`on the comparative strengths of different techniques and the basic roles of
`various materials used in the formation of the bump. One of the teclmiques
`mentioned is the C4 process, treated in greater detail in Section 9.6.
`
`Bump Location
`The three possibilities of locating the solder bump on the substrate, on the chip,
`or both, are shown in Figure 9-27. The decision is based on the following:
`
`Which is the easiest to do
`• Which side is likely to experience less impact going through
`a solder bumping process
`• Which is better for handling and storage
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 460
`
`

`
`FIlP CIDP CONNECTION TECHNOLOGY 435
`
`chi~
`
`• •
`
`substrate
`
`• •
`
`chip
`•
`•
`substrate
`
`II
`
`II
`
`chip
`
`.... •
`
`substrate
`
`a
`
`b
`
`c
`
`Figure 9-27 Three possibilities of locating bumps connecting chip to substrate.
`
`• Which is the easier to assemble
`• Which is the easier to repair and
`• Which is the most cost effective in terms of overall yield.
`
`To answer these questions, consider the members chosen for the flip chip
`ensemble. Silicon chips are produced in wafer form, regardless of type and
`function. MCM substrates could range from silicon wafers (making them
`equivalent to silicon chips in terms of processing) to flexible copper polyimide
`circuits. The equipment for handling and processing these various substrates are
`equally varied, each specializing in optimized processing for that particular
`substrate. If different substrates for different applications are envisioned, it
`would be practical to concentrate on placing bumps on silicon wafers only, since
`the wafer form of silicon chips remains invariant. The placement of solder
`bumps onto chip wafers turns out to be advantageous in areas such as testability
`and repair also. Details of the rework process for solder bumped chips are
`discussed in Section 9.6.
`There is also an overall yield advantage for placing bumps on chip wafers.
`Any silicon chip on any MCM substrate is always smaller than the substrate.
`For a given unit area being processed, more chips are produced than substrates.
`Let's take an example of a five chip set MCM of 1 inch square. Here, in the
`same inch square area being solder bumped for one MCM substrate, five chips
`could be processed. Assume also that the defect level is such that one bad bump
`(short or missing) is produced per inch square on average. This one bad bump
`on the substrate would render the entire MCM useless, whereas it would only
`disable one of the five chips. A healthy chip from a neighboring group could be
`substituted in place of the bad chip to still produce a good MCM. The moral
`here is that, for a given defect level, smaller objects are more tolerant of defects
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 461
`
`

`
`436 CffiP-TO-SUBSlRATE (FIRST LEVEL) CONNECTION TECHNOLOGY OmONS
`
`than larger objects in terms of overall yield. Since chips are always smaller than
`their mating substrates, it is justified to place bumps on the chip wafer.
`Placing the solder bump onto the substrate (Figure 9-27a) is justified in the
`case where chip wafers cannot survive the temperature or the physical and
`chemical environment of a solder bumping process. For example, an aggressive
`backsputtering step (for via cleaning) in a solder bumping process may damage
`CMOS chips sensitive to strong radiation. Bumping substrates also is justified
`if chips are not available in wafer form. Placing bumps on both the chips and
`the substrates adds more cost; however, this scheme becomes mandatory if the
`solder height limitation inherent in any single bump architecture is insufficient
`to meet joint height specifications.
`
`Bump Shape
`Schematics of a solder bump before and after reflow are shown in Figures 9-28a
`and 9-28b, respectively. Reflow is a heating process which takes the solder
`bump through a solid to liquid to solid transition, allowing the solder to
`consolidate its bonding with the connecting interface. While the geometry of the
`bump in Figure 9-28a could differ depending on the processing technique, the
`reflowed bump shape in Figure 9-28b is universal, governed solely by the forces
`of surface tension, gravity and the tendency of the liquid solder (during reflow)
`to assume a shape of minimum surface energy. For small bumps where the
`effect of gravity can be neglected, the equilibrium shape is a spherical segment.
`The surface onto which the solder bump is fabricated consists of two distinct
`areas in the vicinity of the bump: a wettable and a non-wettable area. The
`wettable area is the bonding interface to the solder. Usually the chip's I/O pad
`with an Al finish is located directly below the wettable area for electrical
`
`deposited solder bump
`
`reflowed solder bump
`
`\
`\
`wettable area
`
`non wettable area
`
`non wettable area
`
`wettable area
`
`Figure 9-28 Schematic of a solder bump (a) before and (b) after reflow.
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 462
`
`

`
`FUP ClllP CONNECTION TECHNOLOGY 437
`
`connection, although dummy bumps whose wettable areas are not connected to
`110 pads also could be fabricated for reasons of mechanical robustness or
`improved thermal performance. The non-wettable area is necessary to confine
`the solder within its allowable area, thus controlling the final height of the bump
`for a given volume of solder.
`The shape transformation from Figure 9-28a to Figure 9-28b is determined
`entirely by the volume of the deposited material and the area of the wettable
`region. The original area of the solder deposit mayor may not correspond to the
`area of the wettable base, depending on the technique and the design. The [mal
`footprint of the reflowed bump, however, corresponds exactly to the wettable
`area, assuming complete wetting during reflow. In other words, if the solder
`deposit area is smaller than the wettable area, then solder spreads outward during
`reflow; conversely, the solder footprint shrinks back. This fact, coupled with the
`knowledge that the equilibrium shape of a reflowed solder bump is that of a
`spherical segment, allows us to predict the final shape and height of the reflowed
`bump.
`The plot in Figure 9-29 shows the reflowed bump height as a function of the
`height of the solder deposit. The plot is delineated into three regions,
`corresponding to different shapes of the spherical segment. Figure 9-29b shows
`a perfect hemisphere, while Figures 9-29a and 9-29c show spherical segments
`which are smaller (sub-hemisphere) and larger (super-hemisphere) than the
`hemisphere, respectively. The line of unity slope in the plot is given as a
`yardstick to distinguish the region where the reflowed height is larger than the
`deposited height (above this line) and the region where the opposite is true
`(below this line). The reflowed height of the solder bump has an approximately
`cube root dependence on the height of the solder deposit. This curve crosses the
`straight line in the region where the shape of the bump is a super-hemisphere.
`This means that as long as the bump shape is that of a hemisphere or smaller,
`the deposited volume of solder is used efficiently in building the height of the
`bump. When the shape crosses into the regime of super-hemisphere, a further
`increase in the deposited volume makes little contribution to the height of the
`reflowed bump, most of the material going toward enlarging the waist of the
`bump instead. This can be seen in the shape of the super-hemisphere where the
`largest cross sectional area of the bump is no longer at the base; rather, it has
`migrated toward the middle. This has an effect of creating a reentrant comer at
`the point where the solder bump meets the wettable area. Similar considerations
`regarding solder joint geometry have been presented by Goldman [57], for which
`the same conclusions apply. Unfortunately, such reentrant comers would
`concentrate strain at the base of the joint, rather than distributing it throughout
`the solder volume. In other words, the solder joint would not be used efficiently
`as a mechanical support. The point of this discussion is that geometrical design
`
`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 463
`
`

`
`438 CIDP-TO-SUBSlRATE (FIRST lEVEL) CONNECTION TECHNOLOGY OPTIONS
`
`100 - Diameter of Base Metal = 100 IJm
`90 Diameter of Solder Deposit = 100 IJm
`
`Radius of Base Metal
`
`JO
`
`....... -1- . SUPER-Hemisphere
`
`W~--~--------~~----r---~-----r----~--