274 THIN FILM MULTILAYER INTERCONNECTION TECHNOLOGIES
`
`stress. The stressed TiW films can flake from the walls of sputtering systems
`and produce particulates. Ni is another common diffusion barrier for Au, but it
`has only a moderate interaction with polyimide and thus, moderate adhesion.
`The most important advantage of Ni is that it can be electrolytically or
`electro less plated. Electroless plating is useful in protecting the sidewalls of Cu
`conductor lines from attack by polyamic acid.
`
`Top Layer Metallization
`The top metal layer in a TFML interconnection system serves a different function
`and has different requirements than the internal layers. It must be resistant to
`corrosion, strongly adherent to the dielectric and compatible with the assembly
`processes (wire bonding, soldering or die attachment). Au is used most
`commonly as a top layer metal because of its excellent corrosion resistance and
`its compatibility with die attachment and wire bonding processes. Au requires
`an adhesionlbarrier metal between itself and the dielectric or underlying
`conductor. The most common interface metals for Au are Ni, Cr or TiW. Cr or
`TiW are sputtered, Ni is usually electroplated and Au may be sputtered,
`electroplated or electro less plated. For wire bonding or die attach, the Au is
`usually I - 3 J.Ull thick. For soldering, excessive Au embrittles the solder, so a
`thin flash (less than 0.1 J.Ull) of Au is used over the solderable metal, either Ni
`or Cu. For flip chip solder bonding, a metallization sequence such as sputtered
`CrlNi-Cu plated with Ni and Au [8] or Cr/Cu with a flash of Au [12] is used.
`
`7.3.3 Dielectric Materials
`
`There are many options for the dielectric material in a thin film interconnection
`system. The dielectric must have good thermal and chemical stability over the
`range of conditions encountered in thin film processing, assembly and end use.
`The CTE of the dielectric should be well matched to the substrate to minimize
`stress and warping of the substrate. Processes must be capable of depositing the
`dielectric in thicknesses up to 25 J.Ull with low stress and no cracks or pinholes.
`Ideally the dielectric should smooth or planarize the large topography created by
`underlying conductor patterns. The most important electrical property for the
`dielectric material is a low relative dielectric constant (Er) as discussed in Section
`7.2. The dielectric material also should have a reasonably low dissipation factor
`to avoid significant losses in the dielectric at high frequencies.
`
`Polymer Dielectrics
`High thermal stability polymers are the most frequently used dielectric materials
`for TFML interconnections, although silicon oxides have also been used.
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`MATERIALS 275
`
`Polymers are attractive in general because they have low dielectric constants and
`can be deposited from solution using spin or spray coating processes. Polymer
`dielectrics are discussed in detail in Chapter 8.
`The most common polymer dielectrics are polyimides, a broad class of
`polymers characterized by aromatic groups and an imide ring in the repeat
`structure. Polyimides are deposited as a soluble precursor, usually polyamic
`acid, or as a soluble ester or acetylene terminated polyimide that is already
`imidized. The solution viscosity or coating parameters can be varied to achieve
`a wide range in ftlm thickness. The polymer solution flows on the substrate,
`thus planarizing the conductor and via topography. Curing the solution at
`temperatures up to 450°C removes the solvents and converts the precursor to a
`stable, insoluble polyimide.
`Fully-cured polyimide films are generally stable to 500°C, mechanically
`tough and flexible, and inert to process solvents and chemicals. Polyimides also
`have a low dielectric constant (2.0 - 3.5), a relatively low dissipation factor and
`high breakdown voltage. Polyimides that were developed frrst and are still
`widely used, such as PMDA-ODA and BTDA-based chemistries (refer to
`Chapter 8), have two significant drawbacks:
`(1) high moisture absorption
`resulting in a large variation in dielectric constant (30% variation in Cy over the
`full range of relative humidity) [14], and (2) a large CTE (20 - 50 ppm/°C) that
`causes warping of low-Cm substrates (refer to Equation 5). To alleviate these
`short comings, low thermal expansion polyimides with a rigid backbone structure
`have been introduced [15]. The low CTE polyimides also have less moisture
`absorption, a lower dielectric constant (2.9 - 3.0) and higher tensile strength than
`the earlier polyimides.
`A number of alternative polymers with certain advantages over polyimides
`also have been introduced. Polyphenylquinoxaline (PPQ) has a low dielectric
`constant (2.9), low moisture absorption, good mechanical properties and good
`adhesion. Polyquinolines have a low dielectric constant (2.6), very low moisture
`absorption, low stress when deposited on silicon, good planarization, long shelf
`life at room
`temperature and do not cause corrosion of Cu
`[16].
`Polybenzocyclobutenes (PBCBs) have several desirable properties including
`excellent planarization, a low cure temperature (250°C), a low dielectric constant
`(2.7), low dissipation factor, low moisture absorption (0.3%) and good adhesion
`to Cu without metal adhesion layers. However, the PBCBs have a very high
`cm (50 ppmfOC) and low elongation at break, and are susceptible to oxidation
`during curing or temperature aging. The oxidation problem has been solved by
`curing under a nitrogen atmosphere and adding an antioxidant to the formulation.
`Fluorinated poly(aryl ethers) have very low moisture absorption and an extremely
`stable dielectric constant (2.7) with temperature aging. The development of
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`
`276 TIDN FILM MULTILAYER INTERCONNECTION lECHNOLOGIES
`
`specialty polymers for thin film interconnections will continue to be an active
`area for development as the MCM-D market grows.
`
`Silicon Dioxide Dielectric
`Silicon dioxide (Si02 is used as a dielectric medium by nCHIP, a company that
`manufactures "Silicon Circuit Boards" consisting of thin film interconnections
`on silicon substrates. The Si02 dielectric layers are deposited by a plasma
`chemical vapor deposition (CVD) process that produces films up to 20 J.lIIl. thick
`under moderate compressive stress. nCHIP cites several advantages of the Si02
`dielectric:
`
`It requires fewer processing steps than polymer dielectrics.
`1.
`2. The compressive stress in the ftlm cancels the intrinsic tensile stress of
`metal ftlms and produces a flat substrate.
`3. Si02 has a reasonably high thermal conductivity (1.5 W/moC, ten times
`greater than most polymers), eliminating the need for thermal vias to
`conduct heat through the interconnect layers.
`4. Si02 does not have the high moisture absorption of polymers.
`5. The dielectric is rugged, wire bondable and more reliable under thermal
`cycling, shock or nonhermetic environments.
`
`Potential disadvantages of this dielectric are its slightly higher dielectric
`constant (fy = 4.0), its lack of planarization, susceptibility to pinholes and the
`slow deposition rates and high cost of the process gases, particularly silane.
`Although the CVD process requires fewer steps than polymer deposition and
`curing, it is unclear which dielectric will be more cost effective in a
`manufacturing environment. Additional vendors must offer Si02 dielectric and
`comparative studies of polymer dielectrics versus Si02 must be conducted before
`this dielectric will find widespread use in TFML interconnections.
`
`7.4 THIN FILM MULTILAYER PROCESSING
`
`TFML interconnections are fabricated using a repetitive sequence of unit
`processes for depositing and patterning conductor and dielectric layers. This
`section begins by describing the unit processes that are used most frequently.
`Then two basic approaches for patterning conductor features, additive and
`subtractive processing, are described and compared. Finally, some of the unique
`challenges imposed by TFML designs are discussed.
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`PROCESSING 277
`
`7.4.1 Conductor Deposition and Patterning Processes
`
`Conductor Deposition
`Conductor materials can be deposited by vacuum-based processes such as
`evaporation, sputtering, ion plating or by wet processes such as electrolytic or
`electroless plating. Several textbooks provide detailed descriptions of thin ftlm
`deposition processes [17]-[18]. A recent paper compares the ftlm properties
`(resistivity, stress, microstructure and adhesion) of Cu, AI and Au deposited by
`sputtering, evaporation, enhanced ion plating and electroplating [19]. The metal
`deposition processes that are used most frequently are described below.
`Sputtering. Sputtering is a vacuum-based process in which the ions (usually
`Ar+) in a plasma are accelerated toward a target material, ejecting or "sputtering"
`the target atoms by momentum transfer. The sputtered atoms deposit on surfaces
`exposed to the plasma. including substrates. The plasma can be sustained by
`either an RF or DC discharge. Magnets can be used to concentrate the plasma
`and enhance the sputtering rates without overheating the target. The substrate
`is heated by condensation, and both the target and substrate are heated by ion
`bombardment. The ability to cool the substrate or target can determine the
`maximum deposition rate.
`Sputtering is the most widely used vacuum deposition process because it
`offers a number of advantages:
`
`1. Almost any material can be deposited, including insulators, adhesion
`metals, thin ftlm resistors (such as tantalum nitride or Ni-Cr) or the
`primary conductor.
`2. Excellent adhesion to the substrate or dielectric material can be achieved
`by backsputtering or bombarding the surface with argon ions prior to
`depositing the metal.
`3. Films can be deposited with excellent control of thickness, stress and
`morphology through variations of process parameters such as pressure,
`power and electrical bias of the substrates.
`4. Sputtered thin ftlms have low resistivity due to the high packing density
`of the atoms.
`5. The ftlms achieve conformal coverage of via holes and other
`topography.
`6. Automated equipment is available for sputtering because of its
`widespread use in the Ie industry.
`
`The main drawbacks to sputtering are its relatively low throughput rate (because
`of slow deposition rates and limited batch size) and the high cost of equipment.
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`
`278 TIllN FILM MULTILAYER INTERCONNECITON TECHNOLOGIES
`
`Evaporation. To deposit metals by evaporation, the metal is heated to a
`vapor using an electrical resistance heater or electron beam, and the vapor
`condenses on the substrates. Because the process is carried out at much lower
`pressures than sputtering (10-5 _10-6 torr versus 10-2 - 10-3 torr for sputtering), the
`mean free path of the vaporized metal atoms is tens of meters, and deposition
`occurs only on surfaces that are directly exposed by "line of sight" to the
`deposition source. Therefore vertical surfaces such as via sidewalls are not
`coated as thickly as horizontal surfaces and overhanging surfaces can completely
`shadow underlying surfaces from deposition. The line of sight deposition can be
`used to advantage in liftoff processes (discussed later). In general, evaporated
`films have poorer adhesion than sputtered ftlms because the atoms arrive at the
`substrate with lower energy. There also is less control of ftlm stress and
`microstructure with evaporated films, since there is no controllable substrate bias
`to affect ion bombardment of the growing ftlm.
`Alternative Vacuum Deposition Processes. A variety of alternative vacuum
`deposition processes may be considered for thin ftlm interconnections. Examples
`are ion cluster evaporation, ion plating (or enhanced ion plating), cathodic arc
`deposition, or ion beam sputtering. In ion cluster evaporation and ion plating,
`a thermally evaporated material is ionized and the metal ions are accelerated
`toward a biased substrate. These processes achieve good adhesion and packing
`density due to the high energy of arriving atoms. Film morphology and
`properties can be controlled by varying the evaporation rate and substrate bias.
`Cathodic arc deposition and ion beam sputtering are alternative processes for
`sputtering a target material. Cathodic arc deposition can achieve very high
`deposition rates. The primary limitation to all of these alternative processes is
`the relative lack of industry experience and automated equipment for high
`throughput processing.
`Electroplating. Metals can be deposited from ions in a liquid solution by
`electroplating or electro less plating. Electroplating requires the application of an
`electrical potential to a metal seed layer on the substrate, while electro less plating
`can deposit metal through chemical reactions without an applied potential.
`Electroless plating is limited to thin coatings and therefore is useful mainly for
`interface or barrier metals. Electroless plating of Ni also has been used to fill
`vias [20].
`For the thick conductor layers required in most TFML interconnections,
`electrolytic plating is used. Electroplating is well understood and widely used
`for top metal NilAu metallization. Electrolytic plating first requires deposition
`of a seed layer, usually by sputtering. An electrical contact is made to the seed
`layer and a current is applied. The substrate acts as the anode in an electrolytic
`cell and the metal ions are reduced and deposited on the substrate. The plated
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`PROCESSING 279
`
`metal can be deposited as a blanket coating or in open areas defmed in a
`photoresist film (the additive approach described later).
`The main advantage of electroplating is the high deposition rate, typically
`on the order of flIll per minute. Therefore, electroplating, often is used for thick
`power/ground planes or thick signal lines (> 5 flIll). A drawback of plating is
`the difficulty in controlling the process and film properties. The plating
`deposition rate, uniformity, film stress and morphology are dependent on a
`variety of process parameters, such as bath composition, temperature, agitation,
`electrode design and the plated area. The bath composition must be continually
`monitored and adjusted. Impurities in the plating bath can cause poor adhesion,
`defects or variation in the properties of plated films. In general, electroplated
`films have lower density and higher resistivity than vacuum deposited films.
`Finally, electroplating cannot deposit some metals and allloys that can be
`deposited by sputtering.
`
`Conductor Patterning
`Conductor layers can be patterned by either subtractive or additive processes, as
`discussed in Section 7.4.3. The unit processes discussed below are primarily
`used for subtractive patterning (etching) or direct writing of conductor patterns.
`Wet Etching. Wet etching removes conductor material at a controlled rate
`by oxidizing the metal and converting it to a soluble product in an acid solution.
`It is the patterning process used most widely for 1FML structures because it
`involves inexpensive equipment and can achieve high etch rates. The ideal
`etchant will selectively etch the desired metal without attacking the substrate or
`interface metals. The main limitation of wet etching is the resolution or aspect
`ratio achieved in conductor features. Because the chemical reactions proceed at
`an equal rate in all directions, wet etching undercuts the photoresist and produces
`a sloped sidewall. Figure 7-5 shows the undercut and sloped sidewall in a
`sputtered copper film 8 flIll thick that has been spray etched. The undercut
`limits wet etching to aspect ratios below about 0.5, sufficient for most thin film
`interconnect designs.
`Wet etching may be done by immersion or by spraying the etchant Spray
`etching produces more vertical sidewalls and achieves better etch uniformity and
`higher etch rates by removing depleted reactants. Accurate control of linewidth
`requires a method for detecting the endpoint of etch. Bath parameters such as
`temperature, oxidation potential, pH and additives such as surfactants must also
`be controlled.
`Dry Etching Dry vacuum processes for metal etching include ion beam
`etching, reactive ion beam etching (RIBE) and reactive ion etching (RIE). These
`techniques can produce much higher aspect ratios because the processes are
`activated by charged species accelerated perpendicularly to the metal surface.
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`
`280 TIIIN FILM MULTllA YER INTERCONNECTION TECHNOLOGIES
`
`Figure 7-5 SEM micrograph of the sidewall in a spray etched copper film (8 f.LID thick),
`showing undercut beneath the photoresist.
`
`Ion beam etching (or ion milling) uses a beam of mert gas ions (such as Ar+)
`accelerated perpendicularly or at an angle to the substrate to dislodge metal
`atoms (as in sputtering). Ion milling can etch very high aspect ratio features in
`any material, however, it etches at a slow rate, has poor selectivity (many
`materials etch at similar rates) and causes heating of the substrate and
`photoresist. RIBE is a similar process, but uses a reactive gas to achieve higher
`rates or better selectivity. RIE uses a plasma, usually sustained by an rf
`discharge between parallel plates, as a source of reactive ions and neutral species
`that etch the conductor material. RIE achieves higher etch rates and better
`selectivity than ion milling or RIBE. RIE of AI is a widely practiced process in
`the IC industry, whereas the RIE of Cu requires high electrode temperatures to
`volatilize the reaction products, and is not a practical option at this time. The
`biggest drawback to all of the dry etch processes is the high cost of equipment.
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`
`PROCESSING 281
`
`Laser Patterning Some of the most promising alternative processes for
`patterning conductors are based on the use of lasers to write conductor lines
`directly. The two basic approaches for laser direct writing are: (1) using a laser
`to decompose liquid or gaseous organometallic compounds, and (2) decomposing
`catalytic metals such as palladium (Pd), followed by selective electroless plating
`of Cu or Au. The direct writing processes eliminate the need for masks or
`photolithographic processes and can be computer driven, but are limited in
`writing speed and thickness of the deposited conductor. Thus, they are most
`attractive for quick turnaround, low volume prototype fabrication, or for the local
`repair of conductor faults. Figure 7-6 shows links in a conductor pattern made
`by localized laser irradiation of a Cu formate ftlm [21].
`Lasers also can be used to etch conductor material, either by direct ablation
`in an inert atmosphere or by initiating reactions in a reactive gas or liquid. Laser
`ablation has been used for many years to trim thin film resistors. The main
`limitation to laser etching is the long time required to clear large areas. Thus,
`
`Figure 7-6 Links in a copper conductor pattern filled in by localized laser irradiation of
`copper formate solution.
`(Courtesy of R. Miracky, Microelectronics and Computer
`Technology Corp.)
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`
`282 TInN FILM MULTILAYER INTERCONNECTION TECHNOLOGIES
`
`Figure 7·7 Openings in gold-nickel conductor lines (5 /lID thick x 15 fllll wide), cut by
`a frequency-doubled Nd:YAG laser.
`(Courtesy of R. Miracky, Microelectronics and
`Computer Technology Corp.)
`
`laser etching processes are most useful for defect repair. Figure 7-7 shows Au(cid:173)
`Ni conductor lines 5 J.I1ll thick x 15 J.I1ll wide on polyimide, cut by a frequency(cid:173)
`doubled Nd:YAG laser [21]. Note the minimal damage to the polyimide.
`
`7.4.2 Dielectric Deposition and Patterning Processes
`
`Because the predominant dielectric materials are polymers deposited from
`solution, the following discussion focuses on polymer deposition and patterning
`processes, particularly those used for polyimide.
`
`Polymer Deposition Processes
`Polymer films can be deposited from solution by a variety of techniques
`including spin coating, spraying, dipping, screen printing, roll coating and
`extrusion. In all of these processes, the low viscosity of the deposited solution
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`
`PROCESSING 283
`
`allows it to flow and planarize underlying topography. The thickness, uniformity
`and planarization of the film depend on the viscosity and solids content of the
`solution. Surface tension in the coating causes edge bead, a build up of polymer
`near the edge of the substrate that can interfere with the patterning of features
`near the edge.
`After deposition, the films are cured by heating at a controlled rate in an
`oven, hot plate or tube furnace to evaporate solvents and complete such reactions
`as the conversion of polyamic acid to polyimide. As the film cures, its viscosity
`increases until it is not able to flow; further volume reduction causes the film to
`partially conform to underlying topography. The fmal properties and adhesion
`of the polymer films depend on curing rate and final curing temperature, ranging
`from 250°C - 450°C. The atmosphere of the curing chamber is also important.
`In general, a nonoxidizing atmosphere is preferred to avoid oxidation of
`underlying conductor layers or the polymer itself.
`Multiple coats may be used to achieve the layer thickness required for high
`impedance interconnections. The planarization improves with each coat. An
`important consideration in multiple coatings is the polymer-to-polymer adhesion.
`Good adhesion requires polymer interdiffusion at this interface. Interdiffusion
`depends on the degree of cure and the T g of the underlying fIlm. In general, a
`lower cure temperature or a lower T g for the underlying film will improve
`polymer to polymer adhesion. Polymers that have poor self adhesion are
`sometimes treated with a plasma to roughen the surface prior to subsequent
`coatings.
`An organosilane-based adhesion promoter is often used to improve the
`adhesion of the first polyimide coat to silicon or ceramic substrates [22], [23].
`The adhesion promoter is applied as a very thin fIlm, usually by spin coating.
`In recent years, polyimide formulations that are self priming or that contain
`adhesion promoters have become available.
`Spin Coating. The most common process for depositing polymer fIlms is
`spin coating. This well characterized process is used frequently for depositing
`photoresists in IC fabrication. Highly automated equipment, known as track
`systems, can load substrates from a cassette, dispense the polymer solution, spin
`the substrate at a controlled speed and acceleration, remove the edge bead by
`applying a solvent to the outer edge of the spinning substrate and perform an
`initial cure on hot plates. Adhesion promoters also can be applied on the track
`system. The film thickness can be controlled accurately by varying the spin
`speed and time and very uniform thicknesses can be obtained. The main
`drawback to spin coating is its relatively low throughput rate and difficulty in
`spin coating large, square substrates. Spin coating also wastes 90 - 95% of the
`dispensed polymer.
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`

`
`284 TInN FILM MULTILAYER INTERCONNECTION TECHNOLOGIES
`
`Spray Coating. An attractive alternative to spin coating is spray coating.
`In systems designed for microelectronics processing, substrates are loaded on a
`conveyor that moves beneath a reciprocating arm that dispenses the solution at
`a controlled rate through an atomizing nozzle. The thickness can be controlled
`accurately by varying the flow rate and the conveyor speed. The diluting
`solvent, solution viscosity, solution concentration, nozzle diameter and nozzle
`distance from the substrate are critical to the ftIm uniformity. Spray coating is
`an ideal production process because of its high throughput capability and its
`ability to coat a wide range of film thicknesses on a wide range of substrate
`shapes and sizes, including large, square substrates. However, spray coating
`produces a larger edge bead and more local thickness variation than spin coating.
`Also, the process is sensitive to particulates, which can cause local dewettiog and
`pinholes in sprayed films. The correct solvent and solution concentration will
`pe1lllit enough flow on the substrate to prevent pinholes, yet not enough to cause
`pooling and large thickness variation.
`Extrusion. FAS Technologies recently introduced an extrusion process for
`coating polymer films [24]. The polymer solution is dispellsed by a positive
`displacement, diaphragm driven pump with a master cylinder for ftItering the
`solution at low pressure and a slave cylinder for accumulating and dispensing the
`solution. The metered solution is forced through a linear orifice in an extrusion
`head that is -0.25 mm above the surface of the substrates that are moving
`beneath the head. This casts a polymer film across the full width of the
`substrate. The extrusion process can deposit films 1 -100 IJ1Il thick with 2 - 5%,
`uniformity across the substrate and from substrate to substrate.
`The extrusion process has several important advantages:
`
`1. The large material waste of spinning or spraying is eliminated, since
`most of the polymer stays on the substrate.
`2. Films can be deposited on large square substrates.
`3. Edge bead can be eliminated and a clear zone can be left around the
`perimeter of the substrate.
`4. A wide range of thicknesses can be deposited in a single pass.
`5. High throughput can be achieved.
`
`Possible concerns include the effect of substrate warpage on coating uniformity,
`and the effects of particulates, vias and topography on film defects. Further
`characterization of this process is required, but it has the potential for
`significantly reducing the material cost in high volume production.
`
`Patterning of Polyimide Films
`Polyimide films may be patterned by a variety of processes including wet or dry
`etching through a photolithographically defmed mask, direct photopatterning of
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`
`PROCESSING 285
`
`Wet Etch
`(7 sleps)
`
`Dry Etch
`(9 steps)
`
`Photosensitive
`Polylmlde
`(4 steps)
`
`7////////////h
`
`7////////#&
`
`Hard Cure
`(for dry etch only)
`
`Deposit Masking
`Layer
`
`Apply Photoresist
`
`W)»»>>M
`~$k}}));d
`
`W)/))W)i)i
`ill j 1 j ill
`
`w)))))))))}l
`.!...!...! I I 1 ll.l
`
`Expose
`
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`~»'/7//Ph?
`
`il! 1_1_1_1 II
`
`tJ$7////~
`
`Develop
`
`Etch Mask
`(plasma)
`
`Etch Polylmlde
`(PA developer or
`plasma)
`
`Remove PR (wet)
`Remove Mask (dry)
`
`Figure 7-8 Process steps for patterning polyimide films by three different
`methods: wet etching, reactive ion etching and photopatterning of photosensitive
`polyimide.
`
`photosensitive polyimides or laser ablation. The process steps involved in wet
`etching, dry etching and photopatteming are shown in Figure 7-8.
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`
`286 TIllN Fll.,M MULTIlAYER INfERCONNECTION TECHNOLOGIES
`
`Wet Etching. Polyimide films can be wet etched by partially curing the film,
`patterning a photoresist coating, and dissolving the exposed polymer in an
`aqueous base solution. Many positive photoresist developers etch the partially
`cured polyimide, pennitting development and wet etching in a single step. Wet
`etching is a simple and inexpensive process, but produces low aspect ratio
`features because of the isotropic etch. The etch rate and geometries are highly
`dependent on the extent of partial curing, which is difficult to control. After
`patterning, the film must be fully cured. This results in further shrinkage and
`loss of resolution. More importantly, residues left after etching can cause high
`via resistance. In spite of these problems, the economic incentives for a wet etch
`process are significant, and there has been considerable activity in developing
`polyimides or other polymers that can be wet etched. Polyimide fonnulations
`that are designed for a two step patterning process (separate photoresist developer
`and polyimide etchant) have recently been demonstrated to give steep sidewall
`angles and very smooth features. Figure 7-9 shows a 25 IJ1Il wide opening
`etched in a 10 IJ1Il thick film by such a two step process [25],
`Dry Etching. Dry etching processes, such as plasma etching, RIB or RIBE,
`can produce much higher aspect ratio features in polymer films by using charged
`species in a plasma or ion beam to initiate etching in a direction perpendicular
`to the substrate surface. The most common dry etching process is RIB. Substrates
`are placed on the powered electrode sustaining an RF plasma in a gas mixture of
`oxygen and a fluorine containing gas such as CF4, SF6 or CHF3. Because the
`polymer dielectrics etch at nearly the same rate as photoresists, the RIB of thick
`films requires that a masking layer of a slow etching material, such as a metal,
`silicon dioxide or spin-on glass, is deposited and patterned on top of the polymer.
`The full process sequence is shown in the middle column of Figure 7-8.
`Dry etch processes can be used on fully cured polymer ftlms and are less
`sensitive than wet etching to the specific chemistry of the polymer. Very low
`via resistance can be achieved, since the plasma etches any polymer residue at
`the bottom of vias (although metal oxidation or redeposition of materials from
`the RIB mask or chamber must be minimized). RIB processes can pattern high
`aspect ratio vias with nearly vertical sidewalls. More often, process parameters
`are varied to produce a controlled sidewall angle of 70 - 80 degrees from
`horizonal for better metal step coverage. Figure 7-10 shows a via etched by RIB
`in a 25 IJ1Il thick polyimide ftlm, with a sidewall angle of 70 degrees. The main
`drawbacks to the dry etch processes are the high equipment cost and limited
`throughput rates.
`Photosensitive Polyimide. The number of process steps required to pattern
`polyimide films is greatly reduced by using fonnulations that are photosensitive.
`The chemistry of photosensitive polyimides (PSPls) is discussed in Chapter 8.
`Most PSPls are negative acting so that areas exposed to ultraviolet (UV)
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`PROCESSING 287
`
`0682
`
`SKU
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`-
`X2,200
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`10~m WD48
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`Figure 7-9 Ultrade14212® polyimide patterned by spray etching with a specially
`formulated wet etchant. The coating will be 10 /.1m thick when fully cured, and the
`photoresist opening is 25 I.Iffi wide. (Courtesy of H. Neuhaus, Amoco Chemcial
`Company.)
`
`radiation become cross linked and insoluble. The unexposed material is
`dissolved in a developer solution and the patterned film is cured to complete the
`imidization reactions and drive off solvents and crosslinking agents.
`The photopatterning process involves considerably fewer steps, as shown in
`Figure 7-8 and eliminates the need for expensive plasma equipment. However,
`the resolution and aspect ratio of patterned features, particularly via holes, are
`limited by several factors:
`
`1. Developer solutions cause swelling of the crosslinked polymer, which
`can cause a small opening to close or form webs,
`2. There is considerable shrinkage during the final cure (typically 50%
`thickness loss), causing a loss in via aspect ratio, and
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`msgalica@mintz.com
`
`Elm Exhibit 2162, Page 314
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`

`
`288 THIN FILM MULTILAYER INTERCONNECTION TECHNOLOGIES
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`Figure 7·10 Via hole 25 !IDI in diameter etched in a polymide film 25 !IDI thick
`by reactive ion etching.
`
`3. Polyimide and photoinitiators are highly absorbing at UV wavelengths,
`which limits the depth of crosslinking in the film.
`
`During development, the uncrosslinked polymer beneath the crosslinked surface
`layer is dissolved, resulting in an undercut sidewall. This problem may be
`solved by filtering the highly absorbed wavelengths. Thick PSPI films also may
`be patterned by multiple coating and development of thin films. A final concern
`with PSPIs is the poor mechanical properties of the cured films, a result of their
`In spite of these shortcomings, the potential cost
`lower molecular weight.
`advantage offered by PSPI is so great that significant development efforts
`continue. Many Japanese companies manufacturing thin film interconnections
`are using PSPls.
`Laser Etching. A promising future technique for patterning polymer films
`is etching by laser ablat