11111))111
`
`Semiconductor Integrated Circuit
`Processing Technology
`
`W. R. Runyan
`K. E. Bean
`
`Elm Exhibit 2159
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`

`

`SEMICONDUCTOR
`INTEGRATED CIRCUIT
`PROCESSING TECHNOLOGY
`
`W. R. RUNYAN
`Retired, formerly with Texas Instruments
`K. E. BEAN
`Texas Instruments
`
`INDUSTRIAL DESIGN CORPORATION
`USURY
`2020 S.W. 4th
`PORTLAND, OREGON 97201
`
`A
`VT Addison-Wesley Publishing Company
`Reading, Massachusetts • Menlo Park, California • New York
`Don Mills, Ontario • Wokingham, England • Amsterdam • Bonn
`Sydney • Singapore • Tokyo • Madrid • San Juan
`
`Elm Exhibit 2159, Page 2
`
`

`

`This book is in the Addison-Wesley Series in Electrical and Computer
`Engineering
`
`Many of the designations used by manufacturers and sellers to distinguish
`their products are claimed as trademarks. Where those designations
`appear in this book, and Addison-Wesley was aware of a trademark claim,
`the designations have been printed in initial caps or all caps.
`
`This publication is designed to provide accurate and reliable information
`in regard to the subject matter covered. However, responsibility is
`assumed neither for its use nor for any infringement of patterns or rights
`of others which may result from its use.
`
`Cover photos (top to bottom): Courtesy of Bell Laboratories; Courtesy of
`Texas Instruments; Courtesy of Intel Corporation (®Registered trademark
`of Fairchild Semiconductor Corporation); Courtesy of Gordon Teal;
`Courtesy of Texas Instruments Incorporated.
`
`Library of Congress Cataloging-in-Publication Data
`Runyan, W. R.
`Semiconductor integrated circuit processing technology / Walter R.
`Runyan, Kenneth E. Bean.
`p.
`cm.
`Bibliography: p.
`Includes index.
`ISBN 0-201-10831-3
`I. Integrated circuits—Design and construction.
`I. Bean, Kenneth E.
`2. Semiconductors—Design and construction.
`11. Title.
`TK7874.R86 1990
`621.381'73—dc19
`
`89-320
`CIP
`
`Copyright © 1990 by Addison-Wesley Publishing Company, Inc.
`
`All rights reserved. No part of this publication may be reproduced, stored
`in a retrieval system, or transmitted, in any form or by any means,
`electronic, mechanical, photocopying, recording, or otherwise, without
`the prior written permission of the publisher. Printed in the United States
`of America.
`
`ABCDEFGHIJ-DO-89
`
`Elm Exhibit 2159, Page 3
`
`

`

`Foreword
`
`Forty years ago the transistor was hailed as a model of the scientific
`process of invention. Although Shockley's work provided a basic
`understanding of junction transistor structure, little was really
`known about the fabrication processes used for semiconductors.
`Terms such as "deathnium" and "forming" were used to describe
`effects that were not understood. Most of the techniques used were
`crude adaptations of technology developed for other purposes, and
`much of the learning was empirical.
`Today, after many thousands of man-years of effort, the situa-
`tion has changed. New processes have been developed specifically
`for semiconductor use, and others have been carefully optimized.
`By the standards of the 1950s, all are now well understood.
`The authors of this book, Walt Runyan and Ken Bean, have
`been key contributors to this new understanding. Both have been
`actively involved with semiconductors since the beginning; both, in
`the development of new processes and the application of processes
`to high-volume production.
`Today, semiconductor manufacture is truly a science based in-
`dustry. This book provides an excellent summary of the state-of-the-
`art in modern semiconductor processing, both in terms of the sci-
`entific knowledge of the field and in its practical application to
`devices.
`
`J. S. Kilby
`
`iii
`
`Elm Exhibit 2159, Page 4
`
`

`

`Elm Exhibit 2159, Page 5
`
`Elm Exhibit 2159, Page 5
`
`

`

`Preface
`
`The field of semiconductor process engineering is now so broad that
`it is virtually impossible for a single individual to provide process
`engineering support or process development for the complete semi-
`conductor manufacturing operation. Thus, subdivision and special-
`ization are required. However, since each subdivision is intricately
`related to all others, it is absolutely necessary that each technology
`specialist (engineer) have a good understanding of all phases of the
`manufacturing process. This book is intended to provide a unified
`treatment of that portion of the semiconductor manufacturing pro-
`cess commonly referred to as "wafer fabrication."
`The book is to be used as a text by university students and as a
`reference by practicing engineers. It provides background, theory,
`and practical discussions related to the wafer fabrication process. It
`is not, however, a compendium of all of the latest research activities,
`which are constantly changing and continually covered in various
`technical journals and review book series. The serious student,
`whether in industry or university, must keep up-to-date by following
`the current technical journals most closely allied with his or her cho-
`sen specialty.
`The level of presentation in the book assumes that the student
`has had introductory physics, introductory inorganic chemistry,
`mathematics through differential equations, a first course in transis-
`tor device physics, and a course covering electronic material prop-
`erties including crystal structure. All of these courses are generally
`available by the senior year so the text is suitable for either senior-
`or graduate-level courses.
`The book is organized into eleven chapters and three append-
`ices. All chapters have an extensive list of references, and all but
`the first two chapters have problems and a list of key ideas. Since
`silicon remains the semiconductor used for 99 percent of the inte-
`grated circuits, it is naturally emphasized. However, where GaAs
`processing differs substantially from silicon, it is discussed
`separately.
`The first chapter is an historical discussion of the development
`of the integrated circuit. The second chapter gives an overview of
`the processing steps required to manufacture an integrated circuit.
`Chapters 3 through 10 discuss the various technologies required
`for the steps, and each chapter has a section on safety. The chap-
`ter subjects are, respectively, silicon thermal oxidation, deposi-
`tion of thin inorganic films, photolithography, etching, epitaxial
`
`Elm Exhibit 2159, Page 6
`
`

`

`vi
`
`PREFACE
`
`growth, solid state diffusion, ion implantation, and contacts and
`interconnects.
`Chapter II is devoted to a discussion of yields, yield analysis,
`and yield economics. The latter is included because all too often the
`student (and in some cases, practicing engineers as well) lose sight
`of the fact that to be practical for industrial use, semiconductor pro-
`cesses must be economical as well as scientifically feasible. Empha-
`sis is on defect density measurement and interpretation, on the use
`of I—V plots to determine the cause of faulty integrated circuit ele-
`ments, and on how yield and an economical manufacturing opera-
`tion are related.
`The first of three appendices is a review of crystallography as it
`relates to silicon and gallium arsenide. The second is a review of
`phase diagrams, and the third is a compilation of numerical con-
`stants and conversions. Finally, an extensive list of semiconductor-
`related acronyms is given inside the front and back covers of the
`book.
`
`Acknowledgments: Over the course of time spent in preparing this
`book, many people have been very helpful, and in particular, we
`would like to acknowledge Hettie Smith, who typed the manuscript
`and took care of many of the details involved in its preparation, as
`well as Marion Johnson and John Powell, who provided many of the
`photographs. We also want to acknowledge the following people
`who read and commented on various portions of the manuscript:
`Neal Akridge, ATEQ Corp.; Frederick Strieter, Honeywell Corp.;
`Bruce Deal, Advantage Production Technology, Inc.; Howard Huff,
`Sematech; George Brown, Dwayne Carter, Rinn Cleavelin, Monte
`Douglas, P. B. Ghate, John Hatcher, William Keenan, Charlotte
`Tipton, Michael Tipton, Rick Wise, and Richard Yeakley, all of
`Texas Instruments Incorporated; and Isaac Trachtenberg, Chemical
`Engineering Department at the University of Texas. In addition, we
`want to thank the following people for their helpful reviews of the
`manuscript: D. K. Schroder, Arizona State University; John D.
`Shott, Stanford University; Dean P. Neikirk, University of Texas,
`Austin; Arthur B. Glaser, AT&T Bell Laboratories; and Richard C.
`Jaeger, Auburn University.
`We would also like to thank our editor, Tom Robbins, and his
`staff for guidance during the various stages of manuscript prepara-
`tion. Lastly, we wish to express our appreciation for the patience,
`encouragement, and indulgence of our wives, Delma Runyan and
`Helen Bean.
`
`W. R. Runyan
`K. E. Bean
`
`Elm Exhibit 2159, Page 7
`
`

`

`Contents in Brief
`
`CHAPTER 1 Historical Overview
`
`1
`
`CHAPTER 2 Processing Overview
`
`22
`
`CHAPTER 3 Thermal Oxidation of Silicon
`
`53
`
`CHAPTER 4 Definition of Inorganic Thin Films
`
`121
`
`CHAPTER 5 Lithography
`
`161
`
`CHAPTER 6 Etching 242
`
`CHAPTER 7 Epitaxy
`
`294
`
`CHAPTER 8 Impurity Diffusion
`
`371
`
`CHAPTER 9 Ion Implantation
`
`476
`
`CHAPTER 10 Ohmic Contacts, Schottky Barriers, and Interconnects
`
`518
`
`CHAPTER 11 Yields and Yield Analysis
`
`579
`
`APPENDIX A Crystallography
`
`APPENDIX B Phase Diagrams
`
`645
`
`661
`
`APPENDIX C Reference Tables
`
`670
`
`Index
`
`673
`
`vii
`
`Elm Exhibit 2159, Page 8
`
`

`

`i
`
`Elm Exhibit 2159, Page 9
`
`Elm Exhibit 2159, Page 9
`
`

`

`Detailed Contents
`
`CHAPTER 1 Historical Overview
`
`I
`
`1.1 Background I
`1.2 The Transistor
`2
`1.3 The Integrated Circuit
`1.4 Semiconductor Processes
`References
`20
`
`8
`
`17
`
`CHAPTER 2 Processing Overview
`
`22
`
`2.1 Introduction 22
`2.2 Wafer Fabrication Facility
`2.3 Wafer Fabrication Operations
`2.3.1 Surface Cleaning
`34
`2.3.2 Epitaxy 34
`2.3.3 Thermal Oxidation of Silicon
`2.3.4 Diffusion 35
`2.3.5 Ion Implantation
`2.3.6 Lithography 36
`2.3.7 Etching 38
`2.3.8 Chemical Vapor Deposition (CVD)
`38
`2.3.9 Metal Deposition
`2.3.10 Metal (Contact) Sintering
`39
`2.3.11 Backgrinding
`2.3.12 Multiprobing
`39
`40
`Integrated Circuit Fabrication
`2.4.1 Components and Component Construction
`46
`2.4.2 Steps in IC Fabrication
`
`31
`
`33
`
`35
`
`36
`
`38
`
`39
`
`2.4
`
`40
`
`CHAPTER 3 Thermal Oxidation of Silicon
`
`53
`
`57
`
`3.1 Introduction 53
`3.2 Structure 55
`3.3 Nonelectrical Properties
`57
`3.3.1 Density
`3.3.2 Expansion Coefficient
`60
`3.3.3 Optical Properties
`61
`3.3.4 Chemical Properties
`63
`3.4 Electrical Properties
`3.4.1 Bulk Electrical Conduction
`3.4.2 Surface Electrical Conductivity
`3.4.3 Dielectric Breakdown Strength
`
`59
`
`63
`
`65
`67
`
`ix
`
`Elm Exhibit 2159, Page 10
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`

`

`x
`
`DETAILED CONTENTS
`
`69
`
`79
`
`3.4.4 Mobile Ion Transport
`72
`3.4.5 Interface Charges
`76
`3.5 Kinetics of Oxidation
`77
`3.5.1 Deal—Grove Model
`3.5.2 Initial Stage of Oxidation
`3.5.3 Reaction Path
`81
`81
`3.5.4 Determination of Rate Constants
`83
`3.5.5 Calculation of Oxide Thickness
`3.5.6 Temperature Behavior of Rate Constants
`3.5.7 Effect of Crystal Orientation on Rate
`88
`3.5.8 Polycrystalline Silicon Oxidation
`90
`3.5.9 Effect of Pressure on Oxidation
`3.5.10 Effect of Ambient Impurities on Oxidation Rate
`3.5.11 Effect of Silicon Doping on Oxidation Rate
`91
`3.5.12 Impurity Profile at the Oxide Interface
`96
`3.6 Oxide Thickness Charts
`98
`3.7
`Preparation of Thermal Oxide
`3.7.1 Preoxidation Surface Cleanup
`3.7.2 Atmospheric Pressure Equipment
`3.7.3 High-Pressure Oxidation Processing
`107
`3.7.4 High-Pressure Equipment
`108
`3.7.5 Selective Oxidation
`3.7.6 Two- and Three-Dimensional Oxidation
`1 1 1
`3.7.7 Oxide Physical Defects
`3.7.8 Defects Generated in Silicon During Oxidation
`Key Ideas
`113
`113
`Problems
`114
`References
`
`83
`
`84
`
`99
`99
`
`104
`107
`
`110
`
`90
`
`112
`
`CHAPTER 4 Deposition of Inorganic Thin Films
`
`121
`
`124
`
`4.1 Introduction 121
`4.2 Sputter Deposition
`4.3 Evaporation 126
`128
`Ion Beam Deposition
`4.4
`129
`4.5 Chemical Vapor Deposition
`4.5.1 Atmospheric Pressure and Low-Pressure Depositions
`137
`4.5.2 Plasma-Enhanced CVD
`139
`4.5.3 Photon-Enhanced CVD
`4.6 Deposition of Specific Materials
`140
`4.6.1 CVD Silicon Dioxide
`142
`4.6.2 Plasma Silicon Dioxide
`143
`4.6.3 Doped Silicon Oxide
`145
`4.6.4 CVD Silicon Nitride
`147
`4.6.5 Plasma Silicon Nitride
`4.6.6 APCVD and LPCVD Polysilicon
`151
`4.6.7 Plasma Polysilicon
`
`140
`
`148
`
`130
`
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`

`

`DETAILED CONTENTS
`
`xi
`
`151
`
`4.7 Other CVD Film Materials
`152
`4.8 Spin-On Glasses
`4.9 Glass Fritting
`153
`154
`Safety
`Key Ideas
`Problems
`References
`
`156
`156
`157
`
`CHAPTER 5 Lithography
`
`161
`
`161
`Introduction
`5. I
`5.2 Photomasks 161
`5.2.1 Masks for Optical Printing
`164
`5.2.2 X-Ray Masks
`165
`5.2.3 Mask Protection
`166
`5.3 Mask Defects
`167
`5.3.1 Mask Inspection
`5.3.2 Mask—Wafer Overlay Accuracy
`5.3.3 Overlay Accuracy Measurements
`5.4 Photoresists 172
`175
`5.4.1 UV Negative Resist Formulation
`175
`5.4.2 UV Positive Resist Formulation
`5.4.3 E-Beam, X-Ray, and Ion Beam Resists
`177
`5.4.4 Inorganic Resists
`5.4.5 Plasma-Developable Resists
`178
`5.4.6 Resist Contrast
`182
`5.4.7 Sensitivity
`183
`5.4.8 Reciprocity
`5.4.9 Etch Resistance
`184
`Resist Processing Flow
`5.5.1 Adhesion Promoters and Adhesion
`186
`5.5.2 Resist Application
`5.5.3 Soft-, Postexpose-, and Hard-Bake
`189
`5.5.4 Developing
`5.5.5 Resist Removal
`190
`Light Sources
`190
`5.6.1 Arc Sources
`192
`5.6.2 Excimer Lasers
`192
`Contact Printing
`193
`Optical Proximity Printing
`Fundamental Optical Limitations of Projection Printing
`195
`5.9.1 Resolution
`198
`5.9.2 Depth of Focus
`5.9.3 Variation in Position of Best Focus
`200
`5.10 Full-Wafer Projection Printing
`5.10.1 Operation
`201
`
`184
`
`189
`
`5.5
`
`5.6
`
`5.7
`5.8
`5.9
`
`161
`
`169
`171
`
`176
`
`177
`
`184
`
`189
`
`198
`
`195
`
`Elm Exhibit 2159, Page 12
`
`

`

`xii
`
`DETAILED CONTENTS
`
`202
`
`210
`210
`
`212
`
`217
`
`227
`
`215
`
`234
`
`5.10.2 Focusing Accuracy
`202
`5.10.3 Registration
`204
`5.11 Stepper Printing
`204
`5.11.1 Focus
`206
`5.11.2 Alignment
`207
`5.11.3 Registration
`208
`5.11.4 Throughput
`5.12 Electron Beam Printing
`5.12.1 Pattern Generation
`210
`5.12.2 Resolution
`211
`5.12.3 Alignment
`211
`5.13 X-Ray Printing
`5.13.1 Image Distortion
`212
`5.13.2 Resolution
`214
`5.13.3 X-Ray Sources
`214
`5.13.4 X-Ray Steppers
`215
`5.14 Ion Beam Printing
`215
`5.14.1 Focused Ion Beams
`5.14.2 Masked Ion Beam Printing
`215
`5.15 Printer Selection
`216
`5.16 Line-Width Control
`5.16.1 Process-Initiated Control Problems
`224
`5.16.2 Interference Effects
`5.16.3 Minimizing Effect of Standing Waves
`228
`5.16.4 Resist over Steps
`228
`5.16.5 Multilayer Resist
`231
`5.17 Wafer Flatness
`5.18 Lithography Process Modeling
`235
`Safety
`Key Ideas
`Problems
`References
`
`236
`237
`237
`
`CHAPTER 6 Etching 242
`
`6.1
`Introduction 242
`245
`6.2 Wet Etching
`247
`6.2.1 Etch Formulation
`249
`6.2.2 Nonselective Silicon Etching
`251
`6.2.3 Polycrystalline Silicon Etching
`252
`6.2.4 Anisotropic Silicon Etching
`6.2.5 Resistivity-Sensitive Silicon Etching
`258
`6.2.6 Electrolytic Silicon Etching
`6.2.7 Silicon Staining
`259
`6.2.8 Gallium Arsenide Etching (General)
`6.2.9 Gallium Arsenide Etching (Anisotropic)
`263
`6.2.10 Preferential Etches
`
`256
`
`259
`261
`
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`

`

`DETAILED CONTENTS
`
`xiii
`
`6.3
`
`264
`267
`
`283
`284
`284
`285
`
`273
`278
`
`6.2.11 Silicon Dioxide Etching
`6.2.12 Silicon Nitride Etching
`6.2.13 Metal Etching
`268
`Plasma Etching
`269
`6.3.1 Etching Reactions
`6.3.2 Plasma Etch Rates
`6.3.3 Selectivity
`280
`282
`6.3.4 End-Point Detection
`6.3.5 Effect of Loading on Etch Rate
`6.3.6 Effect of Electrode Material
`6.3.7 Plasma-Induced Damage
`6.3.8 Plasma Etching Equipment
`6.4 Vapor Phase Etching
`287
`Safety
`287
`Key Ideas
`288
`Problems
`289
`References
`289
`
`CHAPTER 7 Epitaxy 294
`
`297
`
`7.1 Introduction 294
`7.2 Vapor Phase Epitaxy
`7.2.1 Nucleation
`297
`306
`7.2.2 Surface Reactions
`308
`7.2.3 Material Transport
`309
`7.3 Vapor Phase Silicon Epitaxy
`7.3.1 Surface Cleaning and Vapor Phase Etching
`313
`7.3.2 Deposition Reactions
`315
`7.3.3 Deposition Rates
`7.3.4 Effect of Orientation on Deposition Rate
`323
`7.3.5 Layer Doping
`7.3.6 Impurity Redistribution during Epitaxy
`328
`7.3.7 Pattern Shift and Distortion
`332
`7.3.8 Selective Epitaxial Growth (SEG)
`7.3.9 Equipment for Silicon Vapor Phase Epitaxy
`342
`7.3.10 Molecular Beam Epitaxy (MBE)
`344
`7.3.11 Defects Introduced during Growth
`349
`7.4 Vapor Phase Gallium Arsenide Epitaxy
`7.4.1 Halide Transport
`349
`7.4.2 Metalorganic Source CVD (MOCVD)
`351
`7.4.3 GaAs Molecular Beam Epitaxy
`352
`7.5 Liquid Phase Epitaxy
`7.5.1 Silicon LPE
`353
`7.5.2 GaAs LPE
`355
`7.6 Epitaxial Crystal Growth from a Solid
`7.7 Crystal Growth over Insulating Substrates
`Safety
`360
`
`309
`
`321
`
`324
`
`338
`
`350
`
`356
`
`357
`
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`

`

`xiv
`
`DETAILED CONTENTS
`
`Key Ideas
`Problems
`References
`
`360
`361
`362
`
`CHAPTER 8 Impurity Diffusion
`
`371
`
`8.1
`8.2
`
`8.3
`
`8.4
`
`8.5
`
`8.6
`
`406
`407
`
`411
`
`418
`
`414
`
`421
`
`424
`
`374
`
`378
`379
`
`383
`
`398
`
`401
`
`390
`392
`394
`395
`
`371
`Introduction
`Atomic Diffusion Mechanisms
`8.2.1 Diffusion by Vacancies
`8.2.2 Diffusion by Interstitialcy
`380
`8.2.3 Interstitial Diffusion
`381
`8.2.4 Electric-Field-Aided Diffusion
`8.2.5 Effect of Thermal Oxidation on the Diffusion Coefficient
`384
`8.2.6 Effect of Diffusing Direction (Orientation)
`385
`8.2.7 Effect of Heavy Doping
`8.2.8 Effect of Temperature
`386
`8.2.9 Effect of Stress/Strain
`386
`388
`8.2.10 Emitter Push, Pull, and Dip
`388
`Solutions to the Diffusion Equations
`8.3.1 Diffusion from Infinite Source on Surface
`8.3.2 Diffusion from Limited Source on Surface
`8.3.3 Diffusion from Interior Limited Source
`8.3.4 Diffusion from Layer of Finite Thickness
`397
`8.3.5 Diffusion from Concentration Step
`8.3.6 Diffusion from Concentration Step into Moving Layer
`401
`8.3.7 Out-Diffusion with Rate Limiting at Surface
`8.3.8 Diffusion from a Fixed Concentration into Moving Layer
`402
`8.3.9 Diffusion through Thin Layer
`404
`8.3.10 Diffusion during Thermal Oxidation
`8.3.11 Diffusion from Infinite Source into Finite Thickness
`8.3.12 Two-Dimensional Diffusion from High-Diffusivity Path
`409
`8.3.13 Two-Dimensional Solutions
`8.3.14 Effect of Temperature Varying with Time
`412
`Diffusion Profile Calculations
`8.4.1 Phosphorus Profile
`414
`8.4.2 Silicon Interstitial Diffusants
`416
`8.4.3 Gallium Arsenide Profile
`416
`8.4.4 Solid Solubility Data
`418
`Diffusion Characterization
`8.5.1 Conversion from Dopant Concentration to Resistivity
`419
`8.5.2 Sheet Resistance Measurement
`8.5.3 Determination of N„
`420
`8.5.4 Junction Depth Measurement
`8.5.5 Profile Measurement
`422
`8.5.6 Determination of Diffusion Coefficient
`Diffusion Processes
`428
`8.6.1 Depth
`428
`
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`

`DETAILED CONTENTS
`
`xv
`
`442
`
`452
`
`454
`
`462
`
`8.7
`
`8.8
`
`8.9
`
`428
`
`453
`
`461
`461
`
`8.6.2 Surface Concentration
`8.6.3 Lifetime Control
`429
`8.6.4 Gettering of Silicon
`431
`440
`Diffusion-Induced Defects
`441
`8.7.1 Diffusion Flaws and Pipes
`8.7.2 Lifetime-Reducing Impurities and Precipitates
`8.7.3 Strain-Induced Dislocations
`443
`8.7.4 Permanent Wafer Warpage
`446
`Diffusion Equipment
`451
`8.8.1 Gas Flow Measurement and Control
`8.8.2 Diffusion Tubes
`453
`8.8.3 Wafer Diffusion Boats
`8.8.4 Wafer Insertion
`454
`8.8.5 Computer Control of Tube Functions
`Diffusion Sources
`456
`458
`8.9.1 Liquid Sources
`8.9.2 Gaseous Sources
`459
`460
`8.9.3 Planar Sources
`8.9.4 Doped Oxide Sources
`8.9.5 Closed-Tube Sources
`8.10 The Error Function
`462
`462
`8.10.1 Error Function Algebra
`8.10.2 Calculation of Error Function Values
`Safety
`465
`466
`Key Ideas
`Problems
`467
`468
`References
`
`CHAPTER 9 Ion Implantation
`
`476
`
`9.3
`
`486
`
`491
`
`9.1 Introduction 476
`478
`9.2
`Implant Depth (Range)
`478
`9.2.1 Range Calculations
`481
`9.2.2 Range Dispersion
`9.2.3 Lateral Range Dispersion
`487
`9.2.4 Channeling
`9.2.5 Implanting through Layers
`494
`Implant-Induced Defects
`495
`9.3.1 Lattice Damage
`497
`9.3.2 Annealing
`9.4 Applications 499
`9.4.1 MOS Threshold Adjust
`9.4.2 Self-Aligned MOS Gate
`9.4.3 Polysilicon Doping
`503
`504
`9.4.4 Alternative to Diffusion Predep
`9.4.5 Ion Beam Mixing and Ion Beam Damage
`9.4.6 Formation of Buried Layers
`505
`
`501
`502
`
`504
`
`Elm Exhibit 2159, Page 16
`
`

`

`xvi
`
`DETAILED CONTENTS
`
`9.5
`
`505
`
`Ion Implant Equipment
`507
`9.5.1 Ion Sources
`509
`9.5.2 Ion Analyzer
`510
`9.5.3 Wafer Handling
`511
`9.5.4 Wafer Contamination
`9.5.5 Implant Uniformity Measurements
`513
`Safety
`Key Ideas
`Problems
`References
`
`514
`514
`515
`
`512
`
`CHAPTER 10 Ohmic Contacts, Schottky Barriers, and Interconnects
`
`518
`
`10.1
`10.2
`
`10.3
`
`10.4
`
`10.7
`10.8
`
`10.9
`
`528
`535
`
`544
`
`552
`
`560
`
`518
`Introduction
`520
`Ohmic Contacts
`520
`10.2.1 Spreading Resistance
`522
`10.2.2 Contact Resistance
`527
`10.2.3 Total Contact Resistance
`10.2.4 The Aluminum—Silicon Ohmic Contact
`10.2.5 The Silicide—Silicon Ohmic Contact
`538
`10.2.6 Alloyed GaAs Ohmic Contacts
`538
`10.2.7 Nonalloyed GaAs Ohmic Contacts
`539
`10.2.8 Measurement of Contact Resistance
`541
`Schottky Diodes
`541
`10.3.1 Rectifying Schottky Barriers
`10.3.2 Choice of Metal for Schottky Barriers
`544
`Leads (Interconnects)
`545
`10.4.1 Lead Resistance
`549
`10.4.2 Adhesion to SiO,
`550
`10.4.3 Diffusion Barrier
`10.4.4 Interconnect Material Contamination
`552
`10.4.5 Step Coverage
`10.4.6 Protective Overcoats
`556
`10.5 MOS Gate Materials
`558
`10.6 Multilevel Metallization
`558
`10.6.1 Interlevel Shorts
`559
`10.6.2 Planarization
`Interconnect and Gate Metal Pattern Definition
`560
`Failure Modes
`10.8.1 Electromigration
`564
`10.8.2 Corrosion
`10.8.3 Internal Stresses
`Deposition Methods
`10.9.1 Surface Cleanup
`10.9.2 Metal Evaporation
`567
`10.9.3 Sputtering
`10.9.4 Chemical Vapor Deposition
`
`555
`
`561
`
`565
`565
`566
`566
`
`568
`
`Elm Exhibit 2159, Page 17
`
`

`

`DETAILED CONTENTS
`
`xvii
`
`570
`10.10 Process Control
`570
`10.10.1 Resistivity Ratio
`571
`10.10.2 Current Capacity
`571
`10.10.3 Lead Adherence
`10.10.4 Process Problems Requiring Test Patterns for Detection
`572
`Safety
`Key Ideas
`Problems
`References
`
`572
`573
`574
`
`572
`
`CHAPTER 11 Yields and Yield Analysis
`
`579
`
`579
`
`581
`
`583
`
`585
`
`601
`
`604
`
`599
`
`611
`
`Introduction
`11.1
`579
`Yield Definitions
`11.2
`11.3 Methods of Yield Measurement
`11.3.1 The Curve Tracer
`582
`11.3.2 Automatic Multiprobe Testing
`Yield Tracking
`585
`11.4.1 Process and Multiprobe Yield Tracking
`585
`11.4.2 Split Lot Testing
`Defect Density
`588
`11.5.1 Theory
`590
`596
`11.5.2 Defect Density Determination
`Chip Yield Predictions Based on Defect Density
`599
`11.6.1 New Devices
`11.6.2 New IC Designs with New Processes
`602
`11.6.3 Devices in Production
`11.6.4 Work in Progress
`603
`11.6.5 When Yield is Low
`603
`Determining Causes of Chip Yield Loss
`605
`Junction Testing
`606
`11.8.1 Reverse-Biased pn Junctions
`11.8.2 Reverse Current Curve Tracer Diagnostics
`11.8.3 Reverse-Biased Schottky Junctions
`616
`617
`11.8.4 Forward-Biased pn Junctions
`11.9 MOS Transistor Testing
`621
`11.9.1 Threshold Voltage
`621
`11.9.2 Subthreshold Leakage Current
`11.9.3 Pinchoff Voltage
`624
`11.9.4 Conduction Factors k and k'
`11.9.5 Channel Mobility
`626
`11.9.6 Drain Breakdown Voltage
`11.10 Bipolar Transistor Diagnostics
`11.10.1 Current Gain
`627
`11.10.2 Reverse Breakdown Voltages
`11.10.3 Reverse and Forward Currents
`
`11.4
`
`11.5
`
`11.6
`
`11.7
`11.8
`
`624
`
`624
`
`626
`626
`
`630
`633
`
`Elm Exhibit 2159, Page 18
`
`

`

`xviii
`
`DETAILED CONTENTS
`
`634
`11.11 Yield Economics
`635
`11.11.1 Silicon Usage
`636
`11.11.2 Wafer Cost
`637
`11.11.3 Wafer Diameter
`11.11.4 Effect of Chip Size on Yield and Cost
`639
`11.11.5 Revenue from Wafers
`11.12 Factors Affecting Yield and Yield Improvement
`Key Ideas
`642
`642
`Problems
`References
`643
`
`638
`
`640
`
`APPENDIX A Crystallography
`
`645
`
`A.1 Silicon and Gallium Arsenide Structure
`654
`A.2 Crystallographic Defects
`659
`References
`
`645
`
`APPENDIX B Phase Diagrams 661
`
`B.1 Binary Phase Diagrams
`B.2 Ternary Phase Diagrams
`669
`References
`
`661
`667
`
`APPENDIX C Reference Tables
`
`670
`
`Index
`
`673
`
`Elm Exhibit 2159, Page 19
`
`

`

`CHAPTER
`
`1
`
`.o
`
`•
`•
`it
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`4
`•
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`4 * e r • 0
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`6 •
`• a
`6 a
`t.
`6 6
`a
`a a
`*
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`R • •6
`*
`I • • • •
`• • • • • •
`• • • • • 3
`
`1.1
`BACKGROUND
`
`Historical Overview
`
`The semiconductor technology that ultimately led to the integrated
`circuit (IC) was over 75 years in the making.' Around 1875, it was
`observed that selenium exhibited rectification and photoconductiv-
`ity. A silicon diode of sorts for detecting radio waves was described
`in 1906 (1). By 1935, selenium rectifiers and photodetectors, silicon
`carbide varistors, and galena (naturally occurring lead sulfide) and
`silicon point contact diodes for radio detection were on the market
`(2). Also in 1935, a British patent was issued, but was never reduced
`to practice, for a thin-film field effect transistor (3).
`The development of radar just prior to and during World War II
`placed a great deal of emphasis on the study of silicon (Si) and ger-
`manium (Ge) since they were singled out as the most appropriate
`materials for the mixer and detector diodes required in the radar
`detection circuitry. Because of this activity, commercial sources of
`high-purity silicon and germanium were developed. Professor Lark-
`Horovitz of Purdue University prevailed on Eagle-Pitcher Mining
`and Smelting Company to develop a high-purity germanium supply,
`which they did, based on extraction from the lead and zinc ores
`mined in the tri-state area of Kansas, Missouri, and Oklahoma.
`(This was the only known significant source of germanium ore in the
`Western Hemisphere.) During the same period, Professor Seitz of
`the University of Pennsylvania initiated a program at DuPont to pro-
`duce high-purity silicon (4).
`
`' The few events and names mentioned in this section should neither be construed
`as representing the total semiconductor activity in that period nor as even neces-
`sarily being the most significant. They were chosen to give some idea of progress
`as a function of time, and in fact, a large number of people, both in industry and
`in the universities, contributed to the development. To single out a few names and
`places may seem unfair, but to do otherwise would turn a processing technology
`text into a volume of semiconductor history. (For more definitive information, see
`reference 2 and the first 85 references contained therein.)
`
`1
`
`Elm Exhibit 2159, Page 20
`
`

`

`CHAPTER 1 HISTORICAL OVERVIEW
`
`2
`1.2
`THE TRANSISTOR
`
`William Shockley (seated at the
`microscope), John Bardeen (at
`left), and Walter Brattain, all of
`Bell Telephone Laboratories, are
`pictured here about the time of
`their discovery of the point con-
`tact transistor in 1947. This work
`resulted in their receiving the No-
`bel Prize for Physics in 1956.
`(Source: Photograph courtesy of
`AT&T Archives.)
`
`In December of 1947, the first transistor (a point contact structure)
`was constructed by John Bardeen and Walter Brattain of Bell Tele-
`phone Laboratories. For a discussion of the events leading up to that
`occasion and of the subsequent work that led to the junction tran-
`sistor (and to the Nobel Prize in physics for Bardeen, Brattain, and
`Shockley), see Shockley's paper "The Path to the Conception of the
`Junction Transistor," IEEE Trans. on Electron Dev. ED-23.
`The first point contact transistor used polycrystalline germa-
`nium for the semiconducting material. However, when the first pa-
`per describing the transistor was submitted for publication (June 25,
`1948), the transistor effect had been demonstrated in silicon as well
`(5). By the end of 1949, single-crystalline rather than polycrystalline
`material was being used (2). This conversion from polycrystalline to
`single-crystal source material (spearheaded by Gordon Teal of Bell
`Telephone Laboratories) has been one of the most significant ad-
`vances in semiconductor technology since the invention of the tran-
`sistor itself. Without a source of large single crystals with uniform
`properties, the high-volume production of small devices would have
`been difficult and development of large-area integrated circuits
`impossible.
`Efforts to build useful structures using polycrystalline or amor-
`phous material thus far have had only spotty success. Amorphous
`silicon solar cells are now commercially feasible, and diodes utilized
`as fuses for programming are sometimes built into polycrystalline
`silicon integrated circuit leads. However, in all cases, single-crystal
`devices outperform comparable devices made in amorphous or
`polycrystalline material.
`Although the point contact transistors were expensive and un-
`reliable, they were, overall, superior in many respects to vacuum
`tubes.' Consequently, they went into production at Western Elec-
`tric's Allentown plant in 1951 as replacements for vacuum tubes in
`some telephone exchange applications. However, by the time the
`transistor process was licensed to other manufacturers in 1952, Wil-
`liam Shockley had invented the grown junction transistor, and Gor-
`don Teal and Morgan Sparks had reduced it to practice (6). This
`transistor became the industry workhorse for several years. It dif-
`fered from all subsequent transistor structures in that junction for-
`
`John Bardeen, co-inventor of the
`point contact transistor, received
`a second Nobel Prize in physics
`in 1972 for his work on the theory
`of superconductivity. (Source:
`Photograph courtesy of AT&T
`Archives.)
`
`' Early guided missiles often used magnetic amplifiers instead of vacuum tubes in
`their control systems because of reliability considerations. The point contact tran-
`sistor, which in retrospect appears to have been a very fragile and unreliable struc-
`ture, was in fact good enough to replace the magnetic amplifiers and greatly im-
`prove the frequency response of the control systems.
`
`Elm Exhibit 2159, Page 21
`
`

`

`1.2 THE TRANSISTOR
`
`3
`
`FIGURE 1.1
`
`n-emitter region (heavily doped)
`
`Construction details of a sili-
`con grown junction transistor.
`(Germanium transistors were
`pnp and used gold wire for the
`base contact.)
`
`n-collector region
`
`p-base region
`
`Walter Brattain was a co-inventor
`of the point contact transistor.
`(Source: Photograph courtesy of
`AT&T Archives.)
`
`(a) Crystal cut in half for
`evaluation
`
`allIMIIM1111111.41
`INOillOPP
`
`(c) Section cut into "bars" (size,
`varying with power rating of
`transistor, but typically 30x
`30x150 mils)
`
`(b) Section cut from mid-region
`of crystal that contains base
`layer and small section each
`of collector and emitter
`regions
`
`Aluminum wire
`
`Base
`(d) Base contact formed by fusing
`(alloying) aluminum wire to
`silicon so that wire made
`ohmic contact to base region
`and rectifying contacts to
`collector and emitter
`
`mation was completed during the crystal-growing operation. Fig. 1.1
`shows the construction details of a silicon grown junction transistor.
`The remainder of the manufacturing steps were to affix leads, pack-
`age, and test. Fig. 1.2 shows a transistor bar3 mounted in a header.
`All that remained to be done here was to add a cover and final-test.
`Even though both silicon and germanium were demonstrated at
`the beginning to be usable for transistors, germanium was much
`more tractable, and silicon transistors (desirable for their higher-
`temperature capability) did not become commercially available until
`
`William Shockley, co-inventor of
`the point contact transistor, was
`also the inventor of the junction
`transistor. (Source: Photograph cour-
`tesy of AT&T Archives.)
`
`As can be seen from Fig. 1.2, the bit of silicon used in each transistor really did
`look like a bar. For people and companies that worked extensively with grown
`junctions, the term bur became so deeply rooted that over 30 years later integrated
`circuits 1 cm on a side and 0.5 mm thick may still be called bars. Those whose
`experience started with alloyed or diffused units used the terms chip or die, which
`today are still common expressions.
`
`Elm Exhibit 2159, Page 22
`
`

`

`4
`
`CHAPTER 1 HISTORICAL OVERVIEW
`
`FIGURE 1.2
`
`Grown junction transistor bar
`mounted in a header. (The col-
`lector and emitter connections
`support the bar; the fine wire is
`the base connection.)
`
`1954 when grown junction silicon transistors were introduced by
`Texas Instruments Incorporated (7).
`Alloyed junction germanium transistors were reported by Saby
`of General Electric in 1951 during the same meeting at which the
`grown junction transistor was first openly discussed (8). These tran-
`sistors were made by alloying a dot of metal, usually indium, into
`each side of a chip of germanium, as shown in Fig. 1.3. A pn junc-
`tion formed at each alloy—germanium interface and provided the col-
`lector—base and emitter—base junctions, respectively. Germanium
`alloyed transistors were very successful and became an al