i
`
`United States Patent [191
`Leedy
`
`4,924,589
`[11] Patent Number:
`[45] Date of Patent: May 15, 1990
`
`[54] METHOD OF MAKING AND TESTING AN
`INIEGRA'I‘ED CIRCUIT
`
`[76] Inventor: Glenn J. Leedy, 1061 E. Mountain
`Dr" Santa Barbara’ Cahf' 93108
`
`[21] Appl' No‘: 194’596
`[22] Filed:
`May 16,1988
`
`-
`
`OTHER PUBLICATIONS
`IBM Tech. Discl. Bull., vol. 10, No. 10, Mar. 1968, pp.
`1466-1467 by Dill et al.
`Primary Examiner—Carl J. Arbes
`Attorney, Agent, or Firm—Skjerven, Morrill,
`MacPherson, Franklin & Friel
`1571
`ABSTRACT
`Each transistor or logic unit on an integrated circuit
`wafer is tested prior to interconnect metallization_
`CAD means, the transistor or logic units placement net
`list is revised to substitute redundant defect-free logic
`units for defective ones. Then the interconnect metalli
`zation is laid down and patterned under control of a
`CAD means. Each die in the wafer thus has its own
`interconnect scheme, although each die is functionally
`equivalent, and yields are much higher than with con
`ventional testing at the completed circuit level.
`The individual transistor or logic unit testing is accom
`plished by a specially fabricated ?exible tester surface
`made in one embodiment of several layers of ?exible
`silicon dioxide, each layer containing vias and conduc
`tive traces leading to thousands of microscopic metal
`probe points on one side of the test surface. The probe
`points electrically contact the contacts on the wafer
`under test by ?uid pressure. The tester surfaces traces
`are then connected, by means of multiplexers, to a con
`ventional tester signal processor.
`
`20 Claims, 16 Drawing Sheets
`
`[5
`
`
`
`GL5 ............................................. .. US. Cl. ...................................... -
`
`407;
`29/346
`[531 Field of Search --------------------- -- 437/8; 324/73 PC;
`29/346, 332, 407, 593
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,405,361 l0/l968
`3,618,201 11/1971
`3,702,025 11/1972
`3,762,037 10/ 1973
`3,781,670 12/1973
`3,795,972 3/1974
`3,795,975 3/1974
`3,835,530 9/1974
`3,969,670 7/1976
`3,993,934 11/1976
`4,573,008 2/1986
`4,590,422 5/1986
`4,617,730 10/1986
`4,715,928 12/1987
`
`Kattner et al. .
`Makirnoto et al. ................... .. 437/8
`Archer ............... ..
`437/8
`Baker et al. ................... .. 437/ 8
`McMahon, Jr. .
`324/73 PC X
`Calhoun ........................ .. 437/8
`Calhoun et al. ..
`437/ 8
`Kilby . .
`. 4.37/8
`Wu ...... ..
`437/8 X
`Baker et
`...................... .. 437/8 X
`Lischke
`Milligan .
`Geldermans et al. .
`Hamby .
`
`Elm Exhibit 2135
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00387
`
`

`

`US. Patent May 15,1990
`
`Sheet 1 of6
`
`4,924,589“ 1
`
`TESTER CONNECTION ARRAY
`
`TESTER CONNECTION ARRAY
`r—-’—w
`
`FIG. 2
`
`17-1
`
`17-2
`
`17-3
`
`22
`23
`24
`
`Elm Exhibit 2135, Page 2
`
`

`

`US. Patent May 15,1990
`
`Sheet 2 of6
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`4,924,589
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`

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`US. Patent
`
`‘May 15, 1990
`
`Sheet 3 0f 6
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`4,924,589 .
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`Elm Exhibit 2135, Page 4
`
`

`

`US. Patent May 15,1990
`
`Sheet 4 of6
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`4,924,589
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`

`

`US. Patent May 15,1990
`
`120-1
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`
`Sheet 5 0f6
`4,924,589 ‘ '
`120-2; /118
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`
`Elm Exhibit 2135, Page 6
`
`

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`
`May 15, 1990
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`

`

`4,924,589
`2
`Another object is to permit the fabrication of very
`large integrated circuits, in terms of number of ICLUs
`or devices per circuit.
`The present invention improves on prior art by test
`ing each ICLU prior to metallization. Redundant
`UCLUs are provided on the die to substitute for those
`found to have defects. Then the metallization layers are
`fabricated so as to exclude defective ICLUs and substi
`tute good ones from the redundant group and render
`the circuit operable. The present invention uses a ?ne
`grain testing approach, by testing at a low level of com
`plexity.
`One key to the present invention is a specially fabri
`cated ?exible test means made of ?exible silicon dioxide
`in one embodiment and including multi-layer metal
`interconnects and microscopic test points. The ?exible
`tester means includes a tester surface, connected to test
`equipment, that permits testing of each device. Then by
`CAD (computer aided design) means, each die is metal
`lized and the metal layer is patterned by suitable means,
`such as E-beam ‘processing, to fabricate discretionary
`metallization interconnect layers of individual gate
`array devices.
`The tester surface is formed on a standard silicon
`wafer typically by means of a low stress chemical vapor
`deposition process. The tester surface includes its own
`metallization layers. On one side of the tester surface are
`thousands of probe points to contact the contact points
`on the wafer under test. The tester surface is a special
`?exible form of silicon dioxide which can be pressed
`?exibly against the wafer under test to achieve good
`electrical contact.
`By eliminating defects at the device level, process
`yield is vastly increased-—for example to about 90%
`regardless of die size, in contrast to much lower yields
`using prior art technology. The present invention also
`allows successful fabrication of very large die compared
`to conventional technology.
`
`5
`
`20
`
`30
`
`35
`
`1
`
`METHOD OF MAKING AND TESTING AN
`INTEGRATED CIRCUIT
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to a method of making and
`testing integrated circuits, and a device used to perform
`such testing.
`2. Description of the Prior Art
`Integrated circuits (ICs) comprise active and passive
`elements such as transistors, diodes, resistors, and ca
`pacitors, that are interconnected in a predetermined
`pattern to perform desired functions. The interconnec
`tions are effectuated by means of metallization layers
`and vias. A “via” is a hole through an insulation layer in
`which conductor material is located to electrically in
`terconnect one conductive layer to another or to an
`active or passive region in the underlying semiconduc
`tor substrate. Present day technology generally em
`ploys two metallization layers that are superimposed
`over the semiconductor wafer structure. Integrated
`circuits and assemblies have become more complex
`with time and in a logic circuit, the number of inte
`grated circuit logic units (ICLUs) and interconnects on
`a given size die have been substantially increased re
`?ecting improved semiconductor processing technol
`ogy. An ICLU can be a device (such as a transistor), a
`gate (several transistors) or as many as 25 or more tran
`sistors and other devices.
`Standard processing to make logic structures (i.e.,
`gate arrays) includes ?r fabricating as many as half a
`million transistors comprising a quarter of a million
`gates per die. Each semiconductor wafer (typically
`silicon but sometimes of other material such as gallium
`arsenide) includes many die, for example, several hun
`dred. In one type of gate array,‘ for example, the transis
`tors are arrayed in rows and columns on each die, and
`each transistor is provided with conductive contact
`points (typically metal but sometimes formed of other
`conductive material such as polycrystalline silicon),
`also arrayed in rows and columns.
`As is well known in the art, these conductive contact
`points have a typical center-to-center spacing of about 6
`to 15 microns (pm).
`In the prior art, the next step is to use ?xed masks to
`fabricate the conductive layers (sometimes called “met
`allization layers”), to connect together the individual
`gate-array devices. Typically two or sometimes three
`metalization layers are used.
`After this, the completed die is tested. If any of the
`devices on the die are defective, that die will fail an
`exhaustive test and be scrapped. Therefore, the more
`transistors per die the lower the manufacturing yield. In
`some cases redundant sections of a circuit are provided '
`that can be substituted for defective sections of a circuit
`by fuses after metallization. Typically such redundant
`sections can be 5% to 10% of the total circuit.
`
`45
`
`60
`
`SUMMARY OF THE INVENTION
`An object of this invention is to provide an improved
`test procedure for integrated circuits to increase pro
`duction yields, by testing a circuit at the ICLU level
`(hereinafter called “?ne grain testing”), compared to
`conventional testing at the functional IC or die level.
`
`65
`
`BRIEF DESCRIPTION OF THE DRAWING
`FIG. 1 shows a section of a gate array wafer and the
`device contacts.
`FIGS. 2-3 show a top and side view of part of the
`tester surface.
`FIGS. 4(a) and 4(b) show the test procedure.
`FIG. 5 shows the ?uid pressure test assembly.
`FIG. 6 shows an exploded view of the wafer and
`tester surface.
`FIGS. 7-12 show the steps to fabricate the tester
`surface.
`FIGS. 13-15 show the steps to fabricate another
`embodiment of the tester surface.
`FIG. 16 shows how nine die can form one super die.
`Each reference numeral when used in more than one
`Figure refers to the same structure.
`
`DETAILED DESCRIPTION
`As stated above, the prior art fabricates a plurality of
`transistors on a die, interconnects the transistors to form
`desired logic, tests the entire die, and scraps the die if
`the logic doesn’t work. In the present invention, after
`fabricating the transistors exactly as before, the transis
`tors or ICLUs are tested individually. Then the inter
`connect scheme is modi?ed, if necessary, by CAD
`means (of well known design) to bypass defective tran
`sistors or ICLUs and substitute, logically speaking,
`replacement ICLUs. Then the metallization layers are
`deposited, and patterned in accordance with the modi
`
`Elm Exhibit 2135, Page 8
`
`

`

`4,924,589
`3
`4
`?ed interconnect scheme typically by E-beam (Elec
`points on the tester surface 10 and the wafer 1 come
`together and make ?rm electrical contact. This is possi
`tron-beam) lithography, instead of the masking process
`of the usual conventional scheme, even though each die
`ble due to the fact that the surface of the wafer 1 under
`test typically has a controlled total runout ?atness
`is to carry out the same function as the other die.
`The present invention in one embodiment begins with
`within 6 to 10 microns across its complete surface. Se
`condly, the tester surface 10 is less than 15 microns
`a gate array conventionally fabricated on a silicon or
`GaAs wafer. The gate array transistors are arrayed in
`thick and typically 1.5 microns thick and of a very
`columns and rows on the wafer surface 1, and the active
`?exible material, such as low stress silicon dioxide.
`Thirdly, the metal contact points are the highest raised
`regions of each transistor are provided with contact
`points such as 2-1 to 2-32 which are in columns and
`surface features on either the tester surface 10 or the
`rows also as shown in FIG. 1 (not all contact points are
`surface of the wafer 1 under test, and are of a controlled
`uniform height typically between 2 and 6 microns.
`numbered). Redundant (or extra) devices are designed
`into each column, with a redundancy factor dependent
`The wafer 1 under test as shown in FIG. 4(a) is
`on the expected yield of the individual transistors of
`mounted on an x-y motion table (not shown). Move
`ICLUs being ‘tested.
`ment of the table in the x-y directions positions the
`The surface of the wafer 1 is optionally planarized
`wafer for test by alignment of the contact points such as
`with a cured layer of polymide 0.8 to 1.5 micron thick
`15-1 and 15-2 of the test surface 10 (FIG. 2) with the
`if the step heights between contact points are greater
`corresponding device contact points such as 2-1 and 2-2
`of the wafer 1.
`than_0.5 microns. (The contact points 2-1 to 2-32 are
`masked from the polymide, and metal is deposited to ?ll
`During the test procedure as shown in FIG. 4(a), the
`the via.)
`wafer 1 under test is retained by suction in a substan
`tially planar ?xed position, by means of the support 26
`The fabricated (but not metallized) wafer 1 is now
`ready for testing. In the described embodiment, only
`illustrated in FIG. 4(a) and in FIG. 5. Use of suction to
`hold a wafer in place is well-known. Tester surface 10 is
`one column of transistors on each die is tested at a time,
`although testing more than one column per step is possi
`mounted on a support ring 36 (as described below) to
`ble. For a die of typical complexity this requires making
`provide mechanical support and electrical connections,
`as shown in FIG. 5. The tester surface 10 is urged uni
`contact with all of the perhaps 10,000 or so contact
`points such as 2-1 to 2-4 in one column simultaneously,
`formly toward the wafer 1 under test by a ?uid well or
`bladder 38 immediately behind tester surface 10. A
`and then stepping across all 100 or 200 or more columns
`in each die, to totally test each die in step-and-repeat
`solenoid (not shown) is provided for macro control of
`fashion. Each contact point such as 2-1 is small—usually
`the pressure exerted by the ?uid in the ?uid well 38 on
`4 X 4 microns. Each wafer contains a plurality of die, the
`tester surface 10. The depth of ?uid well 38 is less than
`exact number depending on the size of the wafer but
`100 mils; this is the distance between the back of tester
`typically being in the hundreds.
`surface 10 and piezoelectric pressure cell 40.
`It is also therefore possible to test more than one
`Piezoelectric pressure cell 40 is a layer of material
`column at once to perform testing on the ICLU’s.
`about ?ve-hundredths of an inch (one millimeter) thick
`that will expand about one-half micron when voltage is
`The ?exible tester of this invention includes a tester
`applied to the piezoelectric material. The applied pres
`surface 10 (described in detail below) as seen in FIG. 2
`which includesa series of tester surface contact points
`sure on the back of the tester surface 10 is only a few
`including 15-1, 15-2 (which are arranged to contact on
`grams per square centimeter. Piezoelectric pressure cell
`40
`a one-to-one basis the corresponding contact points in a
`40 provides the last increment of pressure on the ?uid
`column on the die under test) and a complete wiring
`and in turn on the back of tester surface 10 to achieve
`interconnection, including a testing array which in
`good electrical contact between the contact points such
`cludes contacts 16-1, 16-2 and 16-3 and interconnect
`as 15-1 and 15-2 on tester surface 10 and the contact
`pathways 17-1, 17-2 and 17-3 as seen in FIG. 3, at vari
`points such as 2-1 and 2-2 on wafer 1. The ?uid is pro
`vided to the assembly through ?uid port 46 which is
`ous levels 22, 23, 24 in the tester surface. The tester
`array which includes contacts 16-1, 16-2 and 16-3 con
`connected to a ?uid reservoir (not shown). The support
`ring 36 includes computer cabling attachment sites 48
`nects to a conventional tester signal processor as shown
`in FIG. 40 having line driver logic circuits for accessing
`and‘ multiplexer circuits 50. The support ring structure
`serially or in parallel the devices under test. The driver
`is described in more detail below.
`logic signals are programmed separately in a well
`As described above, mechanical positioners (i.e., x~y
`known manner and are multiplexed between testing
`table aligners and conventional mechanical vertical
`array contacts 16, providing programmable input/out
`positioners, not shown) bring the wafer 1 to within a
`put means for supplying diagnostic signals to the transis
`few mils of the tester surface 10 and make a ?rst approx
`imation of the alignment of contact points through a
`tors or ICLUs under test. Therefore, all the wafer
`conventional optical aligner (not shown). The optical
`contact points in one column can be accessed in one
`physical contact step of the transistors or devices to be
`alignment is performed in a manner similar to that used
`by present semiconductor mask aligners, by using align
`tested.
`The wafer 1 under test and the tester surface 10 are
`ment patterns in predetermined positions on both the
`disposed on a support 26, as shown schematically in
`wafer 1 being tested and the tester surface 10. Only the
`FIG. 4(a), for test purposes, to electrically connect the
`pressure of the ?uid moves the tester surface 10 the one
`contact points on the tester surface 10 and correspond
`or two mil distance separating the tester surface 10 and
`ing contact points on the wafer 1. FIG. 4(b) shows the
`the wafer 1 to be tested in order to gain physical
`test procedure in process-?ow format. A fluid well or
`contact. FIG. 6 illustrates in an exploded view wafer 1
`bladder (not shown) is used to exert an uniform pressure
`and tester surface 10 being moved by ?uid pressure
`over the ?exible tester surface 10 (FIG. 4(a)) in order to
`from ?uid well 38 just before wafer contact points such
`conform it to the surface of the wafer 1 under test and
`as 2-1 and 2-2 make contact with corresponding tester
`to ensure that the numerous corresponding contact
`surface contacts such as 15-1 and 15-2.
`
`30
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`15
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`45
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`50
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`60
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`65
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`Elm Exhibit 2135, Page 9
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`4,924,589
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`fects to be expected with standard available silicon
`In an additional alignment method, a small area (not
`wafers is approximately five per cm2 currently. This
`shown) with a pattern of alignment contact points of
`various sizes up to 1 mil (25 microns) square and posi
`means that approximately ?ve or less ICLUs can be
`expected to be defective per cmz. The number of de
`tioned at two or three corresponding alignment sites on
`both the wafer 1 and the tester surface 10 is then used as
`fects per cm2 increase as device feature sizes decrease,
`an electrical circuit feedback system. The feedback
`but not dramatically, as indicated by the current indus
`system, starting with the largest contact points at each
`trial use of 0.8 micron geometries for 4 Megabit mem
`site and moving progressively to the smallest, deter
`ory devices, which will soon be in limited production.
`This rip-up router software process approach takes
`mines the accuracy of the alignment and makes appro
`priate micron sized adjustments under computer control
`advantage of this wafer ICLU defect density character
`istic by employing a CAD rip-up router. This CAD
`to within sub-micron x-y alignment accuracy.
`software tool has only become available recently and
`In the described embodiment, the fluid in the test
`surface assembly is Florinert from DuPont. Any alter
`heretofore was only used during the design phase of a
`nate ?uid with similar nonconductive and nonreactive
`large IC in an effort to conserve designer and computer
`properties could be substituted.
`time. The rip-up router attempts to make local changes
`to existing IC metallization layout and, therefore, avoid
`After an entire wafer 1 has been tested, it is removed
`ing the expense of recomputing the complete IC’s met
`and another wafer moved into position to be tested.
`The data resulting from the tester signal processor is
`allization trace routing. The rip-up router is an auto
`matic tool; it accepts change commands to the ICLU
`a list of the location of each defective transistors or
`ICLUs. This list is automatically communicated to the
`placement net-list and then computes changes to the
`conventional CAD means from the tester signal proces
`IC’s metallization database. This modi?ed IC metalliza
`tion database is then processed for input to the E-beam
`sor as shown in FIG. 4. The CAD means then, by spe
`lithographic equipment; this processing software is the
`cial software algorithms works out an interconnect
`strategy for each die. Therefore, the master placement
`standard software used to drive the E-beam equipment.
`The computer processing time required to do local
`scheme of the net list is modi?ed in terms of the place
`rip-up route changes has been measured and found to be
`ment of the defective ICLUs so as to bypass the defec
`tive ICLUs and interconnect defectfree ICLUs from
`typically 1 to 2 seconds on an inexpensive 32-bit mini
`computer.
`the stock of redundant ICLUs.
`The invention uses two alternative software algo
`The modi?ed net list is next used to produce the
`rithms: recomputation of metallization trace routing or
`database for the desired interconnect patterns on the
`wafer using E-beam means. The metallization process is
`a CAD rip-up router.
`_
`The ?rst alternative is the well-known and commer
`in one embodiment a two layer metallization, although
`cially available recomputation of the metallization trace
`a single layer of metallization or three or more layers of
`routing for all affected layers of a speci?c IC after it has
`metallization can also be used. The process involves
`been tested. .The routing is performed automatically
`depositing a layer of insulation, such as silicon dioxide,
`with CAD software. This routing procedure requires
`typically of about one micron thickness over the wafer
`that suf?cient defect-free redundant ICLUs have been
`surface, and cutting vias by means of a mask to the
`allocated in the master placement of ICLUs and that the
`contact points on the wafer surface through the silicon
`dioxide layer. Then a layer of metal, typically alumi
`redundant IClIUs can be routed into the circuit given
`the potential restrictions that the number of metalliza
`num, is deposited over the silicon dioxide. Then a layer
`of photoresist is deposited and patterned, for example
`tion layers may present. The software that precedes this
`processing performs the entry into a CAD system of the
`using E-beam (maskless) lithography. The E-beam is
`placement net-list change commands that direct the
`controlled by the CAD database means and its modi?ed
`substitution of the defective ICLUs with available re
`net list to make the desired interconnect pattern cor
`dundant ICLUs. These change commands are speci?c
`rected in accordance with the test results. The photore
`sist is then developed and removed where not exposed
`to the CAD system that is selected for use, and the
`to the E-beam, allowing the patterning of the intercon
`commands issued are similar to those a circuit designer
`would enter if making an ICLU placement select in a
`nects as desired.
`design change when using a gate-array
`The metallization process is then repeated for the
`This recomputation routing approach makes substan
`second metallization layer and any subsequent metalli
`zation layers. The metallization process is generally
`tial requirements on computing resources. However,
`super-minicomputers presently available are suf?cient
`well known technology, the innovation being that the
`to meet the computational requirements.
`net list is modi?ed for each die even though the function
`The second software alternative, a CAD rip-up
`to be implemented on each die is identical.
`router, takes advantage of the knowledge that the de
`At this point the wafer is complete, ready for scrib
`fects occurring in current bulk silicon semiconductor
`ing, packaging and ?nal test as usual.
`processes are few in number and are localized (i.e., the
`The tester surface as mentioned above is a key ele
`defects only affect one or two ICLUs at any particular
`ment of this invention.
`defect site), and of the ?ne grain ICLU structure. The
`The tester surface is specially fabricated using ad
`?ne grain level of testing minimizes the area necessary
`vanced semiconductor manufacturing methods. Start
`60
`for redundant ICLUs and the complexity of the place
`ing as shown in FIG. 7 with typically a conventional 5”
`ment and routing changes that must be effected to cor
`or 6" silicon wafer substrate 101 (without any circuitry
`rect for defective ICLUs. Wafer or large ICs that indi
`on it), a layer of KBr or other release agent 102 is depos
`cate larger than normal numbers of defects or defects
`ited over the wafer 191 surface, followed by a layer of
`that are large in affected area when tested by testing
`gold 103 about 1000 A (0.1 micron) thick. Then a layer
`equipment will cause the wafer to be rejected as outside
`of silicon'dioxide 104 of about one micron thickness is
`of the acceptable bulk manufacturing standards which
`deposited on the wafer 101 surface by means of chemi
`are typical of all existing IC lines. The number of de
`cal vapor deposition. This is a low stress layer, depos
`
`40
`
`45
`
`65
`
`Elm Exhibit 2135, Page 10
`
`

`

`15
`
`20
`
`25
`
`30
`
`4,924,589
`8
`7
`points, the support ring 122 and its attached layers are
`ited at about 100° F., using commercially available sys
`tems such as provided by Ionic Systems (Milpitas,
`put in a ?oat (not shown), and the ?oat placed in an
`electrolytic solution containing gold with the exposed
`Calif.) or ASM Lithography, Inc. (Tempe, Ariz.). The
`silicon dioxide layer 104 has a surface stress of about
`ends of the vias 108 as shown in FIG. 9 immersed in the
`105 dynes/cm2, making it very ?exible. Then, using
`solution. Voltage is applied and the probe points such as
`conventional mask methods and photoresist layer 106 as
`132 grow by electrolyzation at the ends of the vias 108.
`described above, vias such as 108 are etched, down to
`The probe points such as 132 are thus made of gold in
`the gold layer, in the silicon dioxide layer 104 to de?ne
`the preferred embodiment and grow out of the central
`the probe points. The vias such as 108 are 2 to 4 microns
`part 124 of the test surface as shown in FIG. 12. The
`in diameter.
`probe points such as 132 are 2 to 4 microns in diameter,
`The tester surface, in the preferred embodiment, has
`and about 4 microns high. They connect with the metal
`two similar gold metallization layers on top of the wa
`in each via, and hence to the two metallization layers.
`fer. The ?rst metallization layer is formed by ?rst de
`The pattern of probe points such as 132 on the tester
`positing, over‘, the KBr layer 102, a silicide layer (not
`surface is unique, and corresponds to the contact test
`shown) 1000 A to 2000 A (0.1 to 0.2 microns) thick to
`points on the wafer to be tested.
`act as an etch stop. Then the silicide deposition is re
`Several kinds of probe points 132 can be provided. In
`moved from all but the vias 108. A nichrome/ gold
`an alternative embodiment, probe point height is deter
`metallization-J layer 112 is deposited, to a thickness of
`mined by a mask. To provide masked probe points, a
`1000 to 2000 A, and a ?rst layer metal mask and etch are
`mask containing vias is formed on surface 130 at the
`used to de?ne the interconnect lines by forming traces.
`probe point locations, then the points grown in the vias
`Then a second silicon dioxide layer 114, also about
`and then the mask removed. The probe points can be
`one micron thick, is deposited, followed by the second
`aluminum or other suitable metals or conductive materi
`layer via 116 masking, second layer via etching, ni
`als.
`chrome/ gold metallization layer-II 118 and second
`The tester surface itself can be fabricated with elasto
`layer metal mask and etch as shownin FIG. 9.
`meric probe points such as conductive doped polyacet
`Next, customized multiplexer circuits such as 120-1
`ylene (personal contact with Professor Alan G. Mac
`and 120-2 as shown in side view in FIG. 10 are attached
`Diarmid, University of Pennsylvania and also see “Plas
`to the metallization-II layer 118. These multiplexers
`tics that Conduct Electricity”, Scienti?c American,
`120-1 and 120-2 are individual die that contact the me
`Feb., 1988, pgs. 106-111, by Richard B. Kaner and Alan
`tallization-II layer 118 traces as desired, to provide
`G. MacDiarmid) that compress on contact with the
`electrical connections to the tester signal processor.
`contact points of the device or ICLU under test, to
`The multiplexers such as 120-1 and 120-2 are dispersed
`allow closer probe point spacing or to make the tester
`around the outer part of the metallization-II layer 118
`surface more ?exible. Such elastomeric materials are
`on the wafer 101, and serve as programmable input/out
`applied and etched with established techniques.
`put means.
`In a slightly different method to fabricate the tester
`Next a mechanical structure called a support ring 122,
`surface, the substrate wafer ?rst has etched in its center
`as shown in top view in FIG. 11, and in side view in
`a circular depression one to two inches in diameter and
`FIG. 12, is bonded with epoxy adhesive to the metalli
`typically twenty microns deep. This depression will
`zation-II layer'118 on top of the wafer 101. The support
`impart a gradual extension to the outer part of the tester
`ring 122 is typically a quartz annulus (ring) of the same
`surface, so that the center part of the ?nished surface
`outer diameter as the wafer substrate 101 and an inner
`will extend slightly below the surrounding tester sur
`diameter of 1 to 2 inches.
`face.
`The quartz support ring 122 is in one embodiment 0.1
`A different tester surface is illustrated in FIGS.
`inch thick. Its inner area 124 (see FIG. 11) is the contact
`13-15. Here the multiplexer circuits and tester logic are
`area of the test surface. The ring 122 thus supports the
`integrated into the tester surface. FIG. 13 shows how,
`actual contact area 124 and provides electrical connec
`as before, starting with a standard semiconductor wafer
`tions to the remainder of the test system. The support
`133, multiplexer and tester'logic circuitry 134 is fabri
`ring 122 has holes such as 126-1 and 126-2 (FIGS. 11,12)
`cated on the surface of wafer 133. Then, as described
`machined into it to accommodate the multiplexer cir
`above, a depression 135 is etched in the center of wafer
`cuits including 120-1- and 120-2 as shown in FIG. 12.
`133. The depression 135 is again one to two inches in
`The support ring 122 and its underlying silicon diox
`diameter and typically twenty mils deep. Then, as
`ide and metal layers are now released from the underly
`shown in FIG. 14, several layers of silicon dioxide and
`ing silicon wafer 101 shown in FIG. 9. The release
`metallization 136 are formed on the wafer over depres
`agent KBr (or similar material) was the material ?rst
`sion 135 and over the logic sites 134. In this embodi
`deposited on the wafer 101. By means of the release
`agent, scribing around the edge of the support ring and
`ment, the tester probe point array sites such as 138 may
`(optionally) be etched into the surface of the wafer 133
`then dipping the assembly shown in FIG. 12 in water
`in the depression, to allow preformation of the probe
`allows the silicon dioxide layers to be peeled off the
`points by ?lling the etched probe point sites 138 with
`wafer 101. Alternatively, without the use of KBr, re
`metallization.
`lease can be achieved by etching the wafer 101 away in
`After the tester surface 136 (FIG. 14) is fully fabri
`an ethylene-diamine solution.
`Next, with the tester surface free of the wafer 101, the
`cated on wafer 133, the surface 136 is separated from
`?rst gold deposition layer 103 shown in FIG. 7 is
`wafer 133 s before by selective etching away of wafer
`stripped off, leaving the exposed gold-?lled vias such as
`133. (Release agents cannot be used here since part of
`wafer 133 including logic sites 134 must remain as part
`108 on the released surface 130 as shown in FIG. 9.
`To complete the tester surface, probe points are
`of tester surface 136). The tester surface 136 is attached
`grown on the released surface, so that the probe points
`to a support ring 150 before the step