CHARACfERISTICS OF CMOS DEVICES FABRICATED
`
`USING HIGH QUALITY THIN PECVD GATE OXIDE
`
`L.K. Wang, D.S. Wen, A.A. Bright, T.N. Nguyen* and W. Chang
`
`IBM T. J. Watson Research Center
`Yorktown Heights, NY 10598
`
`
`
`*IBM East Fishkill, Hopewell Junction, NY 12533
`
`
`
`ABSTRACT
`
`channel length as low as 0.25JLm. This is the first demon­
`
`stration that very thin PECVD oxides used in the fabri­
`cation of silicon gate FETs. For the comparison purpose
`N-and p-channel FETs at 0.25JLm channel length are
`
`the same 0.25/lm FET devices with thermally grown gate
`
`
`fabricated utilizing very thin (35-70 A) PECVD oxide as
`
`
`oxide are also fabricated in this experiment. In this paper,
`
`the gate dielectric. This oxide can be deposited at very low
`
`the PECVD oxide properties, the FET device character­
`
`substrate temperature (S350 °C) in a low pressure
`istics and the comparison between devices with PECVD
`PECVD system. A helium plasma treatment is applied
`
`and thermally grown gate oxides will be discussed.
`
`prior to the deposition in order to reduce the surface
`roughness and lower the surface state induced mobility
`EXPERIMENT
`
`degradation. Measured oxide quality is similar to the
`
`thermally grown Si02 in terms of the oxide charges and
`
`
`breakdown characteristics. The device characteristics are
`The PECVO oxide films are deposited at very low
`
`similar to the same devices fabricated with thermally
`substrate temperature (S3500C) in a low pressure
`grown gate oxide although the device transconductances
`PECVD system as shown in figure 1. The process pa­
`
`
`are slightly reduced. The potential of using this kind of
`
`rameters of this deposition system are listed in table I. A
`
`oxide for the deep sub-micron devices is discussed.
`
`base pressure at 1 x 10-4 is routinely achieved before each
`
`
`
`deposition process. The substrate is pre-cleaned in the di­
`INTRODUCTION
`lute HF and rinsed in 01 water before loaded into the
`system. A helium plasma treatment prior to the film de­
`
`position is applied to minimize the FET mobility degrada­
`Plasma enhanced chemical-vapor deposition (PECVD)
`
`tion from the surface roughness [I]. The film deposition
`
`has the advantage of depositing oxide in a clean processing
`is operated in a gas flow consisting of diluted
`
`
`vicinity at very low temperature. The thermal oxidation
`
`SiH4/helium, N20 and helium carrying gas. At a low de­
`
`process and dopant segregation/redistribution can be
`
`
`position rate ( l4A/min.) the gas phase nucleation is min­
`
`
`eliminated by depositing oxide directly on the device
`
`
`imized to accomplish a true heterogeneous CVD process.
`
`
`
`substrates in a low temperature environment. This is very
`
`desirable for the deep submicron silicon MOSFET appli­
`The FET devices are fabricated using a O.25/lm CMOS
`
`
`cations and for other novel semiconductor FET devices
`
`
`required low temperature processing. However, the oxide
`process [4]. The wafers are separated into different
`and the film quality are
`
`
`to substrate interface properties
`groups at the gate oxide step. In our experiment the
`the major concerns to use the PECVD oxide as gate
`
`
`PECVD oxides are deposited at a thickness 70A. Thermal
`
`oxides of the same thickness are also grown on the control
`
`dielectric in the device fabrication. It has been reported
`
`
`
`
`that high temperature annealing after the deposition is re­
`wafers for the comparison purpose. Also a 40A thick
`PECVD oxides are deposited on some of the wafers in
`quired to densif y the film and to improve the oxide quality
`
`
`as gate dielectric in MOSFET applications [1-3]. Recently
`
`order to study the FET characteristics with thinner
`
`
`a modified PECVD proc­we have successfully practicing
`
`PECVD gate oxides. Optical lithography is used at all
`ess to deposit very thin (35-70A) oxides as gate insulator
`patterning levels through out the entire device fabrication.
`
`The polysilicon gate dimension as low as O.3JLm can be
`
`of polysilicon gate CMOS devices at very low substrate
`temperature (S 3 50 0). A helium plasma treatment prior
`patterned in a I-line stepper using contrast enhancement
`
`
`to the deposition is introduced in order to improve the
`
`
`lithography followed by a high selectivity reactive ion
`
`
`
`oxide to silicon interface roughness. The oxide is deposited
`
`etching process. In this process arsenic implant doped N +
`in a high flow rate of helium carry gas at low deposition
`
`polysilicon gates is used for the n-channel FETs and boron
`rate to ensure a near ideal chemical vapor deposition
`doped P+ gates are used for p-channel devices. The N+
`
`
`process. Excellent device characteristics are obtained at
`
`and P+ poly gates are doped during the source/drain for-
`17.6.1
`
`
`
`CIl2637-7/89/0000-0463 $1.00 © 1989 IEEE
`
`IEDM 89-463
`
`Page 1 of 4
`
`SAMSUNG ET AL. EXHIBIT 1084
`Samsung et al. v. Elm 3DS Innovations, LLC
`IPR2016-00387
`
`

`

`tions, a 350..\ thick self aligned titanium silicide
`
`mation steps. The arsenic doped N+ source/drain junc­
`
`this device is lower due to the thinner gate oxide is used.
`
`tions at a depth around O.IJ.lm is achieved by a 900°C
`
`It shows a transconductance at 108 mS/mm and there is
`annealing process. The boron doped P+ junctions at
`
`
`no indication of boron penetration from the boron doped
`0.12J.1m deep are formed by germanium amorphorization
`
`P+ polysilicon gate. However the gate current of this de­
`
`implant prior to the BF2 implant and subsequently driven
`vice is much higher at the same gate bias voltages (figure
`
`in at 850°C. After the drive-in of source and drain junc­
`
`4(b» due to the tunneling of the holes through the thin
`is formed
`
`gate oxide. The hot carrier stress induced threshold volt­
`by a rapid thermal annealing process on the source/drain
`
`age shift result is shown in figure 5. After the 105 second
`
`and poly gates simultaneously to obtain a sheet resistance
`
`of hot carrier stress the device threshold voltage is only
`
`of around 7 n/square. The fabricated devices are
`shifted by 110 mV induced by the electron trapping in the
`
`passivated by LPCVD oxide and a Al-Cu-Si metal with
`PECVD gate oxides. These results suggest that the
`titanium barrier layer is used as the final metanization.
`
`PECVD oxide can be used as gate dielectric even for the
`further scaled down FET devices.
`
`DEVICE CHARACTERISTICS
`
`CONCLUSIONS
`
`The thin oxide breakdown characteristics are compared
`
`
`
`using capacitors isolated by thick oxides. A typical break­
`In conclusion a high quality thin PECVD gate oxide
`
`
`
`down current voltage characteristics is described in figure
`
`has been used in the fabrication of 0.25J.1m CMOS de­
`
`2(a). There is little difference in the breakdown voltages
`
`vices. These devices are comparable to thermal oxide de­
`between tbe PECVD oxide and thermal grown oxides at
`
`
`vices without the need of high temperature process and
`
`
`this thickness. Figure 2(b) shows the distribution of the
`
`
`oxidation steps. Although the carrier mobility from both
`breakdown voltages of the 7 nm thick PECVD oxide from
`
`n-and p-channel devices are slightly reduced as indicated
`a large number of samples. Other oxide parameters
`
`from the transconductance measurement. The PECVD
`
`measured from the C-V characteristics are listed in Table
`
`
`deposit oxide provide a potential alternative as the gate
`trap density D. and the
`II. Although the midgap interface
`
`
`dielectric for deep sub-micron FETs as well as other non­
`fix charge density Dr are larger than most thermany grown
`
`silicon FET devices with thermal process limitations.
`
`oxides, they are still acceptable for the device applications.
`
`ACKNOWLEDGMENTS
`
`The faVd characteristics
`of the 0.25J.1m n-and p­
`channel FETs are shown in figure 3 for both PECVD and
`The authors would like to thank the personnel in the
`thermany grown gate oxides. The transistor
`
`mM Yorktown Silicon Facility for their process support.
`
`transconductance from both n-and p-channel FETs with
`The authors also acknowledge Dr. Tak Ning, Dr. John
`
`PECVD gate oxide are slightly reduced due to lower mo­
`
`Batey and Elaine Tierny for helpful discussions of this
`
`
`bility. The mobility reduction is attributed to the higher
`work.
`
`surface state density and/or the rougher interface of the
`PECVD oxide. The helium plasma treatment prior to the
`
`
`oxide deposition has improved the interface quality com­
`
`pared to the prior works [1-3]. The FET parameters de­
`[1] Stasiak et. ai., IEEE Electron Device Lett.,
`rived from this figure are summarized in Table III. The
`
`pp.245-247, Vo1.10, No.6, 1989.
`
`n-channel FETs suffer more on transconductance degra­
`[2] J. Batey et. ai., IEEE Electron Device Lett.,
`FETs with thinner (40..\) gate oxides are also fabricated
`
`dation may due to the higher electron mobility. P-channel
`
`pp.148-150, Vo!'8, No.4, 1987.
`[3] J. Lee, I. C. Chen and C. Hu, IEEE Electron Device
`The fa v., characteristics
`with the same device structure.
`is
`
`Lett., pp.506-509, Vo!.7, No.9, 1986.
`
`shown in figure 4(a). Although the threshold voltage of
`
`
`REFERENCES
`
`[4] B. Davari et. ai., 1988 IEDM proceeding, pp.56.
`
`464-IEDM 89
`
`17.6.2
`
`Page 2 of 4
`
`

`

`Temperature
`Base pressure
`Surfa<:e preparation:
`He flow rate
`preuure
`power
`Deposition:
`ps flow rate:
`Sm.(2%)/He
`NzO
`He
`pressure
`power
`
`350 °c
`2xlO-' torr
`
`1000 acx:m
`1.0 torr
`100 watt
`
`38 acx:m
`250 acx:m
`2150 acx:m
`0.5 torr
`200 watt
`
`Deposition rate
`
`14 A/min.
`
`Table I PECVD oxide process parameters.
`
`Thermal 8iO. ----
`6.0 PECVD 8iO. -
`
`4.0
`
`2.0
`
`_- - - -- - - -- - - - -�o­
`---
`1.5
`--- -- -------
`1.0
`
`--- - -- --- - ---- - 0.5-
`2.0
`1.0
`VoS<V)
`[a]
`
`3.0
`
`-2.0 ----ThermaI5i02
`--
`PECVD Si02
`-1.5
`
`-0.5
`
`-1.0
`-- ------------
`- 3.0
`-2.0
`-1.0
`Vos(V)
`[bJ
`of O.25/Lm Le!! n-channel
`Figure 3(a) I-V characteristics
`FETs with 7 nm thermally grown
`and PECVD gate
`of O.25/Lm Leff p-channel
`oxides. (b) I-V characteristics
`FETs with 7 nm thermally grown
`and PECVD gate
`oxides.
`
`Figure 1 Schematic diagram of the PECVD system.
`
`10-2 -- PECVD Oxide
`
`--- -- Thermal Oxide
`lox=7.0nm
`
`10-4
`
`g 10-6
`10-8
`
`u.
`
`10 -10
`
`-4.0 -6.0 -8.0 -10.0
`VF (V)
`[ a]
`
`100.0
`
`CD
`0
`c:
`� 80.0
`:::I
`0
`0 60.0
`0 '0
`CD 40.0
`Cl
`<II 'E 20.0
`0 CD Q. 0.00
`U') N
`� 00 0 0 0
`ci
`Nc? -.i Il'i u)
`I I I I I
`
`CD
`
`I I
`
`Average Breakdown Field (MV/cm)
`
`[ bJ
`
`of 7 nm PECVD
`Figure 2 (a) Breakdown field distribution
`
`and thermally grown oxides. (b) Breakdown field distrib­
`ution of 7 nm PECVD oxide.
`
`17.6.3
`
`IEDM 89-465
`
`Page 3 of 4
`
`

`

`7.2
`DID
`9
`MY/em
`6x 1010 cm -�y-I
`6xlOll cm-'
`1.6 DA/ cm2
`Table II Parameters of 7 nm PECVD oxide.
`
`
`
`Parameter
`N-dwmeI
`
`PET:
`
`'-
`oubV,lIIope
`
`G.(Vd .. 2.S V)
`
`P-cbumel PET:
`'-
`
`oubV,lIIope
`
`TbermaJ onde
`
`I PECVDoDde
`
`73 A
`
`71 A
`
`81 mY/dec. 83 mY/dec.
`
`220 DIS/mm 177 DIS/mm
`
`74 A
`
`71 A
`
`82 mY/dec. 83 mY/dec.
`
`
`
`G.(Vd--2.S V)
`
`88 DIS/mm
`
`80 DIS/mm
`
`Table ill Comparison of device characteristics
`of n-and
`p-channel devices with thermal and PECVD gate oxides.
`
`120r-----�----�------r-----._----_,
`
`20
`oL-____
`0.0
`
`� ____
`2.0
`
`VG = -0.3 volt.
`vD = -4.0 volt.
`101(= 40 I'IT1
`L ... = 0.24pm
`� ______
`L- ____
`_L ____
`8.0
`8.0
`4.0
`Tme lseoondl
`
`�
`10.0
`x 10'
`
`Fig. 5 Threshold voltage shift as a function of the hot
`electron stress time for a O.24,.m p-channel MOSFET
`with 4.0 nm PECVD gate oxide. (VDS= 4.0 volts, VGS =
`0.3 volts)
`
`_ 2.5 Lett = 0.241"m
`tox= 4.0nm
`-2.0
`<"' - 1.5
`.§.
`Jl -1.0
`
`-1.5
`
`-1.0
`
`-0.5
`-2.0
`-1.0
`Vas (V)
`[a]
`
`-3.0
`
`10-2
`
`10-2
`10-4
`10-8
`g
`10-8
`Cl
`10-'0
`10-12
`10-14
`10-14
`-2.40
`.030 0.00 -0.60 -1.20 - 1.80
`VG (V)
`[b]
`
`Figure 4(a) I-V characteristics and (b) Gate current and
`
`
`
`substrate current of a O.25,.m p-channel MOSFET with 4
`nm PECVD gate oxide.
`
`466·IEDM 89
`
`17.6.4
`
`Page 4 of 4
`
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