Solid-State Electronics Vol. 36, No.7, pp. 1021-1026, 1993
`Printed in Great Britain. All rights reserved
`
`$6.00 + 0.00
`0038-1101/93
`Copyright © 1993 Pergamon Press Ltd
`
`EFFECT OF ANNEALING AND PLASMA PRECLEANING
`ON THE ELECTRICAL PROPERTIES OF N20jSiH4 PECVD
`OXIDE AS GATE MATERIAL IN MOSFETs AND CCDs
`
`R. K. CHANANA,R. DWIVEDIand S. K. SRIVASTAVA
`Centre for Research in Microelectronics, Department of Electronics Engineering, Institute of Technology,
`Banaras Hindu University, Varanasi-221 005, U.P., India
`
`(Received 5 June 1992; in revised form JO'December
`
`1992)
`
`SiH4 and NzO involving low total inflow of gases and very high deposition rate (1400 A/min)
`Abstract-Pure
`have been used to deposit PECVD oxide films in a parallel-plate reactor system. The effect of long time
`(40 min) low temperature (450°C) annealing in N2 ambient and plasma precleaning with different gases
`like Ar, N2, H2, 02' CF4/50% H2oon the electrical properties of the deposited films have been studied.
`Flatband voltage, Vfb, fixed oxide charge density, Dr, interface trap level density, Dit, dielectric breakdown
`strength, hysterisis and bias stress stability are the properties studied. These properties are relevant to the
`gate oxide in MOSFETs and CCDs. The deposited films involving annealing and plasma precleaning have
`been found to show electrical properties comparable to those of dry thermal oxide films grown at I 100°C.
`films deposited on H2 plasma precleaned wafers showed no bias stress instability.
`In particular
`
`1. INTRODUCTION
`
`Plasma processing is now widely used in VLSI tech(cid:173)
`nology. Inorganic insulator films are being deposited
`by plasma deposition (PD) process where low depo(cid:173)
`sition temperature (25-500°C) cannot affect the pre(cid:173)
`vious process steps. The low temperatures involved
`overcome the disadvantages associated with the high
`temperature (90D--1200°C)thermal oxidation process,
`which is becoming incompatible with developments
`in submicron technology. These disadvantages are:
`(1) formation of stacking faults which originate at the
`sites of mechanical damage at the wafer surface[I,2]
`and then expand during oxidation
`by emission
`of vacancies to the growing Si-Si02
`interface[3,4];
`(2) formation of the bird's "beak" profile during
`the dielectric isolation process which creates abrupt
`topographical
`features on the surface causing breaks
`or discontinuities in the film covering them. It also
`reduces the available active surface area and therefore
`affects the packing density of the integrated cir(cid:173)
`cuits[5];
`(3) doping impurity redistribution
`takes
`place because of the high oxidation temperatures.
`PD is useful in controlled doping oflayers, alloying
`and multilayering[6] and is fast replacing the chemical
`vapour deposition (CVD) Si02 because of its better
`results[7]. PECVD Si02 films can be formed by
`or silane
`reacting precursor gases like silane (SiH4)
`derivations with an oxidant like CO2, O2, N20 etc. in
`an RF or microwave discharge. This dates back 27
`years[8-20]. Usually the precursors are diluted in Ar
`or He to 1-5% before being used, but pure gases can
`be used as well[14].The overall reaction leading to the
`formation of plasma Si02 is:
`SiH4 + 2N20 -> Si02 + 2H2 + 2N2
`
`the suggested mechanisms has been
`and one of
`reported by Dun et a/.[21]. The electrical energy in the
`reactors used is either inductively coupled,
`indirect
`capacitively coupled through the walls of the vacuum
`chamber using external electrodes or direct capac(cid:173)
`itively coupled using internal electrodes. The latter
`provides better control over the process and flexibility
`in the reactor design and uniform electric fields can
`be created over
`large areas resulting in uniform
`deposition over larger areas. The choice of the reactor
`affects the physical and electrical properties of the
`as one of the limitations of PD is the
`plasma Si02,
`non-linear effect of a volumetric increase in size of
`the reactor on the process parameters
`such as sub(cid:173)
`strate temperature, RF power, gas ratio and total
`pressure. Due to the type of applications of this
`in EEROM[l6],
`insulator
`plasma Si02 as injector
`films for diffusion masks, interlayer dielectric[7] and
`as passivation layer, most of the above mentioned
`research papers have concentrated on the physical
`properties of the film like refractive index, density,
`stress, stoichiometry, etch rate, deposition rate, step
`coverage, and annealing behaviour.
`if
`The electrical properties which are important
`the film has to be used as an insulator
`in active
`devices like MOSFETs and CCDs, have been stud(cid:173)
`ied[18-20] and have been shown to compare well
`with the thermal oxides. Very low deposition rates of
`50-60 A/min using dilution with inert gas like He,
`have been used in these studies. One or two particular
`substrate temperatures have been chosen in these
`studies with not much reason indicated for the choice
`as also in the case of previous research. We have
`studied the electrical properties by depositing the film
`using pure SiH4 and N20 giving very high deposition
`
`1021
`
`Page 1 of 6
`
`SAMSUNG ET AL. EXHIBIT 1083
`Samsung et al. v. Elm 3DS Innovations, LLC
`IPR2016-00387
`
`

`

`1022
`
`R. K. CHANANA et al.
`
`temperature
`the substrate
`rate of 1400A/min at
`range has
`range of 20G-400°C. This temperature
`been chosen because it has already been shown that
`films deposited in this range have stable physical
`properties[15]. Using this rate and pure gases, the
`effect of long time low temperature annealing and
`plasma precleaning on the electrical properties have
`not yet been reported. Also, using such high rates,
`the physical properties have already been shown to
`compare well with those of thermal oxide[14] and as
`shown in the present study, the electrical properties
`are comparable too.
`Plasma precleaning of the silicon wafer surfaces
`has been performed using different gases like Ar, N2,
`H2' O2, CF4/50% H2oand their effect on the electrical
`properties have been studied by us. The importance
`of cleaning of wafers is more here because in PD, the
`film grows on the cleaned wafer surface which forms
`the Si~Si02 interface, unlike in thermal oxide where
`the silicon is consumed and the Si-Si02 interface
`moves into the silicon during oxidation so that
`the
`final temperature and oxidation time determine the
`interface. The importance of surface preparation
`have also been highlighted by Stasiak et al.[20].
`At the deposition rate used,
`it would require 4 s
`to deposit 100A thick films being used in today's
`devices and it is thus difficult to control
`the flow of
`gases, manually. Therefore, 700 A thick oxides have
`been studied, keeping in mind that
`the properties
`studied (e.g. Df, Dit)
`are not greatly affected by the
`thickness of the oxide[22]. Therefore,
`the results are
`very much applicable to thin films also. The results
`of the present study (e.g. Dit) are similar to the values
`for < 100A thin films[18]. Breakdown
`obtained
`strength has also been shown to remain the same for
`oxide thickness range of 25D-1579 A[19] to further
`support
`the validity of the results obtained for 700 A
`thick films.
`
`2. EXPERIMENTAL
`
`The reactor used in the present study is a parallel(cid:173)
`plate Reinberg type in high pressure configuration.
`The top electrode is supplied by the RF power at
`13.56 MHz frequency and the bottom electrode is
`grounded.
`The
`operating
`pressure
`range
`is
`0.133-1.33 mbar for deposition in this type of reactor.
`The reactor system, PD-10,
`is supplied by Samco
`International
`Inc., Kyoto,
`Japan. The bell-jar of
`the reactor
`is 30 cm in diameter with the bottom
`electrode 20 cm in diameter, provided with the heater
`to heat up to 400°C, and can rotate at 1 rpm. The
`electrode distance is variable from 2 to 4 cm. The RF
`power supply consists of 13.56 MHz crystal con(cid:173)
`trolled generator to supply 150W power with manual
`impedance matching provision. The vacuum line has
`a diffusion pump of 300 lis capacity and a rotary
`pump of 2001/min capacity.
`20 ml/min flowrate of Np and 1 ml/min flowrate
`of SiH4 was used to deposit the plasma Si02 film at
`
`1 mbar total pressure and 50 RF W power for 30 s
`giving an average deposition rate of 1400A/min in
`all depositions. Only the substrate temperature was
`varied from 200 to 400°C in steps of 50°C with
`the intention of studying its effect on the electrical
`properties of the oxide film. A typical deposition run
`involved the following steps after setting the sample
`on the substrate:
`
`1. The chamber is evacuated to 10-3 mbar using
`the rotary and diffusion pump.
`2. N20 is flown in at 20 ml/min using only the
`rotary pump and plasma is generated setting the
`power to 50 RF W.
`3. SiH4 is flown in at 1 ml/min for 30 s to given an
`oxide thickness of about 700 A.
`4. The power is then terminated and the chamber
`again evacuated to 10-3 mbar followed by Nz
`purging for 15min.
`
`run was preceded by plasma
`The above typical
`precleaning in various gases like Ar, Nz, Hz, Oz,
`and CF4/50% Hz. All
`the precleaning was done
`at 0.4 mbar total pressure, except the CF4/50% Hz
`precleaning in one experiment where the total press(cid:173)
`ure was 0.6 mbar. 50 RF W power was supplied
`during precleaning also and the substrate tempera(cid:173)
`ture was in the 200--400°Crange. The precleaning was
`performed for 15min. MOS capacitors were fabri(cid:173)
`cated on these films using high purity AI, evaporated
`through a clean metal mask to form 1mm diameter
`dots on the deposited SiOz film. Al was also evapor(cid:173)
`ated on the backside for ohmic contact. Similarly,
`MOS capacitors were also fabricated on the dry
`thermally grown oxide film, grown at 1100°C for
`24 min giving a thickness of approximately 800 A.
`The electrical properties of the thermal SiOz were
`studied to compare with the electrical properties of
`PECVD oxide in our
`laboratory conditions. The
`wafers used were p-type with (100) orientation and
`1-6 Q-cm resistivity. These wafers were cleaned
`by the RCA standard clean procedure[23] including
`1% HF solution
`dip for
`15 s before
`cleaning
`with standard
`clean-l
`solution. Postmetallization
`annealing was performed in Nz ambient for a total
`of 40 min at 450°C as a study parameter. 10 min
`annealing for
`fabricated devices is essential
`for
`good contact. However,
`in our case, further 30 min
`annealing has affected the electrical properties of the
`deposited film.
`studied were flatband
`The electrical properties
`fixed oxide charge density (Dr),
`inter(cid:173)
`voltage (Vfb),
`and the dielectric break(cid:173)
`face trap level density (Dit),
`down strength. A practical
`implementation of the
`methods used in finding these properties can be found
`in the authors' earlier work[24]. Hysterisis, by way of
`retrace on the CV-plotter, and bias stress stability
`were also studied for the devices. A bias stress of
`± 10V was applied for 1min each, keeping in mind
`the standard MOS technologies.
`
`Page 2 of 6
`
`

`

`Effect of plasma on PECVD oxide
`
`1023
`
`Table
`
`I. Yalues of the electrical properties
`
`at different
`of films deposited
`The wafers underwent
`
`substrate
`no plasma
`
`temperatures,
`precleaning
`
`before and after postmetallization
`
`annealing.
`
`Deposition
`
`temperature Cc)
`
`Electrical
`
`250300350400
`
`3.50.252.5-4.5
`
`
`
`
`3.516.013.75-15.5
`Unannealed14.0Unannealed
`Unannealed
`Annealed
`
`for 10min4.5
`7.14 x 1011
`
`
`x 1012-1.463.13 x 1OJ2
`x 1012
`-4.09
`
`for 10 min
`Annealed1.27 X 1OJ2Annealed5.94 X 10121.I7xlOJ29.53 X 10"
`
`
`
`
`for 10 min
`
`
`
`
`
`-7.13 X 1OJ2X 1012X 10126.04 X 1OJ2X 1OJ2X lOllX 10121.48 X 1OJ21.97 X 1OJ22.78 X 1012-5.83-1.54-3.94-1.12
`
`
`
`
`
`
`
`
`
`-1.573.43 X 1OJ2
`
`1.00 X lOll
`properties
`
`200
`
`3. RESULTS AND DISCUSSION
`
`At first, the electrical properties of the dry thermal
`oxide was studied to later on compare with the
`properties of PECVD oxide films. It was found that
`for~th~ally
`grown oxide, Vlb was -2.0V, Dr was
`3.00 x lOll
`Dit was 2.27 x lOll/cm2-eV
`charges/cm2,
`and an average dielectric breakdown strength of
`5.26 MV/cm in our laboratory conditions. Retrace on
`the CV-plotter showed no hysteresis and a bias stress
`of ± 10V for
`I min each showed no shift
`in Vfb,
`characterizing
`the usual
`charge
`stability of
`the
`thermal oxide. A typical I-V characteristic showed
`a steep rise in the current from I to 100 J.lA within
`IV change in the step voltage applied through a
`Hewlett-Packard
`pA meter/d.c.
`voltage
`source,
`mode14140B, signifying the breakd own. Hence, when
`I J.lA current was emitted through the I mm diameter
`dot capacitor, it was assumed that the breakdown has
`occurred.
`PECVD Si02 films grown directly after the conven(cid:173)
`tional RCA standard clean wet chemical cleaning
`process with the substrate temperature in the range
`of 200-400°C,
`and no annealing, showed high Vlb,
`of
`the order of 14V. Vfb
`for
`films deposited at
`400°C was -15.5 V. Dr values were large ranging
`from -1.57 x 1012
`to
`-7.13 x 1012
`charges/cm2
`charges/cm2• Dr for films deposited at the substrate
`temperature of 400°C was 6.04 x 1012 charges/cm2•
`Dit values were large tvo,
`ranging from 1.97 x
`to 1.00 x 1013cm-2-eV-I. Also,
`the
`1012cm-2_eV-1
`accumulation and inversion regions showed insta(cid:173)
`bility. A 10min postmetallization anneal at 450°C
`in N2 ambient showed large changes in the property
`values and this is summarized in Table 1. The
`values of the electrical properties in Table I shows
`the importance of annealing as compared to no
`ann..:aling.
`
`Gereth and Scherber[25] have studied the effect of
`plasma precleaning using different gases on the bias
`stability and hysteresis of the PECVD nitride films
`deposited using N2/SiH4
`gas mixture. Here,
`the
`authors have used Ar, N2, H2, O2 and CF4/50% H2
`gases for plasma precleaning the wafer surfaces with
`interesting filvourable results. Ar plasma precleaning
`was tried first for 15min on the wafers at
`three
`different
`substrate
`temperatures-250,
`300 and
`350°C, and PECVD oxide films deposited at the same
`individual
`temperatures. The electrical properties of
`the deposited films were evaluated after a 10min
`postmetallization
`anneal,
`followed by evaluation
`after a further 30 min annealing. These values are
`summarized in Table 2. A comparison of the values
`in Tables I and 2 after 10 min anneal favours plasma
`precleaning. Also, a further 30 min anneal improves
`increases the Dit values a little.
`the Dr values, but
`Long
`time,
`low temperature
`postmetallization
`annealing had previously been shown to change the
`properties of the film[15], particularly,
`loss of H20,
`SiOH and SiH groups had been observed. This is
`believed to affect the electrical properties as well. On
`performing retrace,
`the hysteresis that was present
`after a 10 min anneal was eliminated after a further
`30 min anneal. Gereth and Scherber[25] had sup(cid:173)
`ported Zebrst[26] in his theory that
`the hysteresis
`behaviour
`is related to the presence of the native
`oxide layer between Si3N4 and Si in their plasma
`nitride films. According to Zebrst, traps are located at
`the interface between the oxide and the nitride which
`charged and discharged through the native oxide
`during C-V measurements causing hysteresis of the
`C-V curve. Further,
`the charge transport occurs
`through tunneling as the native oxide layer is very
`thin. In our experiments,
`further 30 min annealing
`completely eliminated the hysteresis at ± 10 V bias
`sweep. This either puts the above theory of tunneling
`
`the
`of
`2. Yalues
`Table
`precleaning.
`The devices
`
`the
`of
`properties
`electrical
`fabricated were annealed
`
`after Ar plasma
`films deposited
`for 10 min and a further
`30 min
`
`Deposition
`
`temperature Cc)
`
`Electrical
`
`
`-3.37-2.68
`
`-2.47-2.19
`
`-4.53-2.02
`300350
`1.28 x 1011
`3.46 x 1011
`1.73 x 1011
`4.37 x 1011
`1.14 X 1012
`
`3.31 X 10112.91 X 1011
`
`4.79 X 10111.35 X 1011
`1.10 X 1011
`6.63 X 10114.14 X 101010 min annealing
`
`
`
`
`
`10 min annealing30 min annealing10min annealing
`properties
`30 min annealing
`30 min annealing
`
`250
`
`Page 3 of 6
`
`

`

`1024
`
`R. K. CHANANA et al.
`
`in question or the annealing removes the imperfec(cid:173)
`tions at the native oxide and PECVD oxide interface
`in our case. When bias stress of ± 10V was applied
`for 1min each, VIb shifted from 0.1 V to as much
`as 0.4 V characterizing bias stress instability. The
`dielectric breakdown strength of these films annealed
`for a total of 40 min was determined. Films deposited
`at substrate temperatures of 250, 300 and 350°C
`showed breakdown
`strengths of 6.07, 4.25 and
`9.39 MV/cm respectively. No particular
`trend was
`observed relative to the increase in the substrate
`temperature and therefore the dielectric breakdown
`strengths of PECVD oxide films can be said to vary
`in the range of 4-10 MV/cm. This has also been
`shown by Adams et al.[15].
`N2>Hz and Oz plasma precleaning for 15 min at the
`substrate temperature of 300°C was tried next after
`establishing that plasma precleaning and long time
`low temperature postmetallization annealing improve
`the electrical properties. VIb, Dr and Dit values of the
`films deposited after plasma precleaning using these
`gases and 40 min annealing are summarized in
`Table 3. It can be observed that while the electrical
`properties of the films deposited on Nz and Hz plasma
`precleaned wafers are comparable to those of dry
`thermal oxide films, there is a significant reduction
`in the values of the electrical properties of PECVD
`oxide films deposited on the Oz plasma precleaned
`wafers. This has also been reported by Gereth and
`Scherber[25] for their plasma nitride films precleaned
`these films on Oz plasma pre(cid:173)
`by Oz plasma. But
`cleaned wafers showed hysteresis behaviour on per(cid:173)
`forming retrace, and shift in Vib was observed upon
`bias stress application of ± 10 V for 10 min each of
`as much as 0.9 V. This makes Oz plasma prec1eaning,
`which adds diffusion-limited plasma oxide of up to
`45 A in 15 min[25], an unsuitable process. Figure 1
`shows the bias stress instability.
`PECVD SiOz films deposited on Nz plasma pre(cid:173)
`cleaned wafers showed no hysteresis on retrace but
`showed bias stress instability. With an application of
`10V bias stress for 1 min, the Vib shifted by 0.5 V
`towards the negative voltage axis of the C- V plot and
`the Vib shifted
`with a -IOV bias stress for 1 min,
`by 0.3 V towards the negative voltage axis of the
`C-V plot. This made Nz plasma precleaning also
`unsuitable.
`Films deposited on Hz plasma precleaned wafers
`show values of the electrical properties comparable to
`those of the dry thermally grown oxide. Also,
`the
`films show no hysteresis and no shift in VIb upon bias
`
`Table 3. Yalues of the electrical properties of films deposited after
`N" H, and 0, plasma precleaning at 300'C. The devices fabricated
`were annealed for 40 min
`
`Electrical properties
`
`(Y)
`Vtb
`Dr (Charges-cm-')
`Dit (cm-'ey-I)
`
`Plasma precleaning gas at 300'C
`N,
`H,
`0,
`-1.95
`-2.08
`-0.96
`3.09 x lOll
`4.38 x lOll
`7.17 x 1010
`1.97 X JOII
`5.12 X 1010
`1.13 X JOII
`
`l.1V FLAT BAND
`VOLTAGE WITHOUT
`BIAS STRESS
`
`O.9V SHIFT
`AT -lOV,
`lmin. BIAS
`STRESS
`
`wuz
`i:!u
`~«u
`
`-~-~-~-~-~-ili
`
`APPUED
`
`VOLTAGE
`
`0 ili~~
`(in VOLTS)
`
`~~~
`
`•
`
`Fig.!. C-Vplot
`on the
`fabricated
`of the MOS test structure
`showing shift
`in
`film after O2 plasma precleaning,
`deposited
`flatband
`voltage upon bias stress application.
`
`stress application. This makes Hz plasma precleaning
`a suitable process in the deposition of PECVD SiOz.
`Hz plasma is also known to etch SiOz[27] and
`Si[28-30]. So after etching the native oxide during
`prec1eaning, it can go on to etch the underlying Si
`resulting in roughening the Si surface and some H
`incorporation in the bulk[31]. To avoid this etching
`of the underlying Si, the time of exposure of the wafer
`to the Hz plasma needs to be controlled. This is
`difficult. A remedy for this difficulty was thought
`to
`be the use of CF4/50% Hz plasma in place of Hz
`plasma, which can eliminate Si etching due to high Hz
`content[32]. CF4/Hz
`plasma was tried next for 1min
`preceded by Nz plasma precleaning for 15min but
`with unfavourable end result. In the high pressure
`mode of the plasma reactor, etching is known to be
`performed by the neutr~l species[33]. In our case, the
`HF formed in the CF4/Hz
`plasma etches the native
`oxide without etching the underlying Si. Larger VIb
`(up to -4.0 V), Dr and Dit values were observed
`although there was no hysterisis or shift
`in VIb
`upon bias stress application. CF4/50% Hz plasma
`precleaning was followed by Oz plasma exposure of
`the wafer
`for 10 min at 0.6 mbar
`total pressure,
`in situ, on another wafer because Oz plasma preclean(cid:173)
`ing had shown to significantly improve the VIb' Dr
`and Dit values (Table 3) earlier. No diffusion-limited
`plasma oxide growth resulted as shown by the un(cid:173)
`changed values of the electrical properties of de(cid:173)
`posited films as compared to films deposited directly
`
`Page 4 of 6
`
`

`

`Effect of plasma on PECVD oxide
`
`1025
`
`plasma precleaning. This is possibly due
`after eF4/H2
`to the formation of thin carbon containing fluoro(cid:173)
`carbon film that does not allow 0 atoms to react with
`Si during O2 plasma exposure of the wafer[34]. The
`reactor configuration being in the high pressure mode
`did not allow support of ionic bombardment
`to clear
`the above film as it happens in the reactive ion etching
`low pressure mode due to the presence of negative
`self-bias on the insulated electrode.
`Choosing a substrate temperature for deposition
`has not been given enough importance in the past.
`In previous
`research one or
`two particular
`sub(cid:173)
`strate temperatures have been chosen for deposition
`with
`no
`particular
`reason
`indicated
`for
`the
`choice[14,16,18-20]. All
`the mentioned references
`only indicate a varying upper limit and a consensus
`exists that
`it is less than or equal to 400°C. Adams
`has systematically varied the substrate
`et at.[15]
`temperature
`from lO0-340oe and has studied the
`variation in film properties
`like refractive index,
`stress, etch rate, density and deposition rate. Most of
`these properties have shown a transition temperature
`of 200°C beyond which the properties either become
`stable or are better than for those below 200°C. Based
`on this,
`the lower limit on the choice of substrate
`temperature can be set to 200°C although,
`in view
`of these properties, a higher temperature can also
`be chosen. In the present work,
`the substrate tem(cid:173)
`perature has also been varied systematically from
`20Q-400oe in steps of 50°C, keeping in mind
`the 200°C as the lower limit from the works of
`Adams et at.[15], and the electrical properties have
`been studied. The deposited oxide on wafers with
`no plasma precleaning show a strong but random
`dependence of
`these properties on the substrate
`temperature as indicated in Table I. However,
`the
`following observations have to be made further in
`this regard:
`
`temperature =
`I. Vfb = - 2.19 V,
`deposition
`time = 40 min, Ar
`annealing
`250°C,
`total
`plasma precleaning used, value indicated in
`Table 2.
`temperature =
`2. Vfb = - 2.02 V,
`deposition
`time = 40 min, Ar
`annealing
`350°C,
`total
`plasma precleaning used, value indicated in
`Table 2.
`temperature =
`3. Vfb = - 1.95 V,
`deposition
`time = 40 min,
`annealing
`300°C,
`total
`N2
`plasma precleaning used, value indicated in
`Table 3.
`temperature =
`4. Vfb = - 2.08 V,
`deposition
`time = 40 min,
`annealing
`300°C,
`total
`H2
`plasma precleaning used, value indicated in
`Table 3.
`
`the same for depo(cid:173)
`All these Vfb values are almost
`sition temperatures of 250, 300 and 350°C. These
`V fb values reflect on the values of Dr and the cor(cid:173)
`responding Dit values are also very close to each
`other. Based on these observations,
`it can be stated
`
`SSE 36j7-G
`
`the substrate temperature can be chosen from
`that
`200-350oe, where 200Ge lower limit has been decided
`by the earlier argument
`from the works of Adams
`and provided long time low temperature
`et at.[15],
`postmetallization annealing and plasma precleaning
`has been performed.
`is essential
`Density close to 2.27 g/cm3 (pure Si02)
`in device applications as it is related to the physical
`and electrical properties, where lower density may
`give inferior properties. Densification may be needed,
`or will occur, only if the density of the deposited film
`is less than 2.27 g/cm3. The density of the deposited
`film in the works of Pan et at.[16] was low and after
`lOOOoepost-oxidation anneal
`in N2,
`the value ap(cid:173)
`proached 2.27 g/cm3, keeping in mind that only the
`stoichiometric films have to be considered (first two
`values in Table 2[16]). The density of the deposited
`film in the work of Adams et at.[15] was higher than
`2.27 g/cm3 and after long time (I h) low temperature
`(400°C) annealing in air, the film became less dense,
`has
`2.27 g/cm3• Hollahan[14]
`again approaching
`shown that when pure gases were used, as in our case,
`having high deposition rates,
`the densities of the
`deposited films were higher and after dilution with
`Ar, which lowers the deposition rate, the density of
`the film reduced drastically. This is contrary to the
`claim made by Batey and Tierney[19] that having
`lower deposition rates due to dilution with inert gas,
`gives denser films. Also, Adams et al.[15] used depo(cid:173)
`sition rates of 200-360 A/min (much higher com(cid:173)
`pared to 50-60 A/min rates in the works of Batey and
`Tierney[19]) involving 47.2% Ar dilution in the total
`gas flow and have achieved higher density films
`(> 2.27 g/cm3) which after long time low temperature
`annealing reduces to near 2.27 g/cm3• This supports
`the above mentioned contradiction.
`It has also been
`reported[15] that the density is nearly independent of
`all deposition variables, except power, and high film
`densities are observed for low powers. The authors in
`the present work have used 50 RF W power, which
`is low. Annealing affects the density significantly
`and in order to retain the low temperature advantage,
`long time low temperature postmetallization anneal(cid:173)
`ing is an alternative to high temperature postoxida(cid:173)
`tion anneal. The authors have taken this approach
`and have shown the importance of postmetallization
`annealing for a further 30 min at 450°C in N2 ambient
`by evaluating the values of the properties after 10 min
`annealing, which is usually needed for good contact.
`The density will approach 2.27 g/cm3 anyway and
`use of low power and long time low temperature
`annealing seems to be the method for achieving that.
`With this in view, the density of the films processed
`in the present study is expected to be near 2.27 g/cm3•
`
`4. CONCLUSION
`
`It is concluded from the experimental results that
`PEeVD Si02 deposited using pure N20/SiH4 mixture
`could form a suitable gate material
`for MOSFETs
`
`Page 5 of 6
`
`

`

`1026
`
`R. K. CHANANA et al.
`
`and CCDs as the physical properties[14-15] and the
`electrical properties are found to be comparable to
`the dry thermally grown oxide with bias stability and
`no hysteresis present. H2 plasma precleaning and long
`time (40 min) low temperature
`(450°C) postmetal(cid:173)
`lization annealing is essential to achieve this. Another
`important conclusion that is drawn from the results
`and analysis is that the substrate temperature can be
`chosen from the 200-350°C range provided plasma
`precleaning and long time low temperature post(cid:173)
`metallization annealing is performed. Increased pro(cid:173)
`cess complexity and skill
`requirement
`and less
`throughput are some of the problems, but the advan(cid:173)
`tage of low temperature processing is enormous in
`today's VLSI and ULSI applications. RCA standard
`clean process of cleaning silicon wafers could be
`supplemented with some of the emerging dry cleaning
`techniques[32,35].
`
`REFERENCES
`
`1. D. J. D. Thomas, Physica status soUdi 3, 2261 (1963).
`2. H. J. Queisser and P. G. G. van Loon, J. appl. Phys. 35,
`3066 (1964).
`3. R. J. Jaccodine and C. M. Drum, Appl. Phys. Left. 8,
`29 (1966).
`4. 1. R. Sanders and P. S. Dobson, Phil. Mag. 20, 881
`(1969).
`5. E. Bassous, H. N. Yu and V. Maniscalco, J. electro(cid:173)
`chem. Soc. 123, 1729 (1976).
`6. M. J. Rand, J. Vacuum Sci. Technol. 16, 420 (1979).
`7. Evert P. G. T. van de Yen, SoUd St. Technol. 24, 167
`(1981).
`8. H. F. Sterling and R. C. G. Swann, SoUd-St. Electron.
`8, 753 (1965).
`9. R. J. Joyce, H. F. Sterling and J. H. Alexander, Thin
`SoUd Films 1, 481 (1967/68).
`10. S. P. Mukherjee and P. E. Evans, Thin SoUd Films 14,
`105 (1972).
`11. D. R. Secrist and J. D. Mackenzie, J. electrochem. Soc.
`113, 914 (1966).
`
`12. S. W. Ing Jr and W. Davern, J. electrochem. Soc. 112,
`284 (1965).
`13. D. Kuppers, J. Koenings and H. Wilson, J. electrochem.
`Soc. 123, 1079 (1976).
`14. J. R. Hollhan, J. electrochem. Soc. 126, 930 (1979).
`15. A. C. Adams, F. B. Alexander, C. D. Capio and T. E.
`Smith, J. electrochem. Soc. 128, 1545 (1981).
`16. P. Pan, L. A. Nesbit, R. W. Douse and R. T. Gleason,
`J. electrochem. Soc. 132,2012 (1985).
`17. T. T. Chau, S. R. Mejia and K. C. Kao, Can. J. Phys.
`69, 165 (1991).
`18. J. Batey, E. Tierney and T. N. Nguyen, IEEE Electron
`Device Left. 8, 148 (1987).
`19. J. Batey and E. Tierney, J. appl. Phys. 60, 3136 (1986).
`20. J. Stasiak, J. Batey, E. Tierney and J. Li, IEEE Electron
`Device Left. 10, 245 (1989).
`21. H. Dun, P. Pan, F. R. White and R. W. Douse,
`J. electrochem. Soc. 128, 1556 (1981).
`22. S. M. Sze, Physics of Semiconductor Devices, 2nd edn,
`p. 390. Wiley-Interscience, New York (1981).
`23. W. Kern, J. electrochem. Soc. 137, 1887 (1990).
`24. R. K. Chanana, R. Dwivedi and S. K. Srivastava,
`SoUd-St. Electron. 34, 1463 (1991).
`25. R. Gereth and W. Scherber, J. electrochem. Soc. 119,
`1248 (1972).
`IEEE European Meeting,
`26. M. Zerbst,
`Munich, March (1969).
`27. R. Heinecke, SoUd-St. Electron. 19, 1039 (1976).
`28. A. P. Webb and S. Veprek, Chem. Phys. Left. 62, 173
`(1979).
`29. S. Veprek and V. Marecek, SoUd-St. Electron. 11, 683
`(1968).
`30. S. Veprek and S. A. Saratt, Plasma Chem. Plasma
`Process. 2, 233 (1982).
`31. K. Nagashima, 1. Tagima and M. Yamamoto, Appl.
`Phys. Left. 58, 1378 (1991).
`32. R. K. Chanana, R. Dwivedi and S. K. Srivastava,
`SoUd-St. Electron. 35, 1417 (1992).
`33. N. G. Einspruch and D. M. Brown, VLSI Electronics,
`Microstructure Science, Vol. 8, p.257. Academic Press
`(1984).
`34. N. G. Einspruch and D. M. Brown, VLSI Electronics,
`Microstructure Science, Vol. 8, p.234. Academic Press
`(1984).
`35. B. E. Deal, M. A. McNeilly, D. B. Kao and J. M.
`deLarios, SoUd St. Technol. 33, 73 (1990).
`
`Invited paper,
`
`Page 6 of 6
`
`