Digital Logic
`and
`Computer Design
`
`M. MORRIS MANO
`
`Professor of Engineering
`California State University, Los Angeles
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`f
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`Prentice-Hall, Inc., Englewood Cliffs, N.J. 07632
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`Aisin Seiki Exhibit 1014
`Page 1 of 20
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`

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`Library of Congress Cataloging in Publication Data
`
`(dale)
`MANO, M. MORRIS
`Digital logic and computer design.
`
`Bibliography: p.
`Includes index.
`1.-Electronic digital computers. 2.-Logic
`circuits. 3.-Digital integrated circuits.
`4.-Logic design.
`I.-Title.
`TK7888.3.M345
`621.3815,3
`ISBN 0-13-214510-3
`
`78-21462
`
`©1979 by Prentice-Hall, Inc., Englewood Cliffs, N.J. 07632
`
`All rights reserved. No part of this book
`may be reproduced in any form or
`by any means without permission in writing
`from the publisher.
`
`Printed in the United States of America
`
`10 9 8 7
`
`Editorial/ Production Supervision by Lynn S. Frankel
`Cover Design by Edsal Enterprise
`Manufacturing Buyer: Gordon Osbourne
`
`PRENTICE-HALL INTERNATIONAL, INC., London
`PRENTICE-HALL OF AUSTRALIA PTY. LIMITED, Sydney
`PRENTICE-HALL OF CANADA, LTD., Toronto
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`PRENTICE-HALL OF JAPAN, INC., Tokyo
`PRENTICB-HALL OF SOUTHEAST ASIA PTE. LTD., Singapore
`WHITEHALL BOOKS LIMITED, Wellington, New Zealand
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`Aisin Seiki Exhibit 1014
`Page 2 of 20
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`Contents
`
`PREFACE
`
`1
`
`BINARY SYSTEMS
`
`viii
`
`1
`
`1-1
`1-2
`1-3
`1-4
`1-5
`1 - 6
`1-7
`1-8
`1-9
`
`I
`
`Digital Computers and Digital Systems
`Binary Numbers 4
`Number Base Conversion 6
`Octal and Hexadecimal Numbers 9
`Complements 10
`Binary Codes 16
`Binary Storage and Registers 22
`Binary Logic 25
`Integrated Circuits 30
`References 31
`Problems 31
`
`2
`
`BOOLEAN ALGEBRA AND LOGIC GATES
`
`34
`
`2-1
`2-2
`2-3
`
`2-4
`2-5
`2-6
`2-7
`2-8
`
`Basic Definitions 34
`Axiomatic Definition of Boolean Algebra 36
`Basic Theorems and Properties
`of Boolean Algebra 39
`Boolean Functions 43
`Canonical and Standard Forms 47
`Other Logic Operations 53
`Digital Logic Gates 56
`IC Digital Logic Families 60
`References 68
`Problems 68
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`MEMORY UNIT
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`0 0 0 0 0 0 0 0 0 0
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`sum
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`0 0 1 1 1 0 0 0 0 1
`
`operand 2
`
`0 0 0 1 0 0 0 0 1 0
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`0 0 0 1 0 0 0 0 1 0 R 1
`
`Digital logic
`circuits for
`binary addition
`
`0 1 0 0 1 0 0 0 1 1 R 3
`
`0 0 1 1 1 0 0 0 0 1 R 2
`
`PROCESSOR UNIT
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`Figure 1-3 Example of binary information processing
`
`processor registers can be transferred back into a memory register for storage until
`needed again. The diagram shows the contents of two operands transferred from
`two memory registers into R1 and R2. The digital logic circuits produce the sum,
`which is transferred to register R3. The contents of R3 can now be transferred
`back to one of the memory registers.
`The last two examples demonstrated the information flow capabilities of a
`digital system in a very simple manner. The registers of the system are the basic
`elements for storing and holding the binary information. The digital logic circuits
`process the information. Digital logic circuits and their manipulative capabilities
`are introduced in the next section. The subject of registers and register transfer
`operations is taken up again in Chapter 8.
`
`•
`
`1-8 BINARY LOGIC
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`Binary logic deals with variables that take on two discrete values and with
`J|||S operations that assume logical meaning. The two values the variables take may be
`"ll&r called by different names (e.g., true and false, yes and no, etc.), but for our purpose
`Hlfeit .is' convenient to think in terms of bits and assign the values of 1 and 0. Binary
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`26
`
`BINARY SYSTEMS
`
`CH. 1
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`logic is used to describe, in a mathematical way, the manipulation and processing
`of binary information. It is particularly suited for the analysis and design of digital
`systems. For example, the digital logic circuits of Fig. 1-3 that perform the binary
`arithmetic are circuits whose behavior is most conveniently expressed by means of
`binary variables and logical operations. The binary logic to be introduced in this
`section is equivalent to an algebra called Boolean algebra. The formal presentation
`of a two-valued Boolean algebra is covered in more detail in Chapter 2. The
`purpose of this section is to introduce Boolean algebra in a heuristic manner and
`relate it to digital logic circuits and binary signals.
`
`Definition of Binary Logic
`
`Binary logic consists of binary variables and logical operations. The variables are
`designated by letters of the alphabet such as A, B, C, x, y, z, etc., with each
`variable having two and only two distinct possible values; 1 and 0. There are three
`basic logical operations: AND, OR, and NOT.
`
`1. AND: This operation is represented by a dot or by the absence of an
`operator. For example, x • y = z or xy = z is read "x AND y is equal to
`z." The logical operation AND is interpreted to mean that z = 1 if and
`only if JC = 1 and y = \ \ otherwise z = 0. (Remember that x, y, and z are
`binary variables and can be equal either to 1 or 0, and nothing else.)
`2. OR: This operation is represented by a plus sign. For example, x + y = z
`is read "x OR 7 is equal to z," meaning that z = I if x = I or if y = I or if
`both x = 1 and.y = 1. If both x = 0 and 7 = 0, then z = 0.
`
`3. NOT: This operation is represented by a prime (sometimes by a bar). For
`example, JC' = z (or 3c = z) is read "x not is equal to z," meaining that z is
`what x is not. In other words, if x = 1, then z = 0; but if x = 0, then
`z = 1.
`
`Binary logic resembles binary arithmetic, and the operations AND and OR
`have some similarities to multiplication and addition, respectively. In fact, the
`symbols used for AND and OR are the same as those used for multiplication and
`addition. However, binary logic should not be confused with binary arithmetic.
`One should realize that an arithmetic variable designates a number that may
`consist of many digits. A logic variable is always either a I or a 0. For example, in
`binary arithmetic we have 1 + 1 = 10 (read: "one plus one is equal to 2"), while in
`binary logic we have 1 + 1 = 1 (read: "one OR one is equal to one").
`For each combination of the values of x and 7, there is a value of z specificed
`by the definition of the logical operation. These definitions may be listed in a
`compact form using truth tables. A truth table is a table of all possible combina­
`tions of the variables showing the relation between the values that the variables
`may take and the result of the operation. For example, the truth tables for the
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`TABLE 1-6 Truth tables of logical operations
`
`AND
`
`x y
`
`0 0
`0
`1
`1 0
`1
`1
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`x-y
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`0
`0
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`OR
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`x + y
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`x y
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`0 0
`0 I
`0
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`I
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`NOT
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`x'
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`0
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`0
`1
`
`operations AND and OR with variables x and_y are obtained by listing all possible
`values that the variables may have when combined in pairs. The result of the
`operation for each combination is then listed in a separate row. The truth tables
`for AND, OR, and NOT are listed in Table 1-6. These tables clearly demonstrate
`the definitions of the operations.
`
`Switching Circuits and Binary Signals
`
`The use of binary variables and the application of binary logic are demonstrated by
`the simple switching circuits of Fig. 1-4. Let the manual switches A and B
`represent two binary variables with values equal to 0 when the switch is open and 1
`when the switch is closed. Similarly, let the lamp L represent a third binary
`variable equal to 1 when the light is on and 0 when off. For the switches in series,
`the light turns on if A and B are closed. For the switches in parallel, the light turns
`on if A or B is closed. It is obvious that the two circuits can be expressed by means
`of binary logic with the AND and OR operations, respectively:
`
`L = A • B
`L = A + B
`
`for the circuit of Fig. l-4(a)
`for the circuit of Fig. l-4(b)
`
`Electronic digital circuits are sometimes called switching circuits because they
`behave like a switch, with the active element such as a transistor either conducting
`(switch closed) or not conducting (switch open). Instead of changing the switch
`manually, an electronic switching circuit uses binary signals to control the conduc­
`tion or nonconduction state of the active element. Electrical signals such as
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`(a) Switches in series — logic AND
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`(b) Switches in parallel —logic OR
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`Figure 1-4 Switching circuits that demonstrate binary logic
`
`27
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`Page 6 of 20
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`Figure 1-5 Example of binary signals
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`Tolerance
`allowed
`for logic-1
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`Tolerance
`allowed
`for logic- 0
`
`voltages or currents exist throughout a digital system in either one of two recogniz­
`able values (except during transition). Voltage-operated circuits, for example,
`respond to two separate voltage levels which represent a binary variable equal to
`logic-1 or logic-0. For example, a particular digital system may define logic-1 as a
`signal with a nominal value of 3 volts, and logic-0 as a signal with a nominal value
`of 0 volt. As shown in Fig, 1-5, each voltage level has an acceptable deviation from
`the nominal. The intermediate region between the allowed regions is crossed only
`during state transitions. The input terminals of digital circuits accept binary signals
`within the allowable tolerances and respond at the output terminal with binary
`signals that fall within the specified tolerances.
`
`Logic Gates
`
`Electronic digital circuits are also called logic circuits because, with the proper
`input, they establish logical manipulation paths. Any desired information for
`computing or control can be operated upon by passing binary signals through
`various combinations of logic circuits, each signal, representing a variable and
`carrying one bit of information. Logic circuits that perform the logical operations
`of AND, OR, and NOT are shown with their symbols in Fig. 1-6. These circuits,
`called gates, are blocks of hardware that produce a logic-1 or logic-0 output signal
`if input logic requirements are satisfied. Note that four different names have been
`used for the same type of circuits: digital circuits, switching circuits, logic circuits,
`and gates. All four names are widely used, but we shall refer to the circuits as
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`Page 7 of 20
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`( a ) Two-input A N D gate
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`( b ) Two-input O R gate
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`( c ) N O T gate or inverter
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`G = A
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`(d) Three-input AND gate
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`B C -\- D
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`Figure 1-6 Symbols for digital logic circuits
`
`AND, OR, and NOT gates. The NOT gate is sometimes called an inverter circuit
`since it inverts a binary signal.
`The input signals x and y in the two-input gates of Fig. 1-6 may exist in one
`of four possible states: 00, 10, 11, or 01. These input signals are shown in Fig. 1-7,
`together with the output signals for the AND and OR gates. The liming diagrams
`in Fig. 1-7 illustrate the response of each circuit to each of the four possible input
`binary combinations. The reason for the name "inverter" for the NOT gate is
`apparent from a comparison of the signal x (input of inverter) and that of x'
`(output of inverter).
`AND and OR gates may have more than two inputs. An AND gate with
`three inputs and an OR gate with four inputs are shown in Fig. 1-6. The
`three-input AND gate responds with a logic-1 output if all three input signals are
`logic-1. The output produces a logic-0 signal if any input is logic 0. The four input
`OR gate responds with a logic-1 when any input is a logic-1. Its output becomes
`logic-0 if all input signals are logic-0.
`The mathematical system of binaiy logic is better known as Boolean, or
`switching, algebra. This algebra is conveniently used to describe the operation of
`complex networks of digital circuits. Designers of digital systems use Boolean
`algebra to transform circuit diagrams to algebraic expressions and vice versa.
`Chapters 2 and 3 are devoted to the study of Boolean algebra, its properties, and
`manipulative capabilities. Chapter 4 shows how Boolean algebra may be used to
`express mathematically the interconnections among networks of gates.
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`Input-output signals for gates (a), (b), and (c) of Fig. 1-6
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`Aisin Seiki Exhibit 1014
`Page 8 of 20
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`

`
`SEC 2-3
`
`BASIC THEOREMS AND PROPERTIES OF BOOLEAN ALGEBRA
`
`39
`
`6. Postulate 6 is satisfied because the two-valued Boolean algebra has two
`distinct elements 1 and 0 with 1 ^ 0.
`
`We have just established a two-valued Boolean algebra having a set of two
`elements, 1 and 0, two binary operators with operation rules equivalent to the
`AND and OR operations, and a complement operator equivalent to the NOT
`operator. Thus, Boolean algebra has been defined in a formal mathematical
`manner and has been shown to be equivalent to the binary logic presented
`heuristically in Section 1-8. The heuristic presentation is helpful in understanding
`the application of Boolean algebra to gate-type circuits. The formal presentation is
`necessary for developing the theorems and properties of the algebraic system. The
`two-valued Boolean algebra defined in this section is also called "switching
`algebra" by engineers. To emphasize the similarities between two-valued Boolean
`algebra and other binary systems, this algebra was called "binary logic" in Section
`1-8. From here on, we shall drop the adjective "two-valued" from Boolean algebra
`in subsequent discussions.
`
`2-3 BASIC THEOREMS AND PROPERTIES
`OF BOOLEAN ALGEBRA
`
`Duality
`
`The Huntington postulates have been listed in pairs and designated by part (a) and
`part (b). One part may be obtained from the other if the binary operators and the
`identity elements are interchanged. This important property of Boolean algebra is
`called the duality principle. It states that every algebraic expression deducible from
`the postulates of Boolean algebra remains valid if the operators and identity
`elements are interchanged. In a two-valued Boolean algebra, the identity elements
`and the elements of the set B are the same: 1 and 0. The duality principle has
`many applications. If the dual of an algebraic expression is desired, we simply
`injprrli.ipof OR nnd AKi 11 operators and replace I's by O's and O's by I's.
`
`Basic Theorems
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`Table 2-1 lists six theorems of Boolean algebra and four of its postulates. The
`notation is simplified by omitting the • whenever this does not lead to confusion.
`The theorems and postulates listed are the most basic relationships in Boolean
`algebra. The reader is advised to become familiar with them as soon as possible.
`The theorems, like the postulates, are listed in pairs; each relation is the dual of the
`one paired with it. The postulates are basic axioms of the algebraic structure and
`need no proof. The theorems must be proven from the postulates. The proofs of
`the theorems with one variable are presented below. At the right is listed the
`number of the postulate which justifies each step of the proof.
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`Page 9 of 20
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`TABLE 2-1 Postulates and theorems of Boolean algebra
`
`Postulate 2
`Postulate 5
`Theorem 1
`Theorem 2
`Theorem 3, involution
`Postulate 3, commutative
`Theorem 4, associative
`Postulate 4, distributive
`Theorem 5, DeMorgan
`Theorem 6, absorption
`
`(a) ;c + 0 = JC
`(a) x + x' = \
`(a) x + x = x
`(a) x + 1 = 1
`(x'y = x
`(a) x + y = y + x
`ri
`(a) x + (y + z) = (x + y) + z
`(a) JC{>' + z) = xy + xz
`(a) (JC + y)' = JC>'
`(a) j.' t
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`(b) .x • 1 = x
`(b) JC • x' = 0
`(b) x • x = x
`(b) JC • 0 = 0
`
`(h) xy = yx
`(b) x(yz) = (xy)z
`(b) x + yz = (x + y)(x + z)
`(b) (xy)' ~x'+y'
`(b) X(JC + >>) = JC
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`THEOREM 1(a); x
`
`x + x = (x + x) • 1
`= (x + x)(x + JC')
`= x + xx'
`= JC + 0
`= JC
`
`by postul
`
`5(a)
`4(b)
`5(b)
`2(a)
`
`THEOREM 1(b): JC
`
`JC = JC.
`
`x • JC = JCJC + 0
`= XX + xx'
`= JC(JC + JC')
`= JC • 1
`
`by postulate: 2(a)
`5(b)
`4{a)
`5(a)
`2(b)
`
`Note that theorem 1(b) is the dual of theorem 1(a) and that each step of the
`proof in part (b) is the dual of part (a). Any dual theorem can be similarly derived
`from the proof of its corresponding pair.
`
`THEOREM 2(a): JC + 1 = 1.
`
`JC + 1 = 1 • (JC + 1)
`= (JC +'JC')(JC + 1)
`= JC + JC' • 1
`= X + X'
`
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`by postulate: 2(b)
`5(a)
`4(b)
`2(b)
`5(a)
`
`THEOREM 2(b): JC • 0 = 0 by duality.
`
`THEOREM 3: (JC')' = x. From postulate 5, we have x + x' = I and JC • JC'
`= 0, which defines the complement of JC. The complement of JC' is JC and is also
`(JC')'. Therefore, since the complement is unique, we have that (JC')' = x.
`
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`Aisin Seiki Exhibit 1014
`Page 10 of 20
`
`

`
`SEC. 2-3
`
`BASIC THEOREMS AND PROPERTIES OF BOOLEAN ALGEBRA
`
`41
`
`The theorems involving two or three variables may be proven algebraically from
`the postulates and the theorems which have already been proven. Take, for
`example, the absorption theorem.
`
`THEOREM 6(a): x + xy = x.
`
`x + xy = x • \ + xy
`= x ( \ + y )
`= x(y + i)
`= x- \
`
`by postulate 2(b)
`by postulate 4(a)
`by postulate 3(a)
`by theorem 2(a)
`by postulate 2(b)
`
`THEOREM 6(b): xix + j) = x by duality.
`
`The theorems of Boolean algebra can be shown to hold true by means of
`truth tables. In truth tables, both sides of the relation are checked to yield identical
`results for all possible combinations of variables involved. The following truth
`table verifies the first absorption theorem.
`
`r
`x
`0
`0
`1
`1
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`y
`0
`1
`0
`1
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`1
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`The algebraic proofs of the associative law and De Morgan's theorem are long and
`will not be shown here. However, their validity is easily shown with truth tables.
`For example, the truth table for the first De Morgan's theorem {x + y)' = x'y' is
`shown below.
`
`x
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`0
`1
`1
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`y
`o
`1
`0
`1
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`x + y
`0
`1
`1
`1
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`Operator Precedence
`
`The operator precedence for evaluating Boolean expressions is (1) parentheses, (2)
`NOT. C) AMP, and (<1)
`In other words, the expression inside the parentheses
`must be evaluated before all other operations. The next operation that holds
`precedence is the complement, then follows the AND, and finally the OR. As an
`example, consider the truth table for De Morgan's theorem. The left side of the
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`Page 11 of 20
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`LA
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`42
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`BOOLEAN ALGEBRA AND LOGIC GATES
`
`expression is (x + /)'. Therefore, the expression inside the parentheses is evaluated
`first and the result then complemented. The right side of the expression is x'y'.
`Therefore, the complement of x and the complement of y are both evaluated first
`and the result is then ANDed. Note that in ordinary arithmetic the same prece­
`dence holds (except for the complement) when multiplication and addition are
`replaced by AND and OR, respectively.
`
`Venn Diagram
`
`A helpful illustration that may be used to visualize the relationships among the
`variables of a Boolean expression is the Venn diagram. This diagram consists of a
`rectangle such as shown in Fig. 2-1, inside of which are drawn overlapping circles,
`one for each variable. Each circle is labeled by a variable. We designate all points
`inside a circle as belonging to the named variable and all points outside a circle as
`not belonging to the variable. Take, for example, the circle labeled x. If we are
`inside the circle, we say that x = I; when outside, we say x = 0. Now, with two
`overlapping circles, there are four distinct areas inside the rectangle: the area not
`belonging to either x or y (x'y1), the area inside circle y but outside x (x'y), the
`area inside circle x but outside 7 (xy'), and the area inside both circles {xy).
`Venn diagrams may be used to illustrate the postulates of Boolean algebra or
`to show the validity of theorems. Figure 2-2, for example, illustrates that the area
`belonging to xy is inside the circle x and therefore x + xy = x. Figure 2-3
`illustrates the distributive law x(y + z) = xy + xz. In this diagram we have three
`overlapping circles, one for each of the variables x, y, and z. It is possible to
`distinguish eight distinct areas in a three-variable Venn diagram. For this particu­
`lar example, the distributive law is demonstrated by noting that the area intersect­
`ing the circle x with the area enclosing y or z is the same area belonging to xy
`or xz.
`
`xy'
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`Figure 2-1 Venn diagram for two variables
`
`Figure 2-2 Venn diagram illustration x = xy + x
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`Aisin Seiki Exhibit 1014
`Page 12 of 20
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`Aisin Seiki Exhibit 1014
`Page 13 of 20
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`Aisin Seiki Exhibit 1014
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`Aisin Seiki Exhibit 1014
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`
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`
`(cid:3)(cid:38)(cid:82)(cid:83)(cid:92)(cid:85)(cid:76)(cid:74)(cid:75)(cid:87)(cid:3)(cid:38)(cid:68)(cid:87)(cid:68)(cid:79)(cid:82)(cid:74)(cid:3)(cid:11)(cid:20)(cid:28)(cid:26)(cid:27)(cid:3)(cid:87)(cid:82)(cid:3)(cid:83)(cid:85)(cid:72)(cid:86)(cid:72)(cid:81)(cid:87)(cid:12)
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`Aisin Seiki Exhibit 1014
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