Trials@uspto.gov
`571-272-7822
`
`
`
`Paper 10
`Date Entered: June 8, 2016
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`
`
`
`
` DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00290
`Patent 5,965,924
`____________
`
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`McNAMARA, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571-272-7822
`
`
`
`Paper 10
`Date Entered: June 8, 2016
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`
`
`
`
` DSS TECHNOLOGY MANAGEMENT, INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00290
`Patent 5,965,924
`____________
`
`
`
`
`Before BRYAN F. MOORE, BRIAN J. McNAMARA, and
`MINN CHUNG, Administrative Patent Judges.
`
`McNAMARA, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2016-00290
`Patent 5,965,924
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`BACKGROUND
`
`Intel Corporation (“Petitioner”) filed a petition, Paper 2 (“Pet.”), to
`institute an inter partes review of claims 7–12, 15, and 17 (the “challenged
`claims”) of U.S. Patent No. 5,965,924 (“the ’924 Patent”). 35 U.S.C. § 311.
`DSS Technology Management, Inc. (“Patent Owner”) waived filing a
`Preliminary Response. Paper 7. We have jurisdiction under 37 C.F.R.
`§ 42.4(a) and 35 U.S.C. § 314, which provides that an inter partes review
`may not be instituted unless the information presented in the Petition “shows
`that there is a reasonable likelihood that the petitioner would prevail with
`respect to at least 1 of the claims challenged in the petition.” Having
`considered the arguments and the associated evidence presented in the
`Petition, for the reasons described below, we institute inter partes review of
`claims 7–12, 15 and 17.
`
`
`REAL PARTIES IN INTEREST
`Petitioner identifies itself as the only real party-in-interest. Pet. 5.
`
`PENDING LITIGATION
`The parties state that Patent Owner has asserted ’924 Patent in the
`following litigation: (1) DSS Technology Management, Inc. v. Intel Corp.,
`No. 6:15-CV-130-RWS (E.D. Tex. filed Feb. 16, 2015); and (2) DSS
`Technology Management, Inc. v. Qualcomm Inc., No. 6:15-CV-692-JRG
`(E.D. Tex. filed July 16, 2015). Pet. 5; Paper 6, at 2.
`Petitioner notes that it has filed a separate petition for inter partes
`review of claims 1–6, 13, 14, and 16 of the ’924 Patent. Pet. 5. That
`proceeding has been designated IPR2016-00289. Paper 6, at 3.
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`THE ’924 PATENT (EXHIBIT 1101)
`The ’924 Patent relates to semiconductor fabrication in general, and in
`particular concerns a metal plug local interconnect that is formed in the same
`process of forming metal plugs that are already designed as sub-metal
`plugged contacts. Ex. 1101, col. 1, ll. 9–11. The ’924 Patent discloses that
`in semiconductor fabrication, it is often necessary to make a local
`interconnect between a gate polysilicon layer to N+ or P+ diffusion regions.
`Id. at col. 1, ll. 16–17. According to the ’924 Patent, conventionally such
`local interconnects were fabricated using buried contacts, as shown in
`Figures 1A and 1B of the ’924 Patent (id. at col. 1, l. 25–col. 2, l. 11) or with
`a metallic local interconnect strap to shunt from a gate polysilicon to a
`diffusion region, as illustrated in Figures 2A and 2B of the ’924 Patent (id. at
`col. 2, l. 12–41).
`The ’924 Patent discloses a semiconductor structure in which a
`diffusion region is formed in a silicon substrate and a polysilicon gate is
`formed on the top surface of the silicon substrate adjacent to, but not
`contacting, the diffusion region. Ex. 1101, col. 3, ll. 1–6, 14–18. A layer of
`insulating material is then deposited on top of the polysilicon gate and the
`diffusion region. Id. at col. 3, ll. 6–7, 19–20. A via opening is formed in the
`insulating material to expose a portion of the polysilicon gate and a portion
`of the diffusion region. Id. at col. 3, ll. 7–8, 20–22. An electrically
`conducting material is deposited to at least partially fill the via opening to
`provide an electrical connection between the polysilicon gate and the
`diffusion region. Id. at col. 3, ll. 8–11, 23–27.
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`ILLUSTRATIVE CLAIM
`7. A method of forming a local interconnect in a semiconductor
`structure, comprising the step of:
`depositing an electrically conducting material in a via exposing at
`least a portion of a gate, a sidewall spacer adjacent to said gate
`and a portion of a diffusion region such that said electrically
`conducting material
`contacts
`and provides
`electrical
`communication between said gate and said diffusion region, said
`semiconductor structure comprising said diffusion region in a
`silicon substrate, said gate being on said substrate juxtaposed to
`but not contacting said diffusion region, said sidewall spacer
`being disposed above said diffusion region, said via being in an
`insulating material on said gate.
`
`ART CITED IN PETITIONER’S CHALLENGES
`
`Petitioner cites the following references in its challenges to
`patentability:
`
`Sakamoto, U.S. Patent No. 5,475,240 issued Dec. 12, 1995, Ex. 1103
`(“Sakamoto”); and
`
`Cederbaum et al., U.S. Patent No. 5,100,817 issued Mar. 31, 1992,
`Ex. 1104 (“Cederbaum”).
`
`CHALLENGES ASSERTED IN PETITION
`Claims
`Statutory Basis
`Challenge
`Anticipation by
`7–9, 15, and 17
`35 U.S.C. § 102(e)
`Sakamoto
`Obviousness over the
`combination of
`Sakamoto and
`Cederbaum
`
`35 U.S.C. § 103
`
`10–12
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`CLAIM CONSTRUCTION
`The ’924 Patent issued from an application that was a continuation of
`Appl. No. 08/561,951 filed on Nov. 22, 1995. Thus, the ’924 Patent is
`expired. We construe the claims of an expired patent in accordance with the
`standard set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005)
`(en banc). See In re Rambus, 694 F.3d 42, 46 (Fed. Cir. 2012) (“While
`claims are generally given their broadest possible scope during prosecution,
`the Board’s review of the claims of an expired patent is similar to that of a
`district court’s review.”). “In determining the meaning of the disputed claim
`limitation, we look principally to the intrinsic evidence of record, examining
`the claim language itself, the written description, and the prosecution
`history, if in evidence.” DePuy Spine, Inc. v. Medtronic Sofamor Danek,
`Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips, 415 F.3d at
`1312–17). Only those terms that are in controversy need to be construed,
`and only to the extent necessary to resolve the controversy. Vivid Techs.,
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`The only term Petitioner proposes we construe is “diffusion region in
`a silicon substrate.” Pet. 23–26. Petitioner proposes that we construe this
`term to mean “conductive terminal region, such as a source or drain, that
`contains dopants implanted in the silicon substrate.” Id. at 26. Petitioner
`states that in the co-pending litigation Patent Owner has proposed “diffusion
`region in a silicon substrate” be construed to mean a “conductive terminal
`region such as a source or drain in a silicon substrate.” Id. at 24. Petitioner
`cites the portion of the ’924 Patent specification referencing Figures 3A and
`3B that discloses that diffusion regions 70 and 72 of either N+ or P+ doping
`are formed by an ion implantation in the surface of the silicon substrate 74 in
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`which a photoresist layer is used as an ion implantation mask. Id. at 24–26
`(citing Ex. 1101, col. 3, ll. 40–51); Ex. 1101, col. 3, ll. 46–55. Petitioner
`also cites the Declaration of Dr. John C. Bravman, Ex. 1102 (“Bravman
`Decl.”), for the proposition that, at the time of the invention, one of ordinary
`skill in the art would have understood that a diffusion region is a conductive
`terminal region, such as a source or drain, that contains dopants implanted in
`the substrate. Pet. 25 (citing Bravman Decl. ¶ 65).
`The subject matter of the claims concerns a local interconnect
`between a gate and a diffusion region. For purposes of this decision, we
`need not further construe the term “diffusion region in a silicon substrate.”
`
`ANALYSIS OF PETITIONER’S PRIOR ART CHALLENGES
`
`
`Introduction
`A claim is unpatentable under 35 U.S.C. § 102 if a prior art reference
`discloses every limitation of the claimed invention, either explicitly or
`inherently. Glaxo Inc. v. Novopharm Ltd., 52 F.3d 1043, 1047 (Fed. Cir.
`1995); see MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362, 1365
`(Fed. Cir. 1999) (“[t]o anticipate, a single reference must teach every
`limitation of the claimed invention”; any limitation not explicitly taught
`must be inherently taught); In re Baxter Travenol Labs., 952 F.2d 388, 390
`(Fed. Cir. 1991) (the dispositive question is “whether one skilled in the art
`would reasonably understand or infer” that a reference teaches or discloses
`all of the elements of the claimed invention); Continental Can Co. USA v.
`Monsanto Co., 948 F.2d 1264, 1268–69 (Fed. Cir. 1991) (to anticipate,
`every element of the claims must appear in a single prior art reference, or if
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`not expressly shown, then demonstrated to be known to persons experienced
`in the field of technology).
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`Anticipation By Sakamoto
`Petitioner contends that Sakamoto not only is directed to the same
`problem as that addressed by the ’924 Patent, i.e., connecting different
`transistor portions together, but also that Sakamoto discloses the same
`solution as that found in the ’924 Patent, i.e., using a single plug. Pet. 19–
`20.
`
`Sakamoto “relates to improvement of a contact structure of an
`interconnection in a region having steps in a semiconductor device having a
`multilayer interconnection structure.” Ex. 1103, col. 1, ll. 12–16. Petitioner
`provides the following figure comparing an annotated version of Figure 1 of
`Sakamoto on the left with an annotated version of Figure 3B of the ’924
`Patent on the right:
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`Petitioner’s comparison of Sakamoto Fig. 1
` and ’924 Patent Figure 3B
`Pet. 20. Petitioner contends that Sakamoto discloses a plug filling an
`opening having a sidewall spacer that electrically connects a diffusion region
`to a gate, as claimed in the ’924 Patent. Id. at 20–21. Petitioner addresses
`each of the limitations of the claims challenged as anticipated by Sakamoto
`and discusses why specific features of Sakamoto are anticipatory. Id. at 27–
`46.
`
`Turning to claim 7, Petitioner notes that Sakamoto discloses a method
`of forming a local interconnect in a series of steps for manufacturing a static
`random access memory (SRAM) cell and that the Sakamoto’s SRAM cell is
`a semiconductor structure. Pet. 27–28 (citing Ex. 1103, col. 7, ll. 14–15, col.
`6, l. 39–col. 8, l. 52; Bravman Decl. ¶ 70).
`Petitioner next compares the method recited in claim 7 with the
`disclosure in Sakamoto. Claim 7 recites the following elements as
`designated by Petitioner: (a) depositing an electrically conducting material
`in a via exposing at least a portion of a gate, a sidewall spacer adjacent to
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`said gate and a portion of a diffusion region such that said electrically
`conducting material contacts and provides electrical communication between
`said gate and said diffusion region, (b) said semiconductor structure
`comprising said diffusion region in a silicon substrate, (c) said gate being on
`said substrate juxtaposed to but not contacting said diffusion region, (d) said
`sidewall spacer being disposed above said diffusion region, and (e) said via
`being in an insulating material on said gate. Although framed as a method
`claim, claim 7 recites the single step of depositing electrically conducting
`material in a via exposing at least a portion of a gate and a portion of a
`diffusion region, such that the electrically conducting material contacts the
`gate and diffusion region. The remaining elements of the claim recite effects
`(e.g., the contact by the electrically conducting material provides electrical
`communication between the gate and diffusion region) or structural features
`(e.g., the semiconductor structure comprising a diffusion region in the
`silicon substrate, a sidewall spacer, the via being in an insulating material on
`the gate).
`Turning to element (a), Petitioner provides the following annotated
`illustration of Figure 1 of Sakamoto, including an expanded view of the
`region where the electrically conducting plug is located:
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`Petitioner’s annotated illustration of Figure 1 of Sakamoto
`with exploded view of electrically conducting contact
`
`Pet. 29. Petitioner uses this figure to illustrate that Sakamoto shows
`electrically conducting plug 15 in via opening 16 formed in insulating layer
`9 and that plug 15 is connected directly to source/drain region 7 and gate
`electrode 6. Id. at 29–30. Figure 1 of Sakamoto also shows sidewall spacer
`9'. Id. at 30. Petitioner points out that Sakamoto describes the plug layer 15
`is formed when polycrystalline silicon layer 15a is deposited to fill opening
`16 and is etched leaving a portion of the layer only within opening 16. Id. at
`29–30 (citing Bravman Decl. ¶ 72). An N type impurity is introduced into
`the polycrystalline silicon plug layer 15 to provide conductivity. Id. at 31
`(citing Ex. 1103, col. 6, ll. 49–col. 7, l. 14). Via 16 exposes a portion of gate
`electrode 6 and diffusion region (source/drain region 7), so that when plug
`layer 15 is present, contact between the gate and diffusion region provides
`electrical communication. Id. at 30–31.
`Element (b) of claim 7, as identified by Petitioner, recites that the
`semiconductor structure comprises the diffusion region in a silicon substrate.
`Petitioner contends that Sakamoto teaches that the diffusion region
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`constitutes source/drain region 7 and that the diffusion region contains
`dopants implanted in the silicon substrate. Pet. 33–34. Figure 1 of
`Sakamoto appears to delineate a main silicon substrate 1 and a p-well region
`2 above it. Petitioner acknowledges that Figure 1 of Sakamoto illustrates a
`p-well region 2, but contends that the p-well region is part of the silicon
`substrate. Id. at 35–37. Petitioner argues that p-well region 2 is formed
`below the top surface of silicon substrate and a source/drain region 7 is
`formed in the silicon substrate below the top surface of p-well region 2. Id.
`at 32–33. Petitioner contends that p-well region 2 is part of the silicon
`substrate because p-well region 2 is formed in the surface of the substrate.
`Id. at 35 (citing Ex. 1103, col. 7, ll. 17–21, disclosing that a “p type impurity
`is implanted in a main surface of a silicon substrate” and that the “implanted
`p type impurity is diffused to the depth of about 2–3 µm from the main
`surface of substrate 1 by heat treatment to form a p well 2”). Petitioner also
`notes that during prosecution, the applicant for the ’924 Patent did not
`dispute the Examiner’s assertion that a diffusion region is formed within a
`silicon substrate and argued that the cited reference (Kinoshita) disclosed
`buried ground layers in the substrate. Id. at 35–37 (citing Ex. 1113 and Ex.
`1114). Petitioner further contends that in at least one embodiment (the fifth
`embodiment shown in Figure 25), Sakamoto does not delineate the p-well
`region, stating that an n-type impurity region is formed on a surface of the
`silicon substrate. Id. at 37 (citing Ex. 1103, col 12, ll. 57–58). It is unclear
`if there is a distinction to be drawn between Sakamoto’s first four
`embodiments, which all delineate p-well region 2 and Sakamoto’s fifth
`embodiment in which p-well region 2 is not shown. However, for purposes
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`of this Decision, we accept Petitioner’s contention that the implanted p-well
`region is part of the silicon substrate.
`Based on this analysis, we are persuaded by Petitioner’s argument that
`Sakamoto discloses element (a) depositing an electrically conducting
`material in a via exposing at least a portion of a gate, a sidewall spacer
`adjacent to said gate and a portion of a diffusion region such that said
`electrically conducting material contacts and provides electrical
`communication between said gate and said diffusion region. As to element
`(b), we are persuaded by Petitioner’s argument that Sakamoto discloses a
`semiconductor structure comprising a diffusion region in a silicon substrate.
`Element (c) of claim 7, as designated by Petitioner, recites “said gate
`being on said substrate juxtaposed to but not contacting said diffusion
`region.” Figure 1 of Sakamoto illustrates field oxide film 4 and p+ isolation
`layer 3 formed on a prescribed region of a surface of p-well 2 for isolation.
`Ex. 1103, col. 7, ll. 22–23. Oxide film 5 is formed on the surface of the p-
`well 2. Id. at col. 7, ll. 23–24. A polycide film of polysilicon and refractory
`metal silicide is deposited on the surface of oxide film 5 and patterned to
`form gate electrode 6. Id. at col. 7, ll. 24–31.
`Petitioner contends that the placement of the gate electrode in
`Sakamoto over a field oxide layer constitutes forming the gate on said
`substrate because the applicant for the ’924 Patent relied on conception of
`the same physical construct during prosecution in a Declaration under
`37 C.F.R. § 1.131 (“Rule 131 Declaration”). Pet. 38 n.7 (citing Ex. 1106,
`Ex. A).1 The specification of the ’924 Patent does not discuss forming the
`
`
`1 Petitioner appears to be citing to the center figure at the top of page 11 of
`Ex. 1106.
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`gate electrode on the substrate in detail, stating only that a photoresist layer
`used to pattern and etch openings for the diffusion regions is removed and
`that polysilicon then deposited on substrate 74 is etched to form gate
`electrode 74. Ex. 1101, col. 3, ll. 49–58. In this context, the statements in
`applicant’s Rule 131 Declaration provide context to the meaning of “said
`gate being on said substrate.” In order to antedate a reference, Patent Owner
`demonstrated an invention in which the gate electrode is formed over a field
`oxide layer. Therefore, for purposes of this Decision, we agree with
`Petitioner that taken in the proper context, notwithstanding the presence of
`the field oxide layer 4 and field oxide film 5, Sakamoto discloses the gate
`electrode formed on the substrate.
`Petitioner also argues that the gate in Sakamoto is juxtaposed from but
`is not in direct contact with the diffusion region, as recited in claim 7. Pet.
`39–41. Petitioner contends that oxide film 5 separates the gate from the
`diffusion region, noting that there would be no need for the claimed plug to
`connect the gate and the diffusion region if this were not the case. Id. at 40.
`Sakamoto states:
`The sectional structure of the memory cell shown in FIG. 1 [of
`Sakamoto] is the same as the sectional structure of a
`conventional memory cell shown in FIG. 28 except for a
`structure of direct contact. . . .
`
`Direct contact portion 10 includes an n type
`polycrystalline silicon plug layer 15 . . . directly connected to
`the n+ source/drain region 7 and gate electrode 6 . . . embedded
`within opening 16.
`
`Ex. 1103, col. 6, ll. 42–58. Figures 1 and 28 in Sakamoto illustrate that
`because of the presence of oxide film 5, in the absence of plug 15, there is
`no direct contact between gate 6 and source/drain region 7.
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`Petitioner designates as element (d) of claim 7 the recitation “said
`sidewall spacer being disposed above said diffusion region.” Pet. 41.
`Petitioner designates as element (e) of claim 7 the recitation of “said via
`being in an insulating material on said gate.” Id. at 43. Petitioner cites
`insulating layer 9 shown in Figure 1 of Sakamoto as disclosing element (e)
`of claim 1 of the ’924 Patent. Id. Petitioner cites sidewall spacer 9' in
`Figure 1 of Sakamoto as disclosing the claimed sidewall spacer. Id. at 41–
`42. Sakamoto discloses interlevel insulating layer 9 disposed above the gate
`and diffusion region and that an opening 16 for direct contact formed using a
`photolithography method leaves sidewall spacer 9'. Ex. 1103, col. 7, ll. 47–
`51.
`
`Based on this analysis in the Petition, Petitioner has demonstrated that
`Sakamoto discloses all of the elements of claim 7.
`Claim 8 depends from claim 7 and recites that the diffusion region is
`an N+ or P+ region. Petitioner notes that Sakamoto discloses the diffusion
`region as an N+ region because it expressly refers to an n+ source drain
`region 7. Pet. 44.
`Claim 9 depends from claim 7 and recites that the insulating material
`is selected from the group consisting of silicon oxide and silicon nitride.
`Petitioner cites Sakamoto’s disclosure of softening and reflowing
`BoroPhosphoSilicate Glass (BPSG) film to form insulating layer 9, stating
`that BPSG is a type of silicon oxide. Id. at 44–45 (citing Bravman Decl. ¶
`91; Ex. 1115, at 185).2
`
`
`2 Although Petitioner does not cite Ex. 1115 as a basis for its challenge that
`claim 9 is anticipated by Sakamoto, we understand Petitioner’s citation to
`demonstrate that one of ordinary skill would infer the limitation is disclosed
`by Sakamoto. In re Baxter Travenol Labs., 952 F.2d at 390.
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`Claim 15 depends from claim 7 and recites “said gate is a polysilicon
`gate.” Claim 17 depends from claim 7 and recites “said gate comprises
`polysilicon.” Petitioner notes that Sakamoto discloses the gate electrode 6 is
`formed of polycrystalline silicon, which is another name for polysilicon. Id.
`at 46.
`
`In consideration of the above, Petitioner has demonstrated a
`reasonable likelihood that it will prevail in its challenge to claims 7–9, 15
`and 17 as anticipated by Sakamoto and we institute a trial on this ground.
`
`Obviousness Over Sakamoto and Cederbaum
`Petitioner contends that claims 10–12 are obvious over the
`combination of Sakamoto and Cederbaum. Comparing Figure 7 of
`Cederbaum to Figure 3B of the ’924 Patent, Petitioner contends that
`Cederbaum discloses a structure that includes components arranged in a way
`that is identical to those of Fig. 3B of the ’924 Patent. Pet. 23. The figure
`below is Petitioner’s comparison of Fig 7 of Cederbaum on the left and
`Figure 3B of the ’924 Patent on the right.
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`Petitioner’s Comparison of Fig. 7 of Cederbaum
`to Fig 3B of the ’924 Patent
`Id. at 22. Petitioner emphasizes that, like the ’924 Patent, Cederbaum
`concerns the use of a contact stud or conducting plug to fill an opening with
`a sidewall spacer to directly connect a source/drain region to a gate
`electrode. Id.
`According to Petitioner, one of ordinary skill would have been
`motivated to combine the teachings of Cederbaum with those of Sakamoto
`because they both teach the same type of device and are directed to the same
`problem, i.e., stacking transistors in a SRAM. Pet. 49. Petitioner points out
`that Cederbaum and Sakamoto also disclose nearly identical structures with
`nearly identical components, with both employing an electrically conducting
`plug within an opening that contains a sidewall spacer to directly connect a
`diffusion region to a gate. Id. at 50–51. Petitioner cites Cederbaum’s
`disclosure of materials, such as refractory metals, to be used in forming the
`conductive plug and Sakamoto’s discussion of the advantages to using a
`conductive plug of increased conductivity. Id. at 51–52. Thus, Petitioner
`contends it would have been obvious to one of ordinary skill to replace the
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`polycrystalline plug 15 of Sakamoto with a refractory metal plug of
`tungsten, as disclosed by Cederbaum. Id. at 48–49. Claim 10 recites “said
`electrically conducting plug is a metal plug.” Claim 11 recites “said
`electrically plug is preferably a refractory metal plug.” Claim 12 recites
`“said electrically conducting plug is formed of a material selected from the
`group consisting of titanium, tantalum, molybdenum and tungsten.”
`Petitioner cites Cederbaum’s disclosure at column 9, lines 31–65 as
`disclosing a tungsten conducting plug. Id. at 47–48.
`In consideration of the above, we are persuaded that Petitioner has
`demonstrated a reasonable likelihood it will succeed in its challenge to
`claims 10–12 as obvious over the combination of Sakamoto and Cederbaum
`and we institute a trial on this ground.
`
`SUMMARY
`For the reasons discussed above, on the current record we are
`persuaded that Petitioner has demonstrated a reasonable likelihood that it
`will succeed on the following challenges to patentability:
`Claims 7–9, 15, and 17 as anticipated under 35 U.S.C. § 102(e) by
`Sakamoto; and
`Claims 10–12 as obvious under 35 U.S.C. § 103(a) over the
`combination of Sakamoto and Cederbaum.
`
`
`ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that pursuant to 35 U.S.C. § 314(a) an inter partes review
`of the ’924 Patent is hereby instituted, commencing on the entry date of this
`
`
`
`17
`
`
`
`IPR2016-00290
`Patent 5,965,924
`
`
`Order, and pursuant to 35 U.S.C. § 314(c) and 37 C.F.R. § 42.4, notice is
`hereby given of the institution of a trial.
`FURTHER ORDERED that the trial is limited to the following
`grounds and no other grounds are authorized:
`Claims 7–9, 15, and 17 as anticipated under 35 U.S.C. § 102(e) by
`Sakamoto; and
`Claims 10–12 as obvious under 35 U.S.C. § 103(a) over the
`combination of Sakamoto and Cederbaum.
`FURTHER ORDERED that the trial will be conducted in accordance
`with the accompanying Scheduling Order. In the event that an initial
`conference call has been requested or scheduled, the parties are directed to
`the Office Trial Practice Guide, 77 Fed. Reg. 48,756, 48,765–66 (Aug. 14,
`2012), for guidance in preparing for the initial conference call, and should
`come prepared to discuss any proposed changes to the scheduling order
`entered herewith and any motions the parties anticipate filing during the
`trial.
`
`
`
`PETITIONER:
`
`Grant K. Rowan
`Yung-Hoon Ha
`Wilmer Cutler Pickering Hale and Door LLP
`grant.rowan@wilmerhale.com
`yung-hoon.ha@wilmerhale.com
`
`
`
`
`
`18
`
`
`
`
`
`IPR2016-00290
`Patent 5,965,924
`
`
`
`PATENT OWNER
`
`Andriy Lytvyn
`Anton J. Hopen
`Nicholas Pfeifer
`Smith & Hopen, P.A.
`andriy.lytvyn@smithhopen.com
`anton.hopen@smithhopen.com
`nicholas.pfeifer@smithhopen.com
`
`
`
`
`
`19
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