`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`INTEL CORPORATION
`Petitioner
`
`v.
`
`DSS Technology Management, Inc.
`Patent Owner
`
`U.S. Patent No. 5,965,924
`Claims 1-6, 13, 14 and 16
`____________________________________________
`
`Case IPR2016-00289
`____________________________________________
`
`DECLARATION OF JOHN C. BRAVMAN, PH.D.
`ON BEHALF OF PETITIONER
`
`
`
`INTEL 1002
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`I.
`
`B.
`
`TABLE OF CONTENTS
`
`Relevant Law ................................................................................................... 7
`A.
`Claim Construction ............................................................................... 7
`B.
`Anticipation ........................................................................................... 8
`C.
`Obviousness ........................................................................................... 8
`Summary of Opinions .................................................................................... 11
`II.
`Introduction To the ’924 Patent ..................................................................... 11
`III.
`IV. Brief Description of the Technology ............................................................. 14
`A. Overview of Transistor Fabrication .................................................... 14
`1. Basic Structure of Transistors ............................................................. 14
`2. Formation of Transistor Components ................................................. 16
`3. Local Interconnects ............................................................................. 17
`Overview of the ’924 Patent ................................................................ 18
`1. Problem Disclosed in the ’924 Patent ................................................. 19
`2. Summary of Invention of the ’924 Patent ........................................... 21
`3. Prosecution History ............................................................................. 22
`V. Overview of the Primary Prior Art References ............................................. 25
`A. Overview of Sakamoto (Ex. 1003) ...................................................... 25
`B.
`Overview of Cederbaum (Ex. 1004) ................................................... 27
`VI. Claim Construction ........................................................................................ 29
`VII. Level of Ordinary Skill In The Art ................................................................ 32
`VIII. Specific Grounds for Petition ........................................................................ 33
`A. Ground I: Claims 1-3, 14 and 16 are anticipated by Sakamoto ......... 33
`1. Independent Claim 1 ........................................................................... 33
`2. Claim 2: “A semiconductor structure according to claim 1, wherein
`said diffusion region is an N+ or a P+ region” ......................................... 50
`3. Claim 3: “A semiconductor structure according to claim 1, wherein
`said insulator layer is formed of a material selected from the group
`consisting of silicon oxide and silicon nitride.” ....................................... 51
`
`
`
`1
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`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`B.
`
`4. Claim 14: “A semiconductor structure according to claim 1, wherein
`said polysilicon gate and said diffusion region being exposed in said via
`in the absence of said conducting plug.” .................................................. 52
`5. Claim 16: “The structure according to claim 1, wherein said gate
`comprises polysilicon.” ............................................................................ 53
`Ground II: Claims 4-6 and 13 are obvious in view of the combination
`of Sakamoto and Cederbaum .............................................................. 53
`1. Claim 4: “a semiconductor structure according to claim 1, wherein
`said electrically conducting plug is a metal plug” / Claim 5: “a
`semiconductor structure according to claim 1, wherein said electrically
`conducting plug is a refractory metal plug.” / Claim 6: “a semiconductor
`structure according to claim 1, wherein said electrically conducting plug
`is formed of a material selected from the group consisting of titanium,
`tantalum, molybdenum and tungsten” ...................................................... 54
`2. Claim 13: A semiconductor structure according to claim 1, wherein
`said conducting plug comprises an outer glue layer and a plug material
`therein ....................................................................................................... 60
`IX. Availability for Cross-Examination .............................................................. 62
`X.
`Right to Supplement ...................................................................................... 62
`
`
`
`2
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`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`I, John C. Bravman, declare as follows:
`
`1. My name is John C. Bravman.
`
`2. My academic training was at Stanford University, where I received
`
`my Bachelor of Science degree in Materials Science and Engineering in 1979, and
`
`a Master of Science degree in 1981, also in Materials Science and Engineering. I
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`completed my Doctor of Philosophy degree in 1984, with a dissertation that
`
`focused on the nature of silicon – silicon dioxide interfaces as found in integrated
`
`circuit devices.
`
`3.
`
`From 1979 to 1984, while a graduate student at Stanford, I was
`
`employed part-time by Fairchild Semiconductor in their Palo Alto Advanced
`
`Research Laboratory. I worked in the Materials Characterization group. In 1985,
`
`upon completion of my doctorate, I joined the faculty at Stanford as Assistant
`
`Professor of Materials Science and Engineering. I was promoted to Associate
`
`Professor with tenure in 1991, and achieved the rank of Professor in 1995. In 1997
`
`I was named to the Bing Professorship.
`
`4.
`
`At Stanford I was Chairman of the Department of Materials Science
`
`and Engineering from 1996 to 1999, and Director of the Center for Materials
`
`Research from 1998 to 1999. I served as Senior Associate Dean of the School of
`
`Engineering from 1992 to 2001 and the Vice Provost for Undergraduate Education
`
`
`
`3
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`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`from 1999 to 2010. On July 1, 2010, I retired from Stanford University and
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`assumed the Presidency of Bucknell University, where I also became a Professor
`
`of Electrical Engineering.
`
`5.
`
`I have worked for more than 25 years in the areas of thin film
`
`materials processing and analysis. Much of my work has involved materials for
`
`use in microelectronic interconnects and packaging, and in superconducting
`
`structures and systems. With regard to integrated circuits, I led investigations
`
`involving aluminum, copper and tungsten metallizations, polycrystalline silicon,
`
`metal silicides, a variety of oxide and nitride dielectrics, and barrier layers such as
`
`titanium and tantalum-based nitrides. Further, my groups blended fundamental
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`aspects of the behavior of microelectromechanical systems—specifically,
`
`compliant multilayer cantilever beams—for possible test probe and package
`
`implementations. In this work my group investigated the mechanical behavior of
`
`package underfill systems, focusing on the relationship between microstructures,
`
`processing, and adhesion. I have also led multiple development efforts of
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`specialized equipment and methods for determining the microstructural and
`
`mechanical properties of materials and structures. My groups designed and built
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`the first high voltage SEM for in-situ studies of electromigration, the first high
`
`temperature wafer curvature system, and the first microtensile tester for micron-
`
`
`
`4
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`scale structures, amongst many others. As a graduate student I developed one of
`
`the earliest methodologies for obtaining high resolution cross section transmission
`
`electron micrographs of integrated circuit structures.
`
`6.
`
`I have taught a wide variety of courses at the undergraduate and
`
`graduate level in materials science and engineering, emphasizing both basic
`
`science and applied technology, including coursework in the areas of integrated
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`circuit materials and processing. Some of these courses focused on processes (e.g.,
`
`cleaning, etching, deposition, doping, oxidation, etc.) used in the production of
`
`integrated circuits. More than two thousand students have taken my classes, and I
`
`have trained 24 doctoral students, most of whom now work in the microelectronics
`
`industry.
`
`7.
`
`I am a member of many professional societies, including the Materials
`
`Research Society, the Institute of Electrical and Electronic Engineers, the
`
`American Society of Metals, and the American Physical Society. I served as
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`President of the Materials Research Society in 1994.
`
`8.
`
`A copy of my curriculum vitae (including a list of all publications
`
`authored in the previous 10 years) is attached as Appendix A.
`
`9.
`
`I have reviewed the specification, claims and file history of U.S.
`
`Patent No. 5,965,924. I understand that the ’924 patent was filed on July 24, 1997,
`
`
`
`5
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`issued from a “continued prosecution application” (“CPA”) of U.S. App. No.
`
`08/561,951 and claims priority to an application filed on November 22, 1995. I
`
`understand that, for purposes of determining whether a publication will qualify as
`
`prior art, the earliest date that the ’924 patent could be entitled to is November 22,
`
`1995. However, I further understand that the prior assignee claimed a conception
`
`date of May 17, 1995 during prosecution of the ’924 application. Amendment and
`
`Rule 131 Declaration dated Jan. 5, 1998 (Ex. 1006). Even under that conception
`
`date, the cited references are prior art and invalidate the ’924 patent.
`
`10.
`
`I have reviewed the following patents in preparing this declaration:
`
` U.S. Patent No. 5,475,240 (“Sakamoto”) (Ex. 1003).
`
` U.S. Patent No. 5,100,817 (“Cederbaum”) (Ex. 1004).
`
`11.
`
`I have reviewed the above patents and any other publication cited in
`
`this declaration.
`
`12.
`
`I have considered certain issues from the perspective of a person of
`
`ordinary skill in the art as described below at the time the ’924 patent application
`
`was filed. In my opinion, a person of ordinary skill in the art for the ’924 patent
`
`would have found the ’924 patent invalid.
`
`13.
`
`I have been retained by the Petitioner as an expert in the field of
`
`semiconductor device fabrication and design. I am working as an independent
`
`
`
`6
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`consultant in this matter and am being compensated at my normal consulting rate
`
`of $450 per hour for my time. My compensation is not dependent on and in no
`
`way affects the substance of my statements in this Declaration.
`
`14.
`
`I have no financial interest in the Petitioner. I similarly have no
`
`financial interest in the ’924 patent, and have had no contact with the named
`
`inventor of the ’924 patent.
`
`I. RELEVANT LAW
`15.
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as follows:
`
`A. Claim Construction
`16.
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`the purposes of my analysis in this proceeding and with respect to the prior art, I
`
`have been informed that I should apply what is known as “the Phillips standard,”
`
`rather than the broadest reasonable interpretation standard.
`
`17. Specifically, I have been informed and understand that since the ’924
`
`patent expired on November 22, 2015, the Phillips standard applies for the
`
`purposes of claim construction. I further understand that the Phillips standard
`
`means that claim terms are given their plain and ordinary meaning as understood
`
`
`
`7
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`by a person of ordinary skill in the art at the time of the invention in light of the
`
`claim language and the patent specification.
`
`18.
`
`I have also been informed and understand that any claim term that
`
`lacks a definition in the specification is therefore given its plain and ordinary
`
`meaning as understood by one of ordinary skill in the art.
`
`B. Anticipation
`19.
`I have been informed and understand that a patent claim may be
`
`“anticipated” if each element of that claim is present either explicitly, implicitly, or
`
`inherently in a single prior art reference. I have also been informed that, to be an
`
`inherent disclosure, the prior art reference must necessarily disclose the limitation,
`
`and the fact that the reference might possibly practice or contain a claimed
`
`limitation is insufficient to establish that the reference inherently teaches the
`
`limitation.
`
`C. Obviousness
`20.
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed. This means that, even if all of the requirements of a
`
`claim are not found in a single prior art reference, the claim is not patentable if the
`
`differences between the subject matter in the prior art and the subject matter in the
`
`
`
`8
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`claim would have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed.
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`21.
`
`I have been informed and understand that a determination of whether
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`a claim would have been obvious should be based upon several factors, including,
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`among others:
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` the level of ordinary skill in the art at the time the application was filed;
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` the scope and content of the prior art; and
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` what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`22.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
`
`other factors:
`
` whether the teachings of the prior art references disclose known concepts
`
`combined in familiar ways, which, when combined, would yield
`
`predictable results;
`
`
`
`9
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
` whether a person of ordinary skill in the art could implement a
`
`predictable variation, and would see the benefit of doing so;
`
` whether the claimed elements represent one of a limited number of
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`known design choices, and would have a reasonable expectation of
`
`success by those skilled in the art;
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` whether a person of ordinary skill would have recognized a reason to
`
`combine known elements in the manner described in the claim;
`
` whether there is some teaching or suggestion in the prior art to make the
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`modification or combination of elements claimed in the patent; and
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` whether the innovation applies a known technique that had been used to
`
`improve a similar device or method in a similar way.
`
`23.
`
`I understand that one of ordinary skill in the art has ordinary
`
`creativity, and is not an automaton.
`
`24.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`
`
`10
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`II. SUMMARY OF OPINIONS
`25.
`It is my opinion that every limitation of the structures described in
`
`claims 1 through 6, 13, 14 and 16 of the ’924 patent are disclosed by the prior art,
`
`and are anticipated and/or rendered obvious by the prior art.
`
`III.
`
`INTRODUCTION TO THE ’924 PATENT
`26. The ’924 patent is directed to certain aspects of the structure and
`
`fabrication of transistors used in semiconductor and integrated circuit products
`
`such as microprocessors and memory. Transistors act as microscopic switches that
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`turn on and off at extraordinarily high rates to enable aggregations of transistors
`
`(and other components) to process data. Transistors are made up of various
`
`structures including “contacts” that provide electrically conductive pathways into
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`and out of certain structures within a transistor, and which thereby are used to
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`connect transistors together.
`
`27. The ’924 patent is concerned with electrically connecting different
`
`transistor parts to each other in a particular way. Transistors typically have three
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`terminals through which electrical signals may pass: a “source,” a “drain,” and a
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`“gate.” The ’924 patent is concerned with connecting the gate of one transistor to,
`
`for example, the source or drain of a neighboring transistor.
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`28. According to the specification of the ’924 patent, there were many
`
`well-known ways of making electrical connections between different transistor
`
`
`
`11
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`parts. As shown in Figure 2B (below), for instance, one of the prior art ways of
`
`connecting the components of two transistors was by using two electrical
`
`connections called “plugs”—one connected to the gate of one transistor, and the
`
`other connected to the source or drain of the other—and then connecting those
`
`plugs together. As shown in Figure 3B (below), the purported invention of
`
`the ’924 patent was to replace the two plugs with one plug. 1
`
`Admitted Prior Art: Fig. 2B
`
`Allegedly Novel Structure: Fig. 3B
`
`29.
`
`In both the prior art (Figure 2B) and the allegedly novel structure of
`
`
`
`the ’924 patent (Figure 3B), the gate is connected to a diffusion region (i.e., a
`
`source or drain) by either two connected plugs, or a single plug. The patent does
`
`not claim that the one-plug structure provides any performance benefits over the
`
`two-plug structure. Instead, the benefit was that the one-plug structure was easier
`
`
`1 All emphasis and annotations are added unless otherwise indicated.
`
`
`
`12
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`to manufacture than the admitted prior art. ’924 patent at 1:57-2:63, 4:18-5:12
`
`(Ex. 1001).
`
`30. Long before the ’924 patent’s November 22, 1995 priority date, many
`
`others had already developed and used the exact same one-plug structure. U.S.
`
`Patent No. 5,475,240 (“Sakamoto”), for instance, which has an effective filing date
`
`of March 4, 1992, discloses the same one-plug structure that the ’924 patent
`
`contends is novel. Specifically, as shown in the patents’ respective figures, the
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`one-plug structure of Sakamoto (Figure 1) is in all relevant aspects identical to the
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`one-plug structure of the ’924 patent (Figure 3B).
`
`Sakamoto: Fig. 1
`
`’924 Patent: Fig. 3B
`
`31. As shown, both structures include a gate connected to a source or
`
`
`
`drain through a single plug.
`
`
`
`13
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`32. U.S. Patent No. 5,100,817 (“Cederbaum”) issued on March 31, 1992,
`
`and, just like the ’924 one-plug structure, discloses a single conducting plug
`
`connecting a gate to a source or drain.
`
`Cederbaum: Fig. 7
`
`33. Sakamoto and Cederbaum were not at issue during prosecution of
`
`
`
`the ’924 patent. These references anticipate and/or render obvious claims 1-6, 13,
`
`14 and 16 the ’924 patent.
`
`IV. BRIEF DESCRIPTION OF THE TECHNOLOGY
`34. The ’924 patent generally relates to the field of semiconductor
`
`integrated circuit manufacturing and claims particular structures for transistors in
`
`semiconductors, as well as a related method for manufacturing those structures.
`
`A. Overview of Transistor Fabrication
`1. Basic Structure of Transistors
`
`35. Semiconductor integrated circuits, such as microprocessors and
`
`computer memory, are typically made up of hundreds of millions (and in some
`
`
`
`14
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`cases billions) of microscopic structures called transistors. Transistors act as
`
`microscopic switches that turn on and off at extraordinarily high rates to enable
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`aggregations of transistors (and other components) to process data.
`
`36. As shown in the figure below, transistors typically include three
`
`primary “electrodes” or “terminals”—a “gate,” a “source,” and a “drain”:
`
`
`37. The source and drain regions (also referred to as “diffusion regions”)
`
`are transistor components that emit (source) and receive (drain) current when the
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`transistor is “on.” The gate typically sits between the source and drain and is a
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`terminal that can have a voltage applied to it that in turn causes a current to flow
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`between the source and drain. As of the time of the invention of the ’924 patent,
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`the source and drain of a transistor were typically formed in the surface of a
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`semiconductor “substrate,” while the gate typically sat above the substrate and
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`separated from it by a thin layer of insulator (“gate oxide”).
`
`
`
`15
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`2. Formation of Transistor Components
`
`38. Transistor fabrication typically starts with a silicon substrate. In
`
`typical planar transistors, the source and drain regions (“diffusion regions”) are
`
`created by implanting regions of the substrate with ions (charged atomic particles)
`
`of different materials—called “dopants” or “impurities”— to make those regions
`
`conductive. (Once implanted the ions become neutral atoms). This process—
`
`referred to as “doping” because it dopes the silicon substrate with atomic particles
`
`that have additional charge carriers—is shown below:
`
`
`39. Structures can then be formed above the substrate by depositing layers
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`of other materials onto the substrate. A gate electrode, for example, is formed by
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`first growing or depositing a “gate oxide” (an insulator) on the substrate followed
`
`by depositing a conductive material (metal or polysilicon) on top of the gate oxide.
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`The conductive material acts as the gate, and the gate oxide creates a layer of
`
`isolation between the gate and the source/drain regions (“S/D regions” or
`
`“diffusion regions”).
`
`
`
`16
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`40.
`
`Insulating materials may then be deposited around and over the gate
`
`and the S/D regions to maintain electrical isolation where desired. Sidewall
`
`spacers, for instance, can be formed on each side of the gate electrode as shown
`
`below:
`
`
`As was known as of the time of the ’924 invention, such sidewall spacers help to
`
`prevent direct electrical contact between the gate electrode and nearby components
`
`and thus help to prevent short-circuits.
`
`3. Local Interconnects
`
`41. Many transistors can be connected together to form electronic circuits.
`
`For certain types of circuits, it is sometimes useful to connect the gate of one
`
`transistor to a diffusion region (the source or drain) of a nearby transistor. This
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`type of connection is called a “local interconnect,” because connections are made
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`locally between nearby transistors.
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`42. According to the specification of the ’924 patent, a variety of different
`
`types of local interconnects were well-known prior to the purported invention. For
`
`
`
`17
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`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`example, as shown in Figure 1B of the ’924 patent, one well-known way to form a
`
`local interconnect was to position the gate in a location where it physically touches
`
`the diffusion region on one side, creating an electrical connection. As shown in
`
`Figure 2B of the ’924 patent, another well-known way to make a local interconnect
`
`was to place one electrically conductive “plug” above the gate and another “plug”
`
`above the diffusion (e.g., source or drain) region, and then electrically connect the
`
`two plugs together.
`
`Admitted Prior Art: Fig. 1B
`
`Admitted Prior Art: Fig. 2B
`
`
`
`43. The ’924 patent acknowledges that both examples were known prior
`
`art. See ’924 patent at Figs. 1A, 1B, 2A, 2B, 1:25-2:45, 3:30-35 (Ex. 1001).
`
`B. Overview of the ’924 Patent
`44. The ’924 patent issued from U.S. App. No. 08/900,047, which was
`
`filed on July 24, 1997, and claims priority to an application filed on November 22,
`
`1995. ’924 patent at cover page (Ex. 1001). The invention of the ’924 patent is a
`
`
`
`18
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`single plug to connect different transistor parts. ’924 patent at 2:32-67, 4:18-5:12
`
`(Ex. 1001).
`
`1. Problem Disclosed in the ’924 Patent
`
`45. The ’924 patent addresses manufacturing inefficiencies in forming
`
`local interconnects. Figures 1 and 2 of the ’924 patent are prior art and show
`
`examples of two well-known types of local interconnects that (according to
`
`the ’924 patent) are inefficient to manufacture.
`
`46. Figure 1B shows a “buried contact” local interconnect structure in
`
`which the gate directly touches—i.e., is in direct electrical connection with—a
`
`diffusion region. According to the ’924 patent, the problem with this structure is
`
`that the gate has to be implanted with the same type of impurities as those
`
`implanted in the diffusion region. See ’924 patent at 1:57-2:11 (Ex. 1001). But
`
`most manufacturers use a variety of different types of impurities in different
`
`transistors. To use the “buried contact” approach, a manufacturer would have to
`
`ensure that any two transistors connected using this approach use the same
`
`impurities, which complicates the manufacturing process. See id.
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`
`
`19
`
`
`
`Admitted Prior Art: Fig. 1B
`
`Admitted Prior Art: Fig. 2B
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`
`
`47. Figure 2B shows another prior art local interconnect structure, using
`
`what is called a “strapping” technique. To form this “strapping” local interconnect
`
`structure, a manufacturer creates two electrically conductive plugs (numbers 44
`
`and 46)—one above the gate and one above a diffusion region. The manufacturer
`
`then places an electrically conductive “local strap” (number 50) on top of the
`
`plugs, electrically connecting the two plugs together. This local strap is also
`
`sometimes called a “shunt” or a “shunt layer.” In combination, the two plugs and
`
`the local strap electrically connect the gate to a diffusion region. See ’924 patent at
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`2:12-32 (Ex. 1001). According to the ’924 patent, the problem with the strapping
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`technique is that it requires a large number of manufacturing process steps, as well
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`as significant space to accommodate the two plugs and the local strap. See ’924
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`patent at 2:33-41 (Ex. 1001).
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`
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`20
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`
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`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`2. Summary of Invention of the ’924 Patent
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`48. The ’924 patent’s claimed structure includes nearly identical
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`components as the prior art described in the specification. Specifically, both the
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`claimed structure and the prior art include a substrate, a gate, a diffusion region, a
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`sidewall spacer adjacent to the gate, and an insulating layer.
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`Admitted Prior Art: Fig. 2B
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`Preferred Embodiment: Fig. 3B
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`
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`49. As shown in Figures 2B and 3B, in both the prior art of the ’924
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`patent and the structure of the disclosed embodiment, the gate is connected to the
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`diffusion region (source or drain), by either two connected plugs, or a single plug.
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`The diffusion region is located in a substrate and is not directly connected to the
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`gate. The gate is substantially covered by an insulating layer.
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`50. The only feature that the patent describes as novel, which is shown in
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`Figure 3B, is the use of a single metal plug to connect the gate and the diffusion
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`region, rather than connecting the two components directly (as in the prior art
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`
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`21
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`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
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`“buried contact” technique (Figure 1B)) or using two plugs (as in the prior art
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`“strapping” technique (Figure 2B)). ’924 patent at 2:64-67, 3:35-36 (describing
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`Figure 3B as “a cross-sectional view of a preferred embodiment of the present
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`invention.”), 4:18-5:12, claims 1, 7 (Ex. 1001); see also id. at 2:42-63.
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`3. Prosecution History
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`51. The ’924 patent issued from a “continued prosecution application”
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`(“CPA”) of U.S. App. No. 08/561,951. CPA Request dated Feb. 10, 1999 (Ex.
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`1005). During prosecution of the ’924 patent, the Applicant tried to antedate a
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`prior art reference, based on a lab notebook dated May 17, 1995. Amendment and
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`Rule 131 Declaration dated Jan. 5, 1998 (Ex. 1006). For purposes of this Petition,
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`I understand that the references relied upon by Petitioner all qualify as prior art
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`even if the Patent Owner could ultimately prove a conception date as early as May
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`17, 1995.
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`52. According to this lab notebook, the novelty of the ’924 invention
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`arises from the use of a single plug—which is what allegedly leads to fewer
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`processing steps as compared to known prior art techniques. See Rule 131
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`Declaration dated January 5, 1998, Exhibit A (“By placing a metallic plugged
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`contact where poly is required to shunt to diffusion, contacts to [different types of]
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`diffusion can be achieved …. [T]his will require no more layout area than the
`
`
`
`22
`
`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`traditional buried contact. This method has potential [manufacturing] process step
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`savings of 8-11 steps over Trad. BC [traditional buried contact local interconnect
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`(as shown in Figure 1B of the ’924 patent)] and 6-8 steps over strapping [local
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`interconnect (as shown in Figure 2B of the ’924 patent)].”) (Ex. 1006).
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`53. However, during prosecution, rather than relying on this “single plug”
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`structure, the Applicant relied on other alleged differences to overcome the prior
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`art applied by the Examiner. The present petition relies on prior art that was not
`
`before the Examiner. This prior art teaches not only the “single plug” aspect of the
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`claims, but also all of the additional minor differences that the Applicant used to
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`try to distinguish the Examiner’s prior art.
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`a. The “sidewall spacer” limitations
`54. The Examiner rejected the original claims under 35 U.S.C. § 102(e)
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`based on U.S. Patent No. 5,451,434 to Nicholls (“Nicholls”). Office Action dated
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`Nov. 7, 1996 at p. 3 (Ex. 1007). Nicholls taught a single metal plug that connects a
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`diffusion region and a gate. In order to overcome the rejection, the Applicant
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`added a limitation to the claims requiring a sidewall spacer adjacent to the gate.
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`Amendment dated June 9, 1997 at pp. 2-3 (Ex. 1009). Nicholls expressly teaches
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`the placement of a sidewall during manufacture, but also teaches that the sidewall
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`can be completely or “partially removed” in a later manufacturing step. Nicholls at
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`
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`23
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`
`
`U.S. Patent No. 5,954,924
`Claims 1-6, 13, 14 and 16
`
`
`4:25-32 (Ex. 1008). The Applicant overcame the rejection by arguing that the
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`removal of the sidewall during manufacturing taught away from retaining a
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`sidewall spacer adjacent to the gate. Amendment dated June 9, 1997 at pp. 3-4
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`(Ex. 1009). The prior art relied upon in this petition teaches the “sidewall spacer”
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`limitation.
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`b. Direct electrical connection
`55. The Examiner also rejected the claims under 35 U.S.C. § 102(e) based
`
`on U.S. Patent No. 5,541,427 to Chappell (“Chappell”). Office Action dated
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`February 24, 1998 (Ex. 1010). Chappell taught a single metal plug that connects to
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`both a diffusion region and a gate region. Chappell at 4:38-48 (Ex. 1011). The
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`Applicant overcame the rejection by arguing that the metal plug of Chappell
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`purportedly contacts a portion of the gate region that is not conductive, rather than
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`the conductive portion of the gate itself. See Amendment dated April 23, 1998 at
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`p. 4 (“‘when the opening 42 is filled with an electrically conductive material, there
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`is no contact to the electrically conductive portion of the gate stack’”) (emphasis
`
`in original) (quoting Chappell at 4:38-48) (Ex. 1012). The prior art references
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`relied upon in this petition teach a direct electrical connection between the
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`diffusion region and the elect