DSS Technology Mgmt., Inc. v. Intel Corp. et al., Case No. 6:15-cv-00130-RWS
`(E.D. Tex.)
`
`Claim Construction Dates
`
`
`
`
`
`
`
`EVENT
`
`Dec. 7, 2015
`
`Opening Claim Construction Brief
`
`Dec. 23, 2015
`
`Responsive Claim Construction Brief
`
`Jan. 4, 2016
`
`Reply Claim Construction Brief
`
`Jan. 11, 2016
`
`Joint Claim Construction Chart
`
`Jan. 25, 2016
`
`Claim Construction Hearing
`
`1
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`INTEL 1121
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`

`
`
`
`Local Patent Rule 4-3
`Joint Claim Construction Statement
`
`2
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`

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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 1 of 9 PageID #: 1896
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`TYLER DIVISION
`
`
`
`DSS Technology Management, Inc.,
`
`
`v.
`
`
`Intel Corporation, et al.,
`
`
`
`
`
`
`
`
`
`
` Civil Action No. 6:15-cv-130-RWS
`
`
`
`Plaintiff,
`
`Defendants.
`
`JOINT CLAIM CONSTRUCTION AND PREHEARING STATEMENT
`
`Pursuant to Rule 4-3 of the Local Patent Rules (“P.R.”) of the Eastern District of Texas
`
`and the Docket Control Order (Dkt. 161), Plaintiff DSS Technology Management, Inc. and
`
`Defendants Intel Corporation, Dell, Inc., GameStop Corp., Conn’s, Inc., Conn Appliances, Inc.,
`
`Wal-Mart Stores, Inc., Wal-Mart Stores Texas, LLC, and AT&T Mobility LLC (collectively
`
`referred to as “Defendants”) file this Joint Claim Construction and Prehearing Statement.
`
`I.
`
`AGREED CLAIM CONSTRUCTIONS [P.R. 4-3(a)]
`
`Pursuant to P.R. 4-3(a), the parties have agreed on proposed constructions of the
`
`following claim terms, phrases, or clauses, of the patents-in-suit, U.S. Patent No. 5,965,924 (“the
`
`’924 patent”) and U.S. Patent No. 6,784,552 (“the ’552 patent”):
`
`THE ’552 PATENT
`
`TERM
`
`AGREED CONSTRUCTION
`
`“contact region”
`
`contact openings and/or vias
`
`
`
`This construction is also reflected in the table attached as Exhibits A (U.S. Patent No.
`
`6,784,552). If the parties are able to reach further agreement concerning the constructions of any
`
`3
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`

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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 2 of 9 PageID #: 1897
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`of the remaining claim terms, phrases, or clauses at issue, they will supplement the present Joint
`
`Claim Construction and Prehearing Statement.
`
`II.
`
`DISPUTED CLAIM CONSTRUCTIONS [P.R. 4-3(b)]
`
`Pursuant to P.R. 4-3(b), the parties’ proposed constructions of disputed claim terms,
`
`phrases, or clauses are also reflected in the tables attached as Exhibits A and B, together with all
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`references from the specification or prosecution history that support the construction and an
`
`identification of any extrinsic evidence. The parties expressly reserve the right to rely on any
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`intrinsic and extrinsic evidence identified by the other party, and any evidence obtained, or that
`
`may be obtained, through claim construction discovery. The parties expressly reserve the right
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`to amend, correct, or supplement their claim construction positions and supporting evidence in
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`response to any change of position by the other party, in response to information received
`
`through claim construction discovery, including inventor depositions and expert depositions
`
`concerning claim construction declarations, or for other good cause.
`
`III. LENGTH OF CLAIM CONSTRUCTION HEARING [P.R. 4-3(c)]
`
`Defendants anticipate that the claim construction hearing will require a total of four
`
`hours. This would allow Plaintiff and Defendants two hours per side.
`
`Plaintiff anticipates that the claim construction hearing will require a total of three hours.
`
`This would allow Plaintiff and Defendants an hour and a half per side.
`
`IV.
`
`LIVE WITNESS TESTIMONY AT CLAIM CONSTRUCTION HEARING
`[P.R. 4-3(d)]
`
`Neither party intends to call witnesses live at the claim construction hearing. However,
`
`the parties have agreed that deposition testimony and affidavits of expert and fact witnesses may
`
`be used as exhibits to the Claim Construction Briefs required by P.R. 4-5.
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`4
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`

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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 3 of 9 PageID #: 1898
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`V.
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`OTHER ISSUES [P.R. 4-3(e)]
`
`According to the Docket Control Order, there is no prehearing conference scheduled
`
`before the claim construction hearing. The parties do not at this time have any other issues that
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`might be appropriately taken up at either a prehearing conference before or at the claim
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`construction hearing. Should any party become aware of such issues that it believes necessitates
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`a prehearing conference, it will notify the other party and the Court and propose dates for a
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`prehearing conference.
`
`Dated: November 2, 2015
`
`Respectfully submitted by:
`
`
`
`/s/ Derek Gilliland, with permission by
`Michael E. Jones
`
`
`
`Derek Gilliland
`Texas State Bar No. 24007239
`Attorney in Charge
`
`Edward Chin
`Texas State Bar No. 50511688
`Christian J. Hurt
`State Bar no. 24084364
`Kirk Voss
`Texas State Bar No. 24075229
`Robert Winn Cutler
`State Bar No. 24084364
`Ross Leonoudakis
`State Bar No. 24087915
`Nix Patterson & Roach, L.L.P.
`5215 N. O’Connor Blvd., Suite 1900
`Irving, Texas 75039
`972.831.1188 (telephone)
`972.444.0716 (facsimile)
`edchin@me.com
`christianhurt@nixlawfirm.com
`kirkvoss@me.com
`winncutler@nixlawfirm.com
`rossl@nixlawfirm.com
`
`William E. “Bo” Davis, III
`Texas State Bar No. 24047416
`THE DAVIS FIRM, PC
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`5
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`

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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 4 of 9 PageID #: 1899
`
`222 N. Fredonia St.
`Longview, Texas 75601
`Telephone: 903-230-9090
`Telecopier: 903-230-9661
`Email: bdavis@bdavisfirm.com`
`
`ATTORNEYS FOR PLAINTIFF DSS
`TECHNOLOGY MANAGEMENT INC.
`
`
`
`
`WILMER CUTLER PICKERING
` HALE AND DORR LLP
`James L. Quarles (admitted pro hac vice)
`1875 Pennsylvania Avenue NW
`Washington, DC 20006
`Tel.: (202) 663-6236
`Fax: (202) 663-6363
`Email: james.quarles@wilmerhale.com
`
`
`
`
`
`
`
`
`
`
`/s/ Michael E. Jones
`Michael E. Jones
`Texas Bar No. 10929400
`POTTER MINTON, P.C.
`110 North College, Suite 500
`Tyler, Texas 75702
`Tel.: (903) 597-8311
`Fax: (903) 593-0846
`Email: mikejones@potterminton.com
`
`Michael J. Summersgill (admitted pro hac vice)
`William F. Lee (admitted pro hac vice)
`Sarah Beigbeder Petty (admitted pro hac vice)
`Louis W. Tompros (admitted pro hac vice)
`Silena Paik (admitted pro hac vice)
`WILMER CUTLER PICKERING
` HALE AND DORR LLP
`60 State Street
`Boston, MA 02109
`Tel.: (617) 526-6000
`Fax : (617) 526-5000
`Email: william.lee@wilmerhale.com
`michael.summersgill@wilmerhale.com
`sarah.petty@wilmerhale.com
`louis.tompros@wilmerhale.com
`silena.paik@wilmerhale.com
`
`6
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`

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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 5 of 9 PageID #: 1900
`
`
`
`WILMER CUTLER PICKERING
` HALE AND DORR LLP
`Cosmin Maier (admitted pro hac vice)
`7 World Trade Center 250 Greenwich St.
`New York, NY 10007
`Tel.: (212) 230-8816
`Fax: (212) 230-8888
`Email: cosmin.maier@wilmerhale.com
`
`ATTORNEYS FOR DEFENDANT
`INTEL CORPORATION
`
`
`
`/s/ Gilbert A. Greene, with permission by
`Michael E. Jones
`
`
`
`Gilbert A. Greene
`State Bar No. 24045976
`James G. Warriner
`State Bar No. 24070813
`NORTON ROSE FULBRIGHT US LLP
`98 San Jacinto Boulevard, Suite 1100
`Austin, TX 78701
`Tel: 512.474.5201
`Fax: 512.536.4598
`bert.greene@nortonrosefulbright.com
`jim.warriner@nortonrosefulbright.com
`
`Dan D. Davison
`State Bar No. 05590900
`Brandy S. Nolan
`State Bar No. 24070337
`NORTON ROSE FULBRIGHT US LLP
`2200 Ross Ave., Suite 3600
`Dallas, TX 75201
`Tel: 214.855.8000
`Fax: 214.855.8200
`dan.davison@nortonrosefulbright.com
`brandy.nolan@nortonrosefulbright.com
`
`Darren Smith
`State Bar No. 24088433
`NORTON ROSE FULBRIGHT US LLP
`1301 McKinney Ave., Suite 5100
`Houston, TX 77010
`Tel: 713.651.5151
`Fax: 713.651.5246
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`7
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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 6 of 9 PageID #: 1901
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`darren.smith@nortonrosefulbright.com
`
`Deron R. Dacus
`THE DACUS FIRM, P.C.
`821 ESE Loop 323, Suite 430
`Tyler, Texas 75701
`Tel: (903) 705-1117
`Fax: (903) 705-1117
`ddacus@dacusfirm.com
`
`ATTORNEYS FOR DEFENDANT DELL INC.
`
`/s/ Kent E. Baldauf, Jr., with permission by
`Michael E. Jones
`
`
`
`Kent E. Baldauf, Jr.
`kbaldaufjr@webblaw.com
`Christian D. Ehret (Pro Hac Vice)
`cehret@webblaw.com
`THE WEBB LAW FIRM
`One Gateway Center
`420 Ft. Duquesne Boulevard, Suite 1200
`Pittsburgh, PA 15222
`T: (412) 471-8815
`F: (412) 471-4094
`
`ATTORNEYS FOR DEFENDANT
`GAMESTOP, CORP.
`
`/s/ J. Thad Heartfield, with permission by
`Michael E. Jones
`
`
`
`J. Thad Heartfield
`Texas Bar No. 09346800
`M. Dru Montgomery
`Texas Bar No. 24010800
`THE HEARTFIELD LAW FIRM
`2195 Dowlen Road
`Beaumont, Texas 77706
`Phone: 409.866.3318
`Fax: 409.866.5789
`E-mail: thad@heartfieldlawfirm.com
`dru@heartfieldlawfirm.com
`
`ATTORNEYS FOR CONN’S INC. AND
`CONN APPLIANCES, INC.
`
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`
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`8
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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 7 of 9 PageID #: 1902
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`
`
`
`
`/s/ Laura L. Chapman, with permission by
`Michael E. Jones
`
`
`
`LAURA L. CHAPMAN
`Sheppard Mullin Richter & Hampton LLP
`Four Embarcadero Center, 17th Floor
`San Francisco, CA 94111
`Telephone: (415) 774-3215
`Facsimile: (415) 434-3947
`E-mail: lchapman@sheppardmullin.com
`
`Of Counsel:
`Bridgette Agness
`Sheppard, Mullin, Richter & Hampton LLP
`333 S. Hope St., 48th Floor
`Los Angeles, CA 90071
`Telephone: 213.620.1780
`Facsimile: 213.620.1398
`E-mail: bagness@sheppardmullin.com
`
`Michael E. Jones
`Texas Bar No. 10929400
`POTTER MINTON, P.C.
`110 North College, Suite 500
`Tyler, Texas 75702
`Tel.: (903) 597-8311
`Fax: (903) 593-0846
`Email: mikejones@potterminton.com
`
`ATTORNEYS FOR DEFENDANTS AND
`COUNTER-CLAIMANTS
`WAL-MART STORES, LLC AND WAL-MART
`STORES TEXAS, LLC
`
`
`
`
`
`/s/ Harry L. Gillam, Jr., with permission by
`Michael E. Jones
`
`
`
`Harry L. Gillam, Jr.
`State Bar No. 07921800
`GILLAM & SMITH, L.L.P.
`303 S. Washington Ave.
`Marshall, Texas 75670
`Telephone: (903) 934-8450
`Facsimile: (903) 934-9257
`gil@gillamsmithlaw.com
`
`9
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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 8 of 9 PageID #: 1903
`
`
`Ronald S. Lemieux
`CA Bar No. 120822
`Vid Bhakar
`CA Bar No. 220210
`SINGULARITY LLP
`555 Twin Dolphin Drive, Suite 610
`Redwood Shores, CA 94065
`Telephone: (650) 720-4650
`Facsimile: (650) 720-4662
`rlemieux@ipsingularity.com
`vbhakar@ipsingularity.com
`
`ATTORNEYS FOR DEFENDANT AT&T
`MOBILITY LLC
`
`
`
`
`
`10
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`Case 6:15-cv-00130-RWS Document 165 Filed 11/02/15 Page 9 of 9 PageID #: 1904
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`CERTIFICATE OF SERVICE
`
`The undersigned hereby certifies that all counsel of record who are deemed to have
`
`consented to electronic service are being served with a copy of this document via the Court’s
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`CM/ECF system per Local Rule CV-5(a)(3) on November 2, 2015.
`
`/s/ Michael E. Jones
`
`
`
`
`
`
`
`11
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`

`
`etch stop layer 340 is covered by a third insulating layer,
`etch stop layer 340, overlies the TEOS layer 330 and this
`“A distinct insulating layer, for example a silicon nitride
`
`completely encapsulated.” (’552 patent at 4:51-60.)
`and spacer portion 235 so that the polysiclicon layer 220
`stop layer 240 protected the underlying TEOS layer 230
`described as an etch stop layer. The silicon nitride etch
`Hence, the description of the silicon nitride layer 240 is
`effectively etch the silicon nitride layer 240 material.
`BPTEOS material, the etchant did not etch or did not
`When the contact opening 270 was formed through the
`selectivity toward BPTEOS relative to silicon nitride.
`“The etchant utilized to make the opening had a high
`
`18.)
`etching by the etch stop layer 125.” (’552 patent at 4:13-
`device structuring and layers are protected from excessive
`exposing the device structures and layers because the
`permits subsequent etching of the substrate without risk of
`encapsulating dielectric layer 120. The etch stop layer 125
`“A distinct dielectric etch stop layer 125 overlies the
`
`Specification:
`
`region”
`effectively etched by the etchant used to create the contact
`“a material overlying the first insulating layer that is not
`
`
`
`1994) (“over”)
`Merriam Webster’s Collegiate Dictionary (10th Ed.
`
`US 6,004,875
`
`Fig. 4K; Fig. 4L; Claims
`Abstract; 4:12-17; 12:54-13:20; 13:58-52; 14:10-17;
`
`material.
`prevent etching of the adjacent or underlying
`material exposed to a specific etch process and may
`is relatively higher than an adjacent or underlying
`Generally, an etch stop material has an etch rate that
`
`insulating layer”
`“an etch stop material around or above said first
`
`(claim 1)
`
`layer”
`insulating
`said first
`material over
`“an etch stop
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Parties’ Proposed Claim Constructions for Claim Terms in U.S. Patent 6,784,552
`
`EXHIBIT A
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 1 of 8 PageID #: 1905
`
`12
`
`

`
`Specification:
`
`than or equal to 90°”
`horizontal substrate surface that is greater than 85° and less
`“a side of the insulating spacer has an angle relative to the
`
`11:63-66.)
`with a total thickness of 700 angstroms.” (‘552 patent at
`440, in this example, a silicon nitride (SixNy) layer 440,
`deposited a second distinct dielectric or etch stop layer
`“Referring to FIG. 4(F), overlying the TEOS layer 420 is
`
`9:19-56.)
`insulating material. . . . FIG. 4(L) …” (’552 patent at
`with insulating material, an etch stop layer overlying the
`sectional planar side view of a series of gates encapsulated
`insulating material. . . . FIG. 4(I) illustrates a cross-
`with insulating material, an etch stop layer overlying the
`sectional planar side view of a series of gates encapsulated
`overlying the etch stop layer. FIG. 4(H) illustrates a cross-
`material, and a distinct planarized insulating layer
`material, an etch stop layer overlying the insulating
`view of a series of gates encapsulated with insulating
`material. FIG. 4(G) illustrates a cross-sectional planar side
`an insulating etch stop layer overlying the insulating
`a series of gates encapsulated with insulating material and
`“FIG. 4(F) illustrates a cross-sectional planar side view of
`
`5:46-50.)
`for example a BPTEOS blanket layer 350.” (’552 patent at
`
`3/3/03 Amendment and Request for Reconsideration
`
`4K, 4L; Claims
`Abstract; 12:66-13:18; 13:29-35; 14:10-17; Figs. 4D,
`
`
`
`Plain and ordinary meaning.
`
`either a right
`surface that is
`to the substrate
`angle relative
`spacer has an
`insulating
`“a side of the
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 2 of 8 PageID #: 1906
`
`13
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`

`
`TEOS layer 420 retains its substantially rectangular
`Of primary significance, the spacer portion 435 of the
`TEOS layer spacer portion 435 is removed during the etch.
`only a small portion 475 (illustrated in ghost lines) of the
`rectangular or “boxy” profile. FIG. 4(K) illustrates that
`yields a TEOS layer spacer portion 435 that retains a
`TEOS layer spacer portion 435. The low selectivity etch
`nitride relative to TEOS does not significantly destroy the
`“The use of an etchant with a low selectivity for silicon
`
`than 85°.” (’552 patent at 5:4-17.)
`270, the spacer portion 235 having an angle 290 that is less
`with a spacer portion 235 adjacent to the contact opening
`polysilicon layer 220 encapsulated in a TEOS layer 230
`spacer into a sloped spacer. FIG. 2(B) presents a
`stop layer 240 will transform a substantially rectangular
`properties of the highly selective etch of the overlying etch
`originally substantially rectangular as in FIG. 2(A). The
`This result follows even where the spacer portion is
`235 is sloping or tapered toward the contact opening 270.
`230 with a spacer portion 235 wherein the spacer portion
`compared to TEOS material, however, left the TEOS layer
`contact opening 270. The selective etch for silicon nitride
`effectively removed silicon nitride layer 240 from the
`“FIG. 2(B) shows that the silicon nitride selective etch
`
`Fig. 4(K)
`
`Fig. 2(B)
`
`Fig. 2(A)
`
`(claim 1)
`
`
`
`more than 85°”
`acute angle of
`angle or an
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 3 of 8 PageID #: 1907
`
`14
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`

`
`DSS’s Infringement Contentions:
`
`History, Amendment, Feb. 6, 2004 at 5.)
`portion, and is not substantially rectangular.” (’552 File
`reproduced below. As illustrated, the spacer has a sloping
`Figure 2 shows a spacer. This portion of the figure is
`over a capacitor array of memory cells. Element 18 in
`“Dennison, et al. describes a method of forming a bit line
`
`File History:
`
`56.)
`typically produce a sloped sidewall.” (’552 patent at 2:54-
`generally not highly selective while highly selective etches
`“Etchants that provide a near 90° sidewall angle are
`
`more than 85°.” (’552 patent at 8:41-43).
`the spacer has an angle relative to the substrate surface of
`“The phrase ‘substantially rectangular’ means that a side of
`
`profile.” (’552 patent at 13:2-10.)
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 4 of 8 PageID #: 1908
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`15
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`

`
`contact opening.” (’552 patent at 13:51-53.)
`spacer portions between the conductive layers and the
`“The invention contemplates that the insulating layer has
`
`Fig. 4(B)-(D)
`
`Specification:
`
`from the contact region”
`“lateral spacer that electrically isolates the conductive layer
`
`insulating spacer below.”).)
`shown reference angle of 85°, shown in black on the
`also id. at 6 (“The sidewall spacer is steeper than the
`(DSS’ Infringement Contentions, Exhibit B at p. 7; see
`
`
`
`4L; Claims
`Abstract; 4:34-56; 13:51-65; 14:10-17; Figs. 4D, 4K,
`
`Plain and ordinary meaning.
`
`(claim 1)
`
`spacer”
`“insulating
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 5 of 8 PageID #: 1909
`
`16
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`

`
`small alignment tolerance relative to a gate electrode or
`region, and a device including a contact opening with a
`spacer erosion of an insulating layer on an enclosed contact
`“The invention relates to a process for minimizing lateral
`
`65.)
`added to the contact opening 460.” (’552 patent at 12:61-
`415 from a conductive contact that will subsequently be
`additional spacer material to insulate the polysilicon layer
`spacer portion 435 of the TEOS layer 420 serves as
`“Thus, the remaining etch stop material adjacent to the
`
`49.)
`substantially rectangular profile.” (’552 patent at 11:35-
`the spacers 435 such that the spacers 435 have a
`FIG. 4(D). . . . As shown in FIG. 4(C), care is taken to etch
`435 of the TEOS layer 430 are demarked by ghost lines in
`adjacent to the polysilicon layer. . . . The spacer portions
`spacer portions extending into the contact openings and
`layer of TEOS material 430 over the structure and etching
`contact openings by depositing an additional of conformal
`between the polysilicon layer 415 of the gates and the
`“Referring to FIGS. 4(C) and 4(D), spacers are formed
`
`profile.” (’552 patent at 7:30-36.)
`wherein the spacer portion has a substantially rectangular
`with a lateral spacer portion adjacent the contact region
`comprises an insulating layer overlying a conductive layer
`The insulating spacers are etched so that the device
`structure to isolate the conductive portion of the device.
`“Next, the insulating spacers are added to the device
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 6 of 8 PageID #: 1910
`
`17
`
`

`
`metallization layer, local interconnect layer, or structure
`other layer or structure, for example, an underlying
`substrate, such as a source or drain, or may expose some
`opening may expose a device region within the silicon
`will be used to refer to contact openings and/or via. The
`invention, henceforth ‘contact opening’ or ‘contact region’
`referred to as a ‘via’. For purposes of the claimed
`such as an opening through an intermetal dielectric layer is
`‘contact opening’, while an opening in other oxide layers
`between polysilicon and a first metal layer is called a
`diffusion region or an opening through a dielectric layer
`“Generally, an opening through a dielectric exposing a
`
`Specification:
`
`“contact openings and/or vias”
`
`“contact openings and/or vias”
`
`PARTIES’ AGREED CONSTRUCTION:
`
`PARTIES’ AGREED CONSTRUCTION:
`
`TEOS spacer portion 235.” (’552 patent at 4:39-42.)
`region 270 by an insulating spacer portion, for example a
`“The polysilicon layer 220 is separated from the contact
`
`4:20-25.)
`provided for the diffusion region 140.” (’552 patent at
`shorts to the polysilicon layer 110 when the contact 130 is
`polysilicon layer 110, the dielectric spacer 150 prevents
`110 from the etchant is misaligned with respect to the
`“Even if a photoresist that protects the polysilicon layer
`
`other structure.” (’552 patent at 7:15-20.)
`
`(claim 1)
`
`region”
`“contact
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 7 of 8 PageID #: 1911
`
`18
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`

`
`
`
`(’552 patent at 6:48-52.)
`represents the width at the base of the contact region 360.”
`the width at the top of the planarized layer and w2
`for the same contact in prior art structures. w1 represents
`“FIG. 3 indicates the difference in contact opening widths
`
`at 5:41-51.)
`Adjacent to the gate is a contact region 360.” (’552 patent
`contact region undergoing an RF sputter etch 380 . . . .
`“FIG. 3 illustrates a prior art substrate with a gate and a
`
`through the BPTEOS layer 250.” (’552 patent at 4:49-51.)
`“In FIG. 2(A), a contact opening 270 has been opened
`
`region 270.” (’552 patent at 4:38-40.)
`“Adjacent to the polysilicon layer 220 is a contact opening
`
`such as a gate.” (’552 patent at 1:33-45.)
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-1 Filed 11/02/15 Page 8 of 8 PageID #: 1912
`
`19
`
`

`
`“Openings (not shown) are formed on the surface of
`
`gate and the diffusion region.” (’924 patent at 3:1-11.)
`to provide electrical connection between the polysilicon
`conducting plug filling at least partially the via opening
`layer contains a via opening therein, and an electrically
`covers the poly silicon gate and the diffusion region, the
`contacting the diffusion region, an insulator layer which
`the top surface of the substrate adjacent to but not
`adjacent to the top surface, a polysilicon gate formed on
`surface, a diffusion region formed in the substrate
`provided which includes a silicon substrate having a top
`“In a preferred embodiment, a semiconductor structure is
`
`as an implantation mask.” (’924 patent at 3:49-55.)
`ion implantation process. The photoresist layer is used
`etching to form openings for the diffusion regions for the
`by patterning through a photoresist layer and then
`surface of the silicon substrate 74. This is accomplished
`are first formed by an ion implantation process in the
`“Diffusion regions 70 and 72 of either N+ or P+ doping
`
`Figs. 1A, 1B, 2A, 2B, 3A, 3B
`
`1994) (“formed”)
`Merriam Webster’s Collegiate Dictionary (10th Ed.
`US 5,747,837
`US 6,163,057
`US 8,405,132
`Introduction to VLSI Systems, Mead & Conway (1980)
`
`that contains dopants implanted in the silicon substrate”
`“conductive terminal region, such as a source or drain,
`
`formed in said substrate”
`“conductive terminal region such as a source or drain
`
`Specification:
`
`Abstract; 3:41-51; 4:6-10; 5:13-21; Fig. 3B; Claims
`
`(claim 1)
`
`substrate”
`in said
`region formed
`“diffusion
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Parties’ Proposed Claim Constructions for Claim Terms in U.S. Patent 5,965,924
`
`EXHIBIT B
`
`Case 6:15-cv-00130-RWS Document 165-2 Filed 11/02/15 Page 1 of 15 PageID #: 1913
`
`20
`
`

`
`channel forms by inverting the silicon surface with gate
`The silicon bulk is the portion of silicon in which the
`silicon bulk, the whole structure remains “bulk” silicon.
`the substrate. Even after features are machined into
`the fins are indistinguishable from the bulk, comprising
`multiplicity of fins incorporated in the silicon substrate,
`the image. Since the devices are incorporated into a
`“The silicon substrate is the dark layer at the bottom of
`
`DSS’s Infringement Contentions:
`
`at pp. 5-6.)
`fill the contact hole.” (Amendment date Aug. 14, 1996
`diffusion regions. A refractory metal is then deposited to
`similar to the width of the corresponding source/drain
`insulating material. The first contact hole has a length
`device which has a contact hole opened in a layer of
`“Nishigoori ‘210 discloses a MOS type semiconductor
`
`File History:
`
`1:33-43)
`connection with the diffusion region 16.” (’924 patent at
`method, to form a gate electrode 14 for making electrical
`patterned and etched, typically by a reactive ion etching
`substrate 12. Thereafter, the polysilicon layer is
`removed and a layer of polysilicon is deposited onto
`resistance. Subsequently, the photoresist layer is
`surface dopant concentration for improved contact
`process is performed at the openings to increase the
`formation of buried contacts. An ion implantation
`substrate 12 to expose sections of the substrate for the
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-2 Filed 11/02/15 Page 2 of 15 PageID #: 1914
`
`21
`
`

`
`Infringement Contention, Exhibit A at p. 3.)
`adjacent to top surface of the substrate.” (DSS’
`“The diffusion region appears beneath the metal plugs
`
`(DSS’ Infringement Contention, Exhibit A at p. 3.)
`
`
`
`Contentions, Exhibit A at p. 2.)
`the fin structure, has a top surface.” (DSS’ Infringement
`channel characteristic. The silicon substrate, including
`fin that the channel forms owing to its three-dimensional
`substrate includes the fin because it is within the silicon
`voltage applied across the gate oxide. Thus, the silicon
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-2 Filed 11/02/15 Page 3 of 15 PageID #: 1915
`
`22
`
`

`
`surface, a diffusion region formed in the substrate
`provided which includes a silicon substrate having a top
`“In a preferred embodiment, a semiconductor structure is
`
`as an implantation mask.” (’924 patent at 3:49-55.)
`ion implantation process. The photoresist layer is used
`etching to form openings for the diffusion regions for the
`by patterning through a photoresist layer and then
`surface of the silicon substrate 74. This is accomplished
`are first formed by an ion implantation process in the
`“Diffusion regions 70 and 72 of either N+ or P+ doping
`
`Figs. 1A, 1B, 2A, 2B, 3A, 3B
`
`1994) (“formed”)
`Merriam Webster’s Collegiate Dictionary (10th Ed.
`US 5,747,837
`US 6,163,057
`US 8,405,132
`Introduction to VLSI Systems, Mead & Conway (1980)
`
`that contains dopants implanted in the silicon substrate”
`“conductive terminal region, such as a source or drain,
`
`a silicon substrate”
`“conductive terminal region such as a source or drain in
`
`Specification:
`
`Abstract; 3:41-51; 4:6-10; 5:13-21; Fig. 3B; Claims
`
`(DSS’ Infringement Contention, Exhibit A at p. 3.)
`
`
`
`(claim 7)
`
`substrate”
`silicon
`region in a
`“diffusion
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-2 Filed 11/02/15 Page 4 of 15 PageID #: 1916
`
`23
`
`

`
`at pp. 5-6.)
`fill the contact hole.” (Amendment date Aug. 14, 1996
`diffusion egions. A refractory metal is then deposited to
`similar to the width of the corresponding source/drain
`insulating material. The first contact hole has a length
`device which has a contact hole opened in a layer of
`“Nishigoori ‘210 discloses a MOS type semiconductor
`
`File History:
`
`1:33-43)
`connection with the diffusion region 16.”(’924 patent at
`method, to form a gate electrode 14 for making electrical
`patterned and etched, typically by a reactive ion etching
`substrate 12. Thereafter, the polysilicon layer is
`removed and a layer of polysilicon is deposited onto
`resistance. Subsequently, the photoresist layer is
`surface dopant concentration for improved contact
`process is performed at the openings to increase the
`formation of buried contacts. An ion implantation
`substrate 12 to expose sections of the substrate for the
`“Openings (not shown) are formed on the surface of
`
`gate and the diffusion region.” (’924 patent at 3:1-11.)
`to provide electrical connection between the polysilicon
`conducting plug filling at least partially the via opening
`layer contains a via opening therein, and an electrically
`covers the poly silicon gate and the diffusion region, the
`contacting the diffusion region, an insulator layer which
`the top surface of the substrate adjacent to but not
`adjacent to the top surface, a polysilicon gate formed on
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-2 Filed 11/02/15 Page 5 of 15 PageID #: 1917
`
`24
`
`

`
`“The diffusion region appears beneath the metal plugs
`
`(DSS’ Infringement Contention, Exhibit A at p. 3.)
`
`
`
`Contention, Exhibit A at p. 2.)
`the fin structure, has a top surface.” (DSS’ Infringement
`channel characteristic. The silicon substrate, including
`fin that the channel forms owing to its three-dimensional
`substrate includes the fin because it is within the silicon
`voltage applied across the gate oxide. Thus, the silicon
`channel forms by inverting the silicon surface with gate
`The silicon bulk is the portion of silicon in which the
`silicon bulk, the whole structure remains “bulk” silicon.
`the substrate. Even after features are machined into
`the fins are indistinguishable from the bulk, comprising
`multiplicity of fins incorporated in the silicon substrate,
`the image. Since the devices are incorporated into a
`“The silicon substrate is the dark layer at the bottom of
`
`DSS’s Infringement Contentions:
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-2 Filed 11/02/15 Page 6 of 15 PageID #: 1918
`
`25
`
`

`
`interconnect strap to shunt from a gate polysilicon to a
`“One of such methods is to use a metallic local
`
`patent at 1:50-54.)
`as a tungsten plug is then deposited into hole 24.” (’924
`hole to improve adhesion. A refractory metal plug such
`titanium nitride is normally deposited into the contact
`contact holes 24, a thin layer of titanium tungsten or
`Figs. 1A, 1B, 2A, 2B, 3A, 3B“After the formation of the
`
`Specification:
`
`separate from a strapping shunt layer”
`“electrically conducting material deposited into a via and
`
`(DSS’ Infringement Contention, Exhibit A at p. 3.)
`
`
`
`Claims
`Abstract; 3:1-14; 3:41-45; 4:14-17; 5:13-21; Fig. 3B;
`
`11/07/96 Office Action; 6/10/97 ROA
`
`
`
`Plain and ordinary meaning.
`
`(claim 1)
`
`plug”
`“conducting
`
`Infringement Contention, Exhibit A at p. 3.)
`adjacent to top surface of the substrate.” (DSS’
`
`Defendants’ Proposed Construction and Support
`
`Plaintiff’s Proposed Construction and Support
`
`Claim Term
`
`Case 6:15-cv-00130-RWS Document 165-2 Filed 11/02/15 Page 7 of 15 PageID #: 1919
`
`26
`
`

`
`“It is another further object of the present invention to
`
`patent at 2:56-59.)
`require the use of a local interconnect strap.” (’924
`polysilicon gate and a diffusion region that does not
`provide a metal plug local interconnect between a
`“It is yet another object of the present invention to
`
`intensive method.” (’924 patent at 2:32-34.)
`polysilicon gate and a diffusion region, is a process-
`accomplishes the electrical connection between a
`“The local interconnect strap method, even though
`
`patent at 2:17-31.)
`second insulating layer 60 of a dielectric material.” (’924
`second metal plug 54 is formed in a via opened in the
`region 36 can be connected to the Metal I layer 56. The
`deposition of another metal plug 54 such that diffusion
`shunt 52 is also deposited on metal plug 48 to allow the
`interconnect shunt layer 50 is deposited. A separate
`interconnect masking/etching process, a local
`the vias. After a tungsten plug etch back and a