United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,338,700
`
`Dennison et al.
`
`[45] Date of Patent:
`
`Aug. 16, 1994
`
`US005338700A
`
`Ema et al. “3—Dimensiona1 Stacked Capacitor Cell for
`16M and 64M DRAMs”, IEDM 1988, pp. 592-595.
`Hayashide et al., “Fabrication of Storage Capacitance-
`Enhanced Capacitors with a Rough Electrode,” Ext.
`Abs. of 22nd Conf. on SSDM 1990, pp. 869-872.
`Miyagawa et al., “Two stip Deposited Rugged Surface
`Storagenode and Self Aligned Bitline—Contact Pene-
`trating Cellplate for 64Mb DRAM STC Cell,” pp. 9-10,
`(no date).
`
`Primary Examiner—Brian E. Hearn
`Assistant Examiner-Chandra Chaudhari
`Attorney, Agent, or Fz'rm-Wells, St. John, Roberts,
`Gregory & Matkin
`
`[57]
`
`ABSTRACI‘
`
`A method of forming a bit line over capacitor array of
`memory cells includes providing first conductive mate-
`rial pillars within first contact openings downwardly to
`active (source/drain) areas for ultimate connection with
`bit lines. A covering layer of insulating material is pro-
`vided over the first pillars, and contact openings pro-
`vided therethrough to electrically connect with other
`active (source/drain) areas for formation of capacitors.
`Capacitors are then provided within the capacitor
`contact openings. An overlying layer of insulating ma-
`terial is then provided over the covering layer of insu-
`lating material and over the capacitors. Bit line contact
`openings are then provided through the overlying layer
`and the covering layer to the first pillar upper surfaces.
`Then, a digit line layer of conductive material is pro-
`vided atop the wafer and within the bit line contact
`openings, the digit line layer electrically connecting
`with the first pillar upper surfaces.
`
`[54] METHOD OF FORMING A BIT LINE OVER
`CAPACITOR ARRAY OF MEMORY CELLS
`
`[75]
`
`Inventors: Charles H. Dennison; Aftab Ahmad,
`both of Boise, Id.
`
`[73] Assignee: Micron Semiconductor, Inc., Boise,
`Id.
`
`[21] Appl. No.2 47,668
`
`[22] Filed:
`
`Apr. 14, 1993
`
`Int. Cl.5 ............................................. H01L 21/72
`[51]
`[52] U.S. Cl. ...................................... 437/60; 437/233;
`437/919
`[58] Field of Search ..................... 437/47, 52, 60, 233,
`437/919; 148/DIG. 14; 257/306
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`7/1987 Kuesters .............................. 257/306
`4,855,801
`2/1991 Ozaki et al.
`257/306
`4,994,893
`5/1991 Ku et al.
`.... ... .....
`..... 437/233
`5,010,039
`9/1991 Wakamiya et al.
`257/306
`5,047,817
`5,166,090 11/1992 Kim et al.
`.... ......
`. .... 437/233
`5,206,183
`4/1993 Dennison ............................ .. 437/60
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`6/1988 Japan .
`63-133565
`1-100960 4/1989 Japan .
`1-215060 8/1989 Japan .
`OTHER PUBLICATIONS
`
`Inoue et al., “A Spread Stacked Capacitor (SSC) Cell
`for 64 MBit DRAMS”, IEDM 1989, pp. 31-34.
`
`33 Claims, 20 Drawing Sheets
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`METHOD OF FORMING A BIT LINE OVER
`CAPACITOR ARRAY OF MEMORY CELLS
`
`TECHNICAL FIELD
`
`This invention relates generally to formation of a bit
`line over capacitor array of memory cells.
`BACKGROUND OF THE INVENTION
`
`As DRAMs increase in memory cell density, there is
`a continuous challenge to maintain sufficiently high
`storage capacitance despite decreasing cell area. Addi-
`tionally, there is a continuing goal to further decrease
`cell area. The principal way of increasing cell capaci-
`tance is through cell structure techniques. Such tech-
`niques include three-dimensional cell capacitors, such as
`trenched or stacked capacitors.
`Conventional stacked capacitor DRAM arrays utilize
`either a buried bit line or a non-buried bit line construc-
`tion. With buried bit line constructions, bit lines are
`provided in close vertical proximity to the bit line
`contacts of the memory cell
`field effect transistors
`(FETs), with the cell capacitors being formed horizon-
`tally over the top of the word lines and bit lines. With
`non-buried bit line constructions, deep vertical contacts
`are made through a thick insulating layer to the cell
`FETs, with the capacitor constructions being provided
`over the word lines and beneath the bit lines. Such
`non-buried bit line constructions are also referred to as
`“capacitor-under‘-bit line” or “bit line-over—capacitor”
`constructions, and are the subject of this invention.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Preferred embodiments of the invention are de-
`
`scribed below with reference to the following accompa-
`nying drawings.
`FIG. 1 is a diagrammatic section of a semiconductor
`wafer shown at one processing step in accordance with
`the invention.
`
`20
`
`25
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`30
`
`FIG. 2 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 1.
`FIG. 2A is a diagrammatic section of the FIG. 1
`wafer illustrated at an alternate processing step subse-
`quent to that shown by FIG. 1.
`FIG. 3 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 2.
`FIG. 4 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 3.
`FIG. 4A is a diagrammatic section of the FIG. 2A
`wafer illustrated at a processing step subsequent to that
`shown by FIG. 2A, and corresponds in sequence with
`the step shown by FIG. 4.
`FIG. 5 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 4.
`FIG. 5A is a diagrammatic section of the FIG. 2A
`wafer illustrated at a processing step subsequent to that
`shown by FIG. 4A, and corresponds in sequence to the
`step shown by FIG. 5.
`FIG. 6 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 5.
`FIG. 6B is a diagrammatic section of the FIG. 5
`wafer illustrated at an alternate processing step subse-
`
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`quent to that shown by FIG. 5, and corresponds in
`sequence to that shown by FIG. 6. There is no FIG. 6A.
`FIG. 7 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 6.
`FIG. 7B is a diagrammatic section of the FIG. 6B
`wafer illustrated at processing step subsequent to that
`shown by FIG. 6B, and corresponds in sequence to the
`step shown by FIG. 7. There is no FIG. 7A.
`FIG. 8 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 7.
`FIG. 8C is a diagrammatic section of the FIG. 7
`wafer illustrated at a processing step subsequent to that
`shown by FIG. 7, and corresponds in sequence to the
`step shown by FIG. 8. There are no FIGS. 8A or 8B.
`FIG. 9 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 8.
`FIG. 9B is a diagrammatic section of the FIG. 7B
`wafer illustrated at a processing step subsequent to that
`shown by FIG. 7B, and corresponds in sequence to the
`step shown by FIG. 9. There is no FIG. 9A.
`FIG. 9C is a diagrammatic section of the FIG. 8C
`wafer illustrated at a processing step subsequent to that
`shown by FIG. 8C, and corresponds in sequence to the
`step shown by FIG. 9.
`FIG. 10 is a diagrammatic section of the FIG. 1 wafer
`illustrated at a processing step subsequent to that shown
`by FIG. 9.
`FIGS. 11 and 11B are diagrammatic sections of a
`wafer processed in accordance with alternate aspects of
`the invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`This disclosure of the invention is submitted in fur-
`therance of the constitutional purposes of the U.S. Pa-
`tent Laws “to promote the progress of science and
`useful arts” (Article 1, Section 8).
`In accordance with one aspect of the invention, a
`method of forming a bit line over capacitor array of
`memory cells comprises:
`providing an array of substantially electrically iso-
`lated word lines atop a semiconductor wafer;
`providing active areas about the word lines to define
`an array of memory cell FETs, the active areas being
`defined by a first active region for electrical connection
`with a memory cell capacitor and a second active re-
`gion for electrical connection with a bit line;
`providing a planarized first layer of an insulating
`material over the word lines and active areas, the plana-
`rized layer of insulating material having an upper sur-
`face which is above the word lines;
`providing first contact openings through the first
`layer of insulating material to second active regions;
`providing first conductive material pillars within the
`first contact openings, the first pillars having upper
`surfaces which are elevationally above the word lines;
`providing a covering layer of insulating material over
`the planarized first layer of insulating material and first
`pillars;
`providing capacitor contact openings through the
`covering layer to electrically connect with the first
`active regions;
`providing capacitors within the capacitor contact
`openings;
`
`

`
`3
`providing an overlying layer of insulating material
`over the covering layer of insulating material and over
`the capacitors;
`providing bit line contact openings through the over-
`lying layer and the covering layer to the first pillar
`upper surfaces; and
`providing a digit line layer of conductive material
`atop the wafer and within the bit line contact openings,
`the digit line layer electrically connecting with the first
`pillar upper surfaces.
`The word “contact” as used in this document in-
`cludes container-wide openings, such as for forming
`capacitor constructions.
`Multiple preferred embodiments are collectively
`shown by the accompanying drawings, as will become
`apparent from the continuing discussion. Related tech-
`nical disclosures can be found in our U.S. patent appli-
`cation Ser. No. 08/044,824, filed on Apr. 7, 1993 and
`entitled “Semiconductor Processing Methods Of Form-
`ing Stacked Capacitors”, and U.S. patent application
`Ser. No. 07/838,537, now U.S. Pat. No. 5,206,183, filed
`on Feb. 19, 1992, and entitled “Method Of Forming A
`Bit Line Over Capacitor Array of Memory Cells”,
`which are each hereby incorporated by reference.
`Referring first to FIG. 1, a semiconductor wafer is
`indicated generally by reference numeral 10. Wafer 10
`has been provided with an array of substantially electri-
`cally isolated word lines, such as the illustrated word
`lines 12, 14 and 16. Such word lines are of a conven-
`tional construction having a lowermost gate oxide, a
`lower polysilicon layer, an overlying silicide layer such
`as tungsten silicide, and insulating caps and side insulat-
`ing spacers 18. Such spacers and caps 18 preferably
`comprise an insulative nitride, such as Si3N4. A thin
`layer 20 of Si3N4 is provided atop the wafer to function
`as a diffusion barrier. Layer 20 has a thickness which is
`preferably from about 100 Angstroms to about 250
`Angstroms.
`Active areas are provided about the word lines, such
`as active regions 22, 24 and 26, to define an array of
`memory cell FETs. The discussion proceeds with refer-
`ence to a PET formed with word line 14, which will be
`provided with a capacitor construction for definition of
`a single memory cell. Active region 26 defines a first
`active region for electrical connection with a memory
`cell capacitor (described below). Active region 24 de-
`fines a second active region for electrical connection
`with a bit line (described below). Field oxide 19 is pro-
`vided, as shown.
`A planarized first layer 28 of an insulating material is
`provided over the word lines and active area. An exam-
`ple and preferred material is borophosphosilicate glass
`(BPSG) which is planar-ized back by chemical mechani-
`cal polishing (CMP) to an elevation of from about 2000
`Angstroms to about 4000 Angstroms above the word
`line nitride caps 18 which are positioned adjacent the
`active areas, as opposed to the word lines over the field
`oxide. Such provides a planarized ‘upper surface 30
`which is elevationally above the word lines.
`Referring to FIG. 2, a series of first contact openings
`32 is provided through first layer 28 to second active
`regions 24 to provide bit line connections. Such would
`typically be conducted by photomasking and dry chem-
`ical etching of BPSG selective to nitride. An example
`etch chemistry would include CHF3 and 02 at low 02
`flow rate 6.8.,
`less than 5% 02 by volume in a
`CHF3/O2 mixture), or the combination of CF4, AR,
`CHZF2 and CHF3. Thereafter, a blanket etch of the
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`wafer is conducted to etch nitride layer 20 selectively to
`silicon to upwardly expose active area 24. An example
`etch chemistry would include a combination of CHF3
`and CF4. The principle purpose of barrier layer 20 is to
`prevent diffusion of boron or phosphorous atoms from
`BPSG layer 28 into active areas 24 and 26. Caps 18 are
`preferably comprised of nitride (Si3N4) where layer 28
`is comprised of oxide, such that the contact etch to
`produce first contacts 32 will stop relative to word lines
`spacers and caps 18.
`Thereafter, first conductive material pillars 34 are
`provided within first contact openings 32. An example
`and preferred material for pillars 34 is in situ As doped
`polysilicon. Such is preferably provided by deposition
`of a polysilicon layer, followed by CMP to upper sur-
`face 30 of BPSG layer 28. Such produces first pillar
`upper surfaces 36 which are elevationally above the
`word line and coincide with upper surfaces 30 of BPSG
`layer 28.
`Altemately in accordance with the invention, buried
`capacitor contacts/containers and associated pillars can
`be provided along with the bit line contacts and pillars.
`Specifically, FIG. 2A illustrates a wafer 10A having
`second contact openings 38 extending through first
`layer 28 to first active regions 26. Such are filled with
`second conductive material pillars 40 having upper
`surfaces 42 coinciding with surfaces 30 and 36. Such
`would be provided simultaneously with the creation of
`contact openings 32 and pillars 34, and accordingly
`preferably comprise in situ conductively doped polysili-
`con.
`
`Referring to FIG. 3, a layer 44 of insulating material
`is provided to a thickness of from about 500 Angstroms
`to about 3000 Angstroms, with about 1500 Angstroms
`being most preferred. Layer 44 preferably principally
`comprises an oxide, such as SiOz deposited by decom-
`position of tetraethylorthosilicate (TEOS). A layer 46 is
`deposited atop TEOS layer 44. Layer 46 preferably
`comprises Si3N4 deposited by low pressure chemical
`vapor deposition (LPCVD) to a thickness from about
`100 Angstroms to about 1000 Angstroms, and thus de- '
`fining an upper surface 48. In combination, and for
`purposes of the continuing discussion, layers 44 and 46
`constitute a planarized base layer 50 having a defined
`first thickness (preferably about 2000 Angstroms) and
`uppermost region defined by layer 46. Thus in accor-
`dance with the preferred embodiment, base layer 50 is
`not homogeneous, with uppermost region 46 being
`formed of a different material from remaining portions
`44 of the base layer. An intermediate layer 52 of insulat-
`ing material is provided atop uppermost region 46 of
`base layer 50. The insulating material of intermediate
`layer 52 is different in composition from the insulating
`material of uppermost region 46, with the insulating
`material of intermediate layer 52 being selectively etch-
`able relative to the insulating material of such upper-
`most region 46. An example and preferred material for
`layer 52 is BPSG deposited to a thickness of approxi-
`mately 7500 Angstroms. As illustrated, and for purposes
`of the continuing discussion, intermediate layer 52 and
`base layer 50 in combination constitute a covering layer
`54. Thus in the illustrated and preferred embodiment,
`covering layer 54 is not homogeneous.
`Referring to FIG. 4, capacitor contact openings 56
`are provided through covering layer 54 to electrically
`connect with first active regions 26. Such would be
`conducted by a series of oxide and nitride etches until
`first active area 26 is upwardly exposed. FIG. 4A se-
`
`

`
`5
`quentially illustrates processing of wafer 10A to pro-
`duce capacitor contact openings 56a, where second
`pillars 40 were provided. Where such pillars 40 are
`provided and comprise polysilicon, the etch is con-
`ducted to finally be selective to both polysilicon and
`largely to nitride. A layer 58 (FIGS. 4 and 4A) of con-
`ductive material is provided over covering layer 54
`Cmtermediate layer 52) and within capacitor contact
`opening 56. Conductive material layer 58 has an outer
`surface 60. Layer 58 preferably comprises in situ As
`doped hemispherical grain (I-ISG) polysilicon.
`Referring to FIG. 5, conductive material from atop
`covering layer 54 is removed preferably by CMP tech-
`nique to define isolated cell storage node containers 62
`which electrically connect with first active regions 26.
`FIG. 5A illustrates a slightly differently configured
`isolated container 62a which connects through second
`pillars 40 electrically with first active regions 26. For
`purposes of the continuing discussion, isolated cell stor-
`age node containers 62 define or have internal sidewalls
`64 and external sidewalls 66 (FIG. 5).
`Insulating material of covering layer 54 is removed to
`expose only a portion of external sidewalls 66 of isolated
`cell storage node containers 62. Specifically, intermedi-
`ate layer 52 is selectively etched relative to the material
`of isolated capacitor storage node 62 and uppermost
`region 46 of base layer 50. In such manner, uppermost
`region 46 of base layer 50 is utilized as an etch stop
`during such etching. Where uppermost region 46 com-
`prises nitride, intermediate layer 52 comprises BPSG,
`and the isolated capacitor storage nodes comprise
`.po1ysilicon, an example suitable etch chemistry would
`include dilute HF (l0:l H2O:HF) wet etch.
`Referring to FIG. 6, a conventional or other suitable
`capacitor cell dielectric layer 68 is provided uniformly
`on the wafer atop isolated storage nodes 62. Thus, insu-
`lating material of base layer 50 is interposed between
`first pillar upper surfaces 36 and capacitor cell dielectric
`layer 68. A conductive capacitor cell layer 70 is pro-
`vided atop capacitor cell dielectric layer 68, thus defin-
`ing an array of memory cell capacitors 72 on the wafer.
`Layer 70 has an outer surface 71. Individual memory
`cell capacitors, such as the illustrated capacitor 72, of
`the array are thus provided within the capacitor contact
`openings, and are defined by an outwardly projecting
`container structure having a projecting outermost sur-
`face 74. Layer 70 preferably comprises conductively
`doped polysilicon.
`Ari electrically insulative nitride oxidation barrier
`layer 76, such as Si3N4, is provided atop cell capacitor
`layer 70 to a thickness of from about 150 Angstroms to
`about 1500 Angstroms. The purpose of such layer is
`described below.
`An overlying layer 78 of insulating material is pro-
`vided over oxidation barrier layer 76 and correspond-
`ingly conductive capacitor cell layer 70, and preferably
`comprises BPSG. Thus, an overlying layer of insulating
`material is provided over covering layer 54 and over
`the capacitors 72. Overlying layer 78 is planarized back
`to a second thickness above outermost surface 74, with
`the second thickness being greater than the first thick-
`ness of base layer 50. An example second thickness
`would be 7000 Angstroms.
`FIG. 6B illustrates a wafer 10B showing an alternate
`process where the second thickness is not greater than
`the first thickness, with the second thickness being ap-
`proximately 4000 Angstroms. The significance of the
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`second thickness relative to the first thickness will be-
`come apparent from the continuing discussion.
`Referring to FIG. 7, preliminary bit
`line contact
`openings 80 are provided through overlying layer 78,
`oxidation barrier layer 76, conductive capacitor cell
`layer 70, and cell capacitor dielectric layer 68 over first
`pillars 34, in an anisotropic progressive manner, to es-
`sentially stop on uppermost region 46 of base layer 50.
`Preliminary bit contact openings 80 have interior side-
`walls 82 which include a pair of exposed edges 84 of cell
`polysilicon layer 70. At the latter stages during such
`anisotropic etch of polysilicon layer 70, conditions are
`modified slightly to induce an isotropic etch to obtain
`an undercut etch into polysilicon exposed edges 84, as
`shown. Wafer 10 is then exposed to oxidizing ambient
`conditions to oxidize the cell polysilicon exposed edges
`to form insulating SiO2 regions 86 (FIG. 8). Example
`oxidizing ambient conditions to produce the desired
`regions 86 would include H2 and 02 at 850° C. in a
`conventional atmospheric furnace tube. A reason for
`undercut into cell polysilicon layer 70 is to prevent
`regions 86 from undesirably projecting considerably
`into preliminary bit line contact opening 80.
`Exposure of a wafer to oxidizing ambient conditions
`typically causes oxidation of silicon, and even that sili-
`con which underlies such insulating layers as phospho-
`silicate glass (PSG) and BPSG. In accordance with an
`aspect of the invention, nitride oxidation barrier layer
`76 during exposure to an oxidizing ambient inhibits
`oxidation of outer surface 71 of cell polysilicon layer 70
`which otherwise could occur through material of over-
`lying layer 78. Additionally, uppermost region/layer 46
`during oxidizing ambient exposure inhibits oxidation of
`the lower portion of outer sidewalls 66 of isolated ca-
`pacitor storage node 72.
`FIG. 8C illustrates a wafer 10C where an alternate
`technique has been employed for isolating conductive
`cell edges 84. Such occurs by deposition of an insulative
`oxide or nitride layer 88. Such a technique has the
`drawback of diminishing the width of preliminary bit
`line contact opening 80, and thus the quantity of con-
`ductive material which will ultimately be used to fill
`such opening.
`Referring to FIG. 9, base layer 50 and overlying layer
`78 are blanket etched without photomasking to extend
`preliminary bit line contact opening 80 to first pillar
`upper surface 36, thus defining a completed bit line
`contact opening 90. Thus, a bit line contact opening 90
`is provided through overlying layer 78 and covering
`layer 54. Such an etch also leaves insulating material of
`overlying layer 78 atop projecting outermost surfaces
`74 of the individual capacitor cell containers. Blanket
`etching in this manner is enabled by second thickness of
`overlying layer 78 above outermost surfaces 74 being
`greater than the first thickness of base layer 50. Slight
`undesired misalignment of contact 90 relative to plug 34
`is shown, causing some overetch into insulating layer
`28.
`FIG. 7B illustrates an alternate embodiment wherein
`the second thickness was not made to be greater than
`the first thickness. Here, the etch for the bit line contact
`to the pillar is not stopped on uppermost region/layer
`46 for purposes of electrically insulating the exposed
`conductive cell layer edges. Rather, complete etching
`of a bit line contact opening 90b is conducted inwardly
`to upwardly expose first pillar upper surface 36. To
`insulate such exposed edges, FIG. 9B illustrates deposi-
`tion of a thin oxide or nitride layer 92 which has been
`
`

`
`7
`subjected to a spacer etch. FIG. 9C illustrates a step
`subsequent to that of FIG. 8C for extending the contact
`to upper surface 36 of first pillars 34.
`Referring to FIG. 10, a digit line layer 94, such as
`metal or conductively doped polysilicon, is provided
`atop the wafer and within the complete bit line contact
`openings 90, and thus electrically connects with first
`pillar upper surfaces 36 for establishing electrical con-
`nection with second active regions 24.
`FIG. 11 illustrates an alternate process whereby cell
`polysilicon in the form of layer 70a is effectively pat-
`terned prior to deposition of overlying layer 78. Thus
`the bit line contact 90a’ is required to be provided only
`through overlying layer 78 and covering layer 54 to
`expose bit pillar 34 upper surface 36. From FIG. 11, a
`digit line layer of conductive material would be pro-
`vided atop wafer 10:! and within bit line contact open-
`ings 90d, with the digit line layer electrically connecting
`with the first pillar upper surfaces 36.
`FIG. 12 illustrates a slightly modified process relative
`to that shown by FIG. 11. Here, pillar 34e has been
`fabricated to be sufficiently wide such that open cross
`section of contact We is assured of falling entirely
`within the confines of pillar surface area 36e. When the
`bit contact poly pillar (i.e., 34e) significantly overlaps
`relative to the bit contact (i.e., 90e), the bit contact
`photo/etch can be combined with the peripheral
`contact photo/etch for process simplification. Note that
`in forming peripheral contacts, the etch step will etch
`insulators 78, 54, 28 and 20 for active area contacts, or
`insulators 78, 54, 28, 20 and 18 for poly l (word line
`poly) contacts, with all such etching being selective to
`‘ silicon. In accordance with this aspect of the invention,
`the probable larger size of area 36e would probably
`require an overall increase in memory cell size, but the
`processing steps are reduced.
`In compliance with the statue, the invention has been
`described in language more or less specific as to struc-
`tural and methodical features. It is to be understood,
`however, that the invention is not limited to the specific
`features shown and described, since the means herein
`disclosed comprise preferred forms of putting the in-
`vention into effect. The invention is, therefore, claimed
`in any of its forms or modifications within the proper
`scope of the appended claims appropriately interpreted
`in accordance with the doctrine of equivalents.
`We claim:
`1. A method of forming a bit line over capacitor array
`of memory cells comprising:
`providing an array of substantially electrically iso-
`lated word lines atop a semiconductor wafer;
`providing active areas about the word lines to define
`an array of memory cell FETs, the active areas
`being defined by a first active region for electrical
`connection with a memory cell capacitor and a
`second active region for electrical connection with
`a bit line;
`layer of an insulating
`providing a planarized first
`material over the word lines and active areas, the
`planarized layer of insulating material having an
`upper surface which is above the word lines;
`providing first contact openings through the first
`layer of insulating material to second active re-
`gionsz
`providing first conductive material pillars within the
`first contact openings, the first pillars having upper
`surfaces which are elevationally above the word
`lines;
`
`5
`
`l0
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`5,338,700
`
`8
`providing a covering layer of insulating material over
`the planarized first layer of insulating material and
`first pillars;
`providing capacitor contact openings through the
`covering layer to electrically connect with the first
`active regions;
`providing capacitors within the capacitor contact
`openings;
`providing an overlying layer of insulating material
`over the covering layer of insulating material and
`over the capacitors;
`providing bit line contact openings through the over-
`lying layer and the covering layer to the first pillar
`upper surfaces; and
`providing a digit line layer of conductive material
`atop the wafer and within the bit line contact open-
`ings,
`the digit line layer electrically connecting
`with the first pillar upper surfaces.
`2. The method of forming a bit line over capacitor
`array of memory cells of claim 1 wherein the first con-
`ductive material pillars have an upper surface area and
`the bit line contact openings have an open cross section,
`and wherein the step of providing bit line contact open-
`ings
`comprises photopatterning and etching,
`the
`method further comprising:
`fabricating the surface area of individual first conduc-
`tive material pillars to be greater than the open
`cross section of individual bit line contact openings
`to substantially assure complete overlap of the
`individual bit line contact openings relative to the
`individual first conductive material pillar surface
`areas; and
`photopatteming and etching area on the wafer pe-
`ripheral to the memory array in the same step in
`which the bit line contact openings are photopat-
`temed and etched.
`
`3. A method of forming a bit line over capacitor array
`of memory cells comprising:
`providing an array of substantially electrically iso-
`lated word lines atop a semiconductor wafer;
`providing active areas about the word lines to define
`an array of memory cell FETs, the active areas
`being defined by a first active region for electrical
`connection with a memory cell capacitor and a
`second active region for electrical connection with
`a bit line;
`providing a planarized first layer of an insulating
`material over the word lines and active areas, the
`planarized layer of insulating material having an
`upper surface which is above the word lines;
`providing first contact openings through a first layer
`of insulating material to second active regions;
`providing first conductive material pillars within the
`first contact openings, the first pillars having upper
`surfaces which are elevationally above the word
`lines;
`providing a covering layer of insulating material over
`the planarized first layer of insulating material and
`first pillars;
`providing capacitor contact openings through the
`covering layer to electrically connect with the first
`active regions;
`providing a layer of conductive material over the
`covering layer of insulating material and within the
`capacitor contact openings, the layer of conductive
`material having an outer surface;
`removing conductive material from atop the cover-
`ing layer to define isolated cell storage node con-
`
`

`
`9
`tainers electrically connecting with the first active
`regions;
`providing a capacitor cell dielectric layer on the
`wafer atop the isolated storage nodes, insulating
`material of the covering layer being interposed
`between the first pillar upper surfaces and the ca-
`pacitor cell dielectric layer;
`providing a conductive capacitor cell layer atop the
`capacitor cell dielectric layer to define an array of
`memory cell capacitors;
`providing an overlaying layer of insulating material
`over the conductive capacitor cell layer;
`providing bit line contact openings through the over-
`lying layer, conductive capacitor cell layer, cell
`capacitor dielectric layer and covering layer to the
`first pillar upper surfaces, the bit line contact open-
`ings having sidewalls, the bit line contact opening
`sidewalls including exposed edges of the conduc-
`tive capacitor cell layer;
`electrically insulating exposed edges of the conduc-
`tive capacitor cell layer within the bit line contact
`openings; and
`after electrically insulating the exposed edges, pro-
`viding a digit line layer of conductive material atop
`the wafer and within the bit line contact openings,
`the digit line layer electrically connecting with the
`first pillar upper surfaces.
`4. The method of forming a bit line over capacitor
`array of memory cells of claim 3 wherein the covering
`layer is not homogeneous.
`5. The method of forming a bit line over capacitor
`array of memory cells of claim 3 wherein the material of
`' the first conductive pillars and the material of the con-
`ductive layer provided over the covering layer com-
`prises conductively doped polysilicon.
`6. The method of forming a bit line over capacitor
`array of memory cells of claim 3 wherein the material of
`the first conduct