Our Case No. 10200/12
`Client Ref. No. PM95012D
`
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`' correspondence is being
`V
`I hereby
`ited States Postal Service, with
`deposited with
`sufficient postage, as first class mail in an envelope
`addressed to:
`
`
`
`Commissioner for Patents
`Washington, DC. 20231
`on October 1, 2001
`Date of Deposit
`
`Paul E. Rauch, Ph.D. Re . No. 38,591
`
`Name of applicant, assignee or
`
`,Regis%|‘x’eErE e
`
`Signature
`October 1, 2001
`Date of Sig nature
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of:
`
`Nulty et al.
`Serial No. 09/540,610
`__
`Filing Date: March 31, 2000
`
`For
`
`STRUCTURE HAVING REDUCED
`LATERAL SPACER EROSION
`
`\/\a\a‘~z\a\_d\./\z\_/xy
`
`A
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`E
`
`'
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`h
`xammerchnsc C U
`Group Art Unit No. 2815
`
`AMENDMENT AND RESPONSE
`
`Commissioner for Patents
`Washington, D.C. 20231
`
`Dear Sir:
`
`Responsiveto the Office Action mailed June 1, 2001, Applicants respectfully
`
`request reconsideration in light of the following amendments and remarks.
`
`IN THE SPECIFICATION
`
`‘Please insert the following statement in the application on page 1, before line 1:
`
`INTEL 1016
`
`
`
`

`
`;
`-}-This application is a divisional ofmappli atign f§er, N792; 0181531751, now U.S. Pat.
`3...;
`g
`_“ I 7/. A;-\
`No. 6,066,555, filed December 22, 1995.-
`
`
`
`
`Please replace the following paragraphs:
`
`pg. 1, ln. 19-pg. 2, ln. 9
`
`At several stages of the fabrication of semiconductor devices, it is necessary to
`
`make openings in the dielectric to allow for contact to underlying regions or layers.
`
`Generally, an opening through a dielectric exposing a diffusion region or an opening
`
`through a dielectric layer between polysilicon and a first metal layer is called a "contact
`
`fl?
`
`opening", while an opening in other oxide layers such as an opening through an
`
`intermetal dielectric layer is referred to as a “via". For purposes of the claimed
`
`invention, henceforth “contact opening” or "contact region" will be used to refer to .
`
`contact openings and/or via. The opening may expose a device region within the silicon
`substrate, such as a source or drain, or may expose some other layer or structure, for
`
`example, an underlying metallization layer, local interconnect layer, or structure such as
`
`a gate. After the opening has been formed exposing a portion of the region or layer to
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`be contacted, the opening is generally cleaned with a sputter etch, e.g., a Radio-
`
`Frequency (“RF") sputter etch, and then the opening is filled with a conductive material
`
`deposited in the opening and in electrical contact with th gg
`LE, In. 23-pg. 5, ln. 3
`
`.j—-—-—'*—'—‘
`
`The preceding discussion focused on the making of openings, e.g., contact
`
`openings, in dielectric material on a semi-conductor substrate. The same principles are
`
`used in constructing device regions with a dielectric layer or layers. As geometries
`
`63
`
`shrink, the forming of discrete devices on a semiconductor substrate becomes more
`
`specialized. Specialized deposition and etching techniques permit the density of
`
`semiconductor elements on a single chip to greatly increase, which translates into larger
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`memory, faster operating speeds, and reduced production costs.
`
`
`
`

`
`"I
`
`/_...
`
`pg. 6, In. 4-8
`
`~——-"‘
`
`Figure 1 illustrates a self-aligned contact 130 between two gate structures.
`
`élyt
`
`Figure 1(A) is a planar top view of the contact 130. Figure 1(B) is a planar cross-
`sectional view of the self-aligned contact 130 between a pair of gates taken through line
`1(B) of Figure 1(A). Figure 1(C) is a planar cross-sectional view of the self-aligned
`
`contact 130 between a pair of gates taken through line 1(C) of Figure 1(A).
`
`Eé 6, In. 91%
`
`The self-aligned contact 130 is a contact to a source or drain diffusion region (n+
`
`or p+ silicon) 140 that can overlap the edge of the diffusion region 140 without shorting
`
`out to a well beneath the diffusion region 140. This can be seen most illustratively
`through Figure 1(C).
`in Figure 1(C). the contact 130 does not lie directly in the diffusion
`
`region 140, but is misaligned and slightly overlaps the field oxide (designated by FOX. in
`
`Fig. (1C).
`
`in this illustration, the se|f—aligned contact 130 is not directly over the diffusion
`
`region 140 but extends over (i.e., overlaps) a well portion 170. The self-aligned contact
`
`130 does not short to the well portion 170 because the self-aligned contact 130 is
`
`separated from the well 170 by the field oxide.
`‘X
`
`l
`
`pg. 6, |n.‘l8-23
`
`The self-aligned contact 130 is separated from a conducting polysilicon layer 110
`
`by an encapsulating dielectric layer 120 such that the contact 130 can also overlap the
`
`polysilicon layer 110 without making electrical contact to the layer 110 or gate. The
`
`polysilicon layer 110 is separated from the source/drain diffusion region 140 by a
`
`dielectric spacer or shoulder‘150 of the same or different dielectric material as the
`
`dielectric layer 120 directly above the conducting polysilicon layer 110.
`
`LE6 6, In. 24—pg. 7, In. 8
`
`A distinct dielectric etch stop layer 125 overlies the encapsulating dielectric layer
`
`120. The etch stop layer 125 permits subsequent etching of the substrate without risk
`
`of exposing the device structures and layers because the device structuring and layers
`
`

`
`are protected from excessive etching by the etch stop layer 125. The diffusion contact
`
`is self-aligning because the structure can be etched to the substrate over the
`
`46 171/
`
`source/drain diffusion region 140 while the dielectric spacer 150 protects the polysilicon
`layer 110. Even if a photoresist that protects the polysilicon layer 110 from the etchant
`is misaligned with respect to the polysilicon layer 110, the dielectric spacer 150 prevents
`
`shorts to the polysilicon layer 110 when the contact 130 is provided for the diffusion
`
`region 140.
` .,_...._
`
`~.._
`pg. 7, In. 11-22
`
`The current practice with respect to forming contact regions, particularly self-
`
`aligned contact regions, that are in electrical contact with gates, interconnect lines. or
`
`other structures in small feature size structures is to utilize etchants with high selectivity
`
`to protect underlying regions, like the etch stop layer and the first insulating layer.‘
`
`Figure 2 illustrates a typical prior art process of forming a self-aligned contact region
`
`adjacent to a gate.
`
`in Figure 2(A), a gate oxide layer 210 is formed on a substrate 200
`
`/ with a conducting layer, for example a polysilicon layer 220, overlying the gate oxide
`W layer 210, and an insulating layer, for example a TEOS layer 230. overlying the
`polysilicon layer 220. Adjacent to the polysilicon layer 220 is a contact opening region
`
`270. The polysilicon layer 220 is separated from the contact region 270 by an insulating
`
`spacer portion, for example a TEOS spacer portion 235. A separate insulating or- etch
`
`stop layer, for example a silicon nitride layer 240, overlies the TEOS layer 230 and the
`
`contact region 270. A blanket layer, for example a doped insulating layer like a
`
`BPTEOS layer 250, planarly overlies the etch stop layer 240.
`
`,‘/
`
`\;EE;7, In. 23-pg. 3. in.?_]
`
`A layer of photoresist material 280 overlies the planarized BPTEOS layer 250 to
`
`expose the contact opening 270.
`
`In Figure 2(A), a contact opening 270 has been
`
`opened through the BPTEOS layer 250. The etchant utilized to make the opening had
`
`a high selectivity toward BPTEOS relative to silicon nitride. When the contact opening
`
`270 was formed through the BPTEOS material, the etchant did not etch or did not
`
`effectively etch the silicon nitride layer 240 material. Hence, the description of the
`
`

`
`/ silicon nitride layer 240 is described as an etch stop layer. The silicon nitride etch stop
`59 layer 240 protected the underlying TEOS layer 230 and spacer portion 235 so that the
`
`polysilicon layer 220 completely encapsulated.
`&_.-
`f’
`ll
`' pg. 8, in. 6-13
`
`'7
`
`Figure 2(A) illustrates an etch 260 to remove the silicon nitride etch stop layer
`
`240.
`
`In the etch 260 illustrated .in Figure 2(A), a high selectivity etch toward silicon
`
`/50)
`
`nitride relative to the underlying TEOS layer 230 material is practiced to efficiently etch
`the silicon nitride layer 240 and to protect the underlying TEOS layer 230 from the
`etchant. An example of a high selectivity etch recipe to effectively strip silicon nitride as
`
`compared to the TEOS layer is 30 sccm CHF3 and 30 sccm 02 at 60 mtorr and 100
`
`watts of power. The result of the high selectivity etch is illustrated in Figure 2(B).
`"_’:}?A$——
`
`pg. 8, ln. 14—|n. 23
`
`Figure 2(B) shows that the silicon nitride selective etch effectively removed
`
`silicon nitride layer 240 from the Contact opening 270. The selective etch for silicon
`
`nitride compared to TEOS material, however, left the TEOS layer 230 with a spacer
`
`portion 235 wherein the spacer portion 235 is sloping or tapered toward the contact
`
`opening 270. This result follows even where the spacer portion 235 is originally
`
`substantially rectangular as in Figure 2(A). The properties of the highly selective etch of
`
`the overlying etch stop layer 240 will transform a substantially rectangular spacer into a
`
`sloped spacer. Figure 2(B) presents a polysilicon layer 220 encapsulated in a TEOS
`
`layer 230 with a spacer portion 235 adjacent to the Contact opening 270, the spacer
`
`portion 235 having an angle 290 that is less than 85°.
`..—d‘''
`
`E3, in. 24-pg. 9, In.‘ 10
`
`In addition to providing stopping points or selectivity between materials, the use
`
`of high selectivity etches to form sloped spacer portions is the preferred practice
`
`because the sloped shape will result in good step coverage by the metal that is
`
`deposited into it. The filling of contact openings or gaps (i.e., gap fill) is an important
`
`consideration because it relates directly to the reliability of a device.
`
`If an opening is not
`
`
`
`

`
`completely filled with an insulative material, for example, and a gap is created, a
`
`subsequent conductive material deposit can fill the gap which can lead to shorting.
`
`Sloped contact openings are easier to completely fill than boxy structures because the
`
`transition between sloped structures and openings is smooth compared to the abrupt
`
`transitions between boxy structures and openings. Because of concerns for complete
`
`gap fill and good step coverage, industry preference is for sloped spacers and planar
`
`deposition layers similar to that shown in Figure 2(B).
`_;i___*
`
`pg. 9, in. 11-26
`3,/'-
`Once the contact opening is made, the opening is cleaned with a sputter etch,
`
`e.g., an RF sputter etch.'before conductive material is added to fill the opening or gap.
`
`The RF sputter etch that is used to clean the contact opening in the process described
`
`above will attack and erode a portion of the insulating spacer surrounding the
`
`conducting portion and adjacent to the contact region. Figure 3 illustrates a prior art
`67 substrate with a gate and a contact region undergoing an RF sputter etch 380.
`in
`Figure 3, a gate oxide 310 is formed on a substrate 300 with a polysiiicon layer 320
`
`overlying the gate oxide 310 and an insulating layer, for example a.TEOS layer 330
`
`overlying the polysilicon layer 320. A distinct insulating layer, for example a silicon
`
`nitride etch stop layer 340, overlies the TEOS layer 330 and this etch stop layer 340 is
`
`covered by a‘ third insulating layer, for example a BPTEOS blanket layer 350. Adjacent
`
`to the gate is a contact region 360. An etch of the silicon nitride etch stop layer 340 with
`
`a high selectivity etch for silicon nitride relative to the underlying TEOS layer material
`
`produced a gate with a sloping or tapered spacer portion 370 of TEOS material,
`
`illustrated in ghost lines. A subsequent RF sputter etch 380 is utilized to clean the
`
`contact region 360.
`
`LE10, In. 1—T(g’_j
`
`Although brief and designed to clean the contact region. the RF sputter etch 380
`
`will erode a portion of the insulating TEOS spacer portion 370. The dynamics of the
`
`sputter etch 380 are that it proceeds vertically, directing high-energy particles at the
`
`contact region. The sloping or tapered spacer portion 370 adjacent the polysilicon layer
`
`
`
`

`
`V /_
`
`N
`
`320 and separating the polysilicon layer 320 from the contact region 360 is struck by the
`
`high-energy particles of the RF sputter etch 380. Because the spacer portion 370 is
`
`sloping or diagonal, a significant surface area portion of the spacer portion 370 is
`
`directly exposed to the high-energy particles from the RF sputter etch 380. Further, with
`
`sloping spacers, or spacers having an angle relative to the substrate surface of less
`
`than 85° the vertical portion of the dielectric layer (i.e., that portion above the polysilicon
`
`layer 320) decreases much less than the diagonal portion of the spacer.
`
`in terms of
`
`measuring TEOS material removal during the RF sputter etch 380 in Figure 3, the
`
`difference between d1 and d2 is greater than the difference between v1 and 92. Thus, in
`
`conventional prior art self aligned contact structures, the diagonal thickness of the
`
`TEOS spacer portion 370, rather than the vertical thickness of the TEOS layer 330,
`
`determines the minimum insulating layer thickness for the gate.
`
`pg. 10, In. 17-pg. 11, ms
`
`For gate structures having minimum diagonal insulative spacer portions of 500 A
`
`or less, the result of the sputter etch 380 is that the sputter etch 380 laterally erodes the
`
`diagonal portion of the TEOS spacer portion 370 adjacent to the contact region to a
`
`point where the polysilicon layer 320 is no longer isolated from the contact region 360
`
`by an insulating layer.
`
`in that case, there is a short circuit through the underlying
`
`conductive material when the contact region 360 is filled with conductive material. This
`
`result follows because the conventional RF sputter etch 380 utilized for cleaning the
`
`contact region 360 results in an approximately 200-500 A loss of the spacer material.
`
`Further, process margins generally require that the device spacer have a final minimum
`
`thickness (after all etches, doping, and deposits) of at least 500 A. Thus, eliminating
`
`alignment sensitivity for conventional small feature size structures, including self-aligned
`
`contact structures, requires a final (i.e., at the time of contact deposition) minimum
`
`insulating spacer of more than 500 A and preferably on the order of 1000-1500 A or
`
`greater to fulfill requirements for an adequate process margin, complete gap fill, and
`
`device reliability.
`
`
`
`

`
`pg. 11. In. 6-pg. 12, in. 2
`
`To construct structures having a minimum insulative spacer portion of more than
`
`500 A directly effects the number of structures that can be placed on a device, such as
`
`a chip. The construction of structures having a minimum insulative spacer portion of
`
`more than 500 A requires that the pre-etch-stop-etch spacer be bigger or thicker to" yield
`
`an effective spacer after the etching processes.
`
`In such cases, the structures must be
`
`separated a distance such that the contact area opening is sufficient enough for an
`effective contact. This spacing requirement directly limits the number of structures that
`
`,
`77!‘
`
`can be included on a device.
`In small feature size structures, particularly structures
`utilizing self-aligned contacts. the width of contact openings is approximately 0.6
`microns at the top of the planarized layer and 0.2 microns at the base of the contact
`
`opening. Figure 3 indicates the difference in contact opening widths for the same
`
`Contact in prior art structures. W1 represents the width at the top of the planarized layer
`
`and W2 represents the width at the base of the contact region 360. Further, an aspect
`
`ratio can be defined as the height of a structure (field oxide plus conductive layer plus
`
`first insulative layer plus etch stop layer, if any) relative to the width of the base of a
`
`contact opening (i.e., the distance between adjacent spacers). Typical aspect ratios for
`
`self-aligned contact structures target ratios of 1.0-2.4. This prior art range is not
`
`achievable with any device reliability. To achieve aspect ratios of 1.0-2.4 requires
`
`minimum spacer portions of less than 1000 A and preferably on the order of 500 A. As
`
`noted above, the minimum spacer portions required for aspect ratios of 1.0-2.4 cannot
`
`withstand the sputter etch and will result in the exposure of the underlying polysilicon
`
`gate and short circuiting with the contact.
`
`_____,I
`
`—
`L’. pg. 13. In. 2-19
`
` _
`
`. T
`
`he invention relates to a process for minimizing lateral spacer erosion of an
`
`insulating layer on an enclosed contact region, and a device including a contact opening
`with a small alignment tolerance relative to a gate electrode or other structure. The
`
`E)?
`
`process provides high quality contacts between a conductive material in the contact
`
`region and a device region, such as a source or drain, or some other layer or structure.
`
`
`
`

`
`The process comprises the well known step of forming a conductive layer on the
`
`semiconductor body adjacent a contact region. This is followed by the forming of a first
`
`insulating layer adjacent said conductive layer andthe contact region. A selected area
`
`is masked with photoresist and the first insulating layer and the conductive layer are
`
`etched to form a device structure, such as a gate, adjacent the contact region. Next,
`
`'5
`
`8 insulating lateral spacers are added to the device structure to isolate the conductive
`portion of the device. The insulating spacers are etched so that the device comprises
`an insulating layer overlying a conductive layer with a lateral spacer portion adjacent the
`
`contact region wherein the spacer portion has a substantially rectangular profile. A
`
`distinct insulating layer or etch stop layer is then formed adjacent to the first insulating
`
`layer and over the contact region. A third insulating layer or blanket layer is then
`
`optionally formed over the etch stop layer. The blanket layer may or may not be i
`
`\ planarized.
`
`
`2
`
`pg. 16, In. 5-9
`Figure 1
`
`illustrates a self-aligned contact to a diffusion region. Figure 1(A) is a
`
`planar top view of the self-aligned contact. Figure 1(B) is a cross-sectional planar side
`
`view of the self-aligned contact taken through line 1(B) of Figure 1(A). Figure 1(C) is a
`
`cross-sectional planar side view of the self-aligned contact taken through line 1(C) of
`
`Figure 1(A).
`
`‘M
`
`16,in.1oZ2:l
`
`Figure 2 is a cross-sectional side view illustrating the formation of a prior art
`
`contact opening. Figure 2(A-) illustrates a high selectivity etch of an etch stop insulating
`
`layer, and Figure 2(B) illustrates the results of that etch.
`
`.
`
`,,—-
`
` 16,|n.13-14
`
`Figure 3 is a cross-sectional side view of a prior art contact opening formation
`
`during a sputter cleaning etch.
`
`i./4'2
`
`

`
`p/g‘17, In. 9-11 l
`
`Figure 4(E) illustrates a cross-sectional planar side view of a series of gates
`
`gm encapsulated with insulating material, wherein the diffusion regions are implanted with,
`for example, a silicide.
`
`“
`
`Eg.17,|n. 12-15
`
`I
`
`Figure 4(F) illustrates a cross-sectional planar side view of a series of gates
`
`encapsulated with insulating material and an insulating etch stop layer overlying the
`
`insulating material.
` /7:?"
`‘(.4
`
`pg. 17, In. 23-pg. 18, in. 2
`
`Figure 4(|) illustrates a cross-sectional planar side view of a series of gates-
`
`encapsulated with insulating material, an etch stop layer overlying the insulating
`
`material, a distinct planarized insulating blanket layer overlying the etch stop layer, and
`contact openings etched through the blanket layer above the diffusion regions, but
`separated from the diffusion regions by the etch stop layer.
`/5-7"‘
`
`,5“
`
`LE; 18, in.
`
`Figure 4(J) illustrates a cross-sectional planar side view of a series of gates
`
`encapsulated with insulating material, an etch stop layer overlying the insulating
`
`material, a distinct planarized insulating blanket layer overlying the etch stop layer, and
`
`contact openings to the diffusion regions.
`
`
`1,"
`pg. 19. In. 2-15
`
`The invention is a device and a process whereby there is provided a contact
`
`opening with no alignment sensitivity relative to a gate electrode or other structure such
`
`/ta
`
`é
`
`that the gate electrode does not fall within the contact opening but remains isolated from
`the contact opening by an insulating layer. The structure contemplated by the invention
`is an effective device for small feature size structures, particularly self-aligned contacts,
`
`10
`
`Q‘
`
`

`
`because it is capable of maintaining high quality contacts between the conductive
`
`material in the contact region and the underlying device region, such as a source or
`
`drain, or some other layer or structure with minimum contact opening base widths (i.e.,
`
`fit}
`
`at the base of the contact openings) of 0.2 microns and minimum contact opening
`
`widths of 0.5 microns when measured from the top of a pianarized layer, minimum
`
`encapsulating layer thicknesses of 400 A. and aspect ratios (i.e., height of structure
`
`including the etch stop layer relative to the width of the base of a contact opening
`
`between the spacers) in the range of 1.0-2.4.
`
`z-as-—'=
`
`/‘pg. 20. In. 5-18
`
`Figure 4 presents a cross-sectional view of the preparation of a series of gates or
`
`transistors on a semiconductor substrate surface. Referring to Figure 4(A), the
`semiconductor substrate 400 can be either p-for n-type, and includes diffusion regions
`
`405, such as sources or drains, that are heavily doped with the opposite dopant type of
`
`the substrate. An n-type first conducting layer 415 of polysilicon doped by implantation
`
`with phosphorous to a resistivity of 50-200 ohms/square is deposited over the diffusion
`
`regions 405. The polysilicon layer 415 is deposited by low pressure CVD (“LPCVD”)
`
`using an LPCVD tube and SiH4 gas at 200-400 mtorr with a thickness of 2000-3000 A.
`
`it should be appreciated by those skilled in the art that this conducting layer 415 could
`
`instead be a p-type conducting layer or a metallic conductor of, for example, W, Mo, Ta,
`
`and/or Ti, or that this conducting layer 415 could also be a silicide, consisting of WSi2,
`
`MoSi2, TaSi2, PtSi, PdSi. or that this conducting layer 415 can further be a layered
`
`structure consisting of a silicide on top of doped polysilicon.
`
`‘
`
`‘
`
`(pg. 20, in. 19-pg. 21, in. 2'
`
`The polysilicon layer 415 overlays an insulating dielectric layer 410 such as
`doped or undoped silicon dioxide. The dielectric layer 410 may comprise a single oxide,
`
`or several layers formed by various methods. For example, one or more layers of oxide
`
`may be deposited by plasma enhanced chemical vapor deposition (“PECVD"), thermal
`
`CVD (“TCVD”), atmospheric pressure CVD (“APCVD"), subatmospheric pressure CVD
`
`11
`
`

`
`(“SACVD"). utilizing, for example, TEOS and oxygen. or TEOS and ozone chemistries.
`
`g/3
`
`As used herein, reference to, for example, a PECVD TEOS oxide denotes an oxide
`layer deposited by PECVD utilizing TEOS chemistry. Additionally, one or more layers of
`
`dielectric layer 410 may be a spin-on-glass ("SOG") layer.
`
`
`Referring further to Figure 4(A), a photoresist masking layer 425 is deposited
`
`over the TEOS dielectric layer 420. The photoresist masking layer 425 is patterned to
`
`enable exposure of diffusion regions 405 in the semiconductor substrate. Referring to
`
`Figure 4(B), a series of photolithographic etches are performed to remove the TEOS
`
`layer 420 material and the polysilicon layer 415 from the diffusion regions 405 to form
`
`contact openings. The etches are performed using a parallel plate plasma etcher with a
`
`power of 200-300 watts. First, a fluorocarbon photolithographic etch, CH F3/C2F6 at 50
`
`mtorr. is performed to remove the insulating TEOS material from areas adjacent to and
`
`including the diffusion regions 405. This is followed by a single polysilicon
`
`photolithographic etch using a chlorine plasma (Cl2/He) to define a polysilicon
`
`conducting layer 415 above the transistor or gate regions.
` (,m_
`i‘
`pg. 22, in. 5-20
`
`Referring to Figures 4(C) and 4(D), spacers are formed between the polysilicon
`
`layer415 of the gates and the contact openings by depositing an additional of conformal
`
`layer of TEOS material 430 over the structure and etching spacer portions extending
`
`into the contact openings and adjacent to the polysilicon layer 415 approximately
`1500 A in width. The spacer. portions 435 of the TEOS layer 430 are demarked by
`
`bl)
`
`ghost lines in Figure 4(D). The spacers 435 serve to insulate the polysilicon layers 415
`
`from the conducting material that will fill the contact openings and prevent the gates
`
`from overlapping the diffusion regions 405. The spacers 435 serve to completely
`
`encapsulate the polysilicon layers 415 of the individual gates. As shown in Figure 4(C),
`
`care is taken to etch the spacers 435 such that the spacers 435 have a substantially
`
`rectangular profile. This is accomplished using a low bias and high pressure etch (2.8
`
`
`
`

`
`
`
`torr, 140 sccm He, 30 sccm CHF3, 90 sccm CF... and 850 watts power), that results in
`
`low polymer formation. At this point, the preferred embodiment of the invention
`
`contemplates that the TEOS layer can have a minimum vertical width of approximately
`
`3000 A and spacers with a minimum width of approximately 1000 A.
`
`W5 . 22,ln.21‘-E
`
`Referring to Figure 4(E), the diffusion regions 405 are next implanted with a
`
`suitable dopant utilizing conventional techniques. The dopant may be implants of
`
`arsenic, phosphorous, or boron. Subsequently, silicides, for example WSi2 and TiSi2,
`
`may also be formed. Figure 4(E) illustrates silicide formation 445 in the diffusion
`
`regions 405.
`
`L59. 23. in. 1-32}
`Referring to Figure 4(F), overlying the TEOS layer 420 is deposited a second
`
`distinct dielectric or etch stop layer 440, in this example, a silicon nitride (Si,.N,.) layer
`
`440, with a total thickness of 700 angstroms.
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`it should again be appreciated by those of
`
`ordinary skill in the art that this silicon nitride layer 440 could instead be an insulating
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`layer of, for example, silicon dioxide, SiO2, ONO, or SiOxN,,(Hz). Additionally, the silicon
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`nitride etch stop layer 440 may be undoped or may be doped, for example with boron,
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`phosphorous, or both, to form, for example, borophosphosilicate glass (“BPSG").
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`.4
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`phosphosilicated glass ("PSG"), and borophosphosilicate tetraethyl orthosilicate
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`~(“BPTEOS"). Further, the etch stop layer 440 may comprise a single silicon nitride layer
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`or several layers formed by various methods.
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`It is important that the etch stop layer 440
`
`be different or distinct from the underlying insulating layer.
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`£39. 23, in. 13-18!
`The invention contemplates that at this point the structure has an aspect ratio of
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`1.0-2.4. As used herein, an aspect ratio is defined as the ratio of the height of a contact
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`opening measured to the top of the horizontal portion of the etch stop layer 440 to the
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`base width of the contact opening between the insulating spacers 435. For example, an
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`13
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`

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`embodiment of the invention contemplates contact opening heights of 5300 A (0.53 pm)
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`relative to widths of 0.32 pm to give aspect ratios of 1.6.
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`j E 23, In. 19-pg. 24. In. 2
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`Referring to Figure 4(G), an optional dielectric blanket layer 450 is next deposited
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`adjacent to the etch stop layer 440. The blanket layer 450 may or may not be
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`In Figure 4(G), the blanket layer 450 is planarized. The planarized blanket
`6 planarized.
`layer 450 facilitates the formation of an interconnect layer that might later be deposited
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`overthe contact regions. The blanket layer 450 in Figure 4(G) is a doped silicate glass,
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`for example BPTEOS.
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`It should be appreciated by those of ordinary skill in the art that
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`this BPTEOS layer 450 could instead be another doped insulating layer of, for example,
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`BPSG or PSG. or an undoped insulating layer of silicon dioxide. SiOz. ONO. or Si0xNy.
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`Further, the blanket layer 450 may comprise a single oxide. like BPTEOS, or several
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`layers formed by various methods.
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`
`
`@424, in. 33
`Next, as shown in Figure 4(H), a photoresist pattern or mask layer 455 is
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`deposited adjacent to the blanket layer 450 such that the diffusion regions 405 can be
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`exposed. This is followed by a photolithographic etch of the BPTEOS blanket layer 450
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`in the contact openings. The etch is a fluorocarbon photolithographic etch (7 sccm
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`CHF3, 6 sccm Freon 134a) at 29 mtor_r. The etch reveals a pair of contact openings 460
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`and 465 above the diffusion regions 405. as shown in Figure 4(l).
`
`]E_24,...9r,5j
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`Referring to Figure 4(J), a photoresist material (not shown) is overlayed in
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`contact opening 465 adjacent to the etch stop layer 440 to protect the etch stop material
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`in contact opening 465 from a subsequent photolithographic etch to remove the etch
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`stop layer 440. Next, a photolithographic etch, (900 mtorr, 100 sccm. He, 85 sccm
`CZF5, and 225 watts power using a Lam 4400 Series plasma etching system) is
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`
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`

`
`performed to remove the etch stop layer 440 from contact opening 460. The etch
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`conditions for this etch are low bombardment/high neutral flux conditions.
`
`[Eng 24, In. 16-24
`fly
`460 in Figure 4(J). The etch proceeds anisotropicaily, primarily removing etch stop
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`Figure 4(K) is a close-up view of the cross—sectional portion of contact opening
`
`material lying in a horizontal plane relative to the vertical direction of the etchant ions.
`
`The etchant removes material primarily from the base of the contact opening 460, and
`
`does not remove all of the etch stop material adjacent to the spacer portion 435 of the
`
`TEOS layer 420. Thus, the remaining etch stop material adjacent to the spacer portion
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`435 of the TEOS layer 420 serves as additional spacer material to insulate the
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`polysilicon layer 415 from a conductive contact that will subsequently be added to the
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`contact opening 460.
`
`
`L99. 25, in. 1-9
`
`The etchant utilized to remove silicon nitride from the contact opening 460 has a
`
`low seiectivity for etching the silicon nitride material compared to the underlying TEOS
`
`layer 420. The use of an etchant with a low selectivity for silicon nitride relative to
`él 9 TEOS does not significantly destroy the TEOS layer spacer portion 435. The low
`selectivity etch yields a TEOS layer spacer portion 435 that retains a rectangular or
`
`“boxy" profile. Figure 4(K) illustrates that only a small portion 475 (illustrated in ghost
`
`lines) of the TEOS layer spacer portion 435 is removed during the etch. Of primary
`
`significance, the spacer portion 435 of the TEOS layer 420 retains its substantially
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`rectangular profile.
`
`LE25, in 10-15
`
`It is to be appreciated that the described etch stop layer etch conditions (i.e., low
`
`selectivity, low bombardment/high neutral flux) are exemplary of etch conditions that
`
`result in the retention of a boxy spacer. The invention relates to these process
`
`15
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`
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`

`
`conditions as well as others that result in the retention of a boxy spacer. Thus, the etch-
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`stop etch conditions should be regarded in an illustrative rather than restrictive sense.
`
`lpg. 25, In. 16-pg. 26, In. 2
`
`The silicon nitride etch stop layer etch is followed by a sputter etch to clean the
`
`contact opening 460.
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`In a currently preferred embodiment, the sputter etch is carried
`
`6] 0
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`out in an atmosphere of argon, a 8 mtorr pressure, with a 1000 volt bias.
`In a currently
`preferred embodiment, the sputter etch is carried out in a commercially available system
`such as the Applied Materials Endura 5500 systems. Alternatively, any system having a
`
`sputter etch mode may be used to practice the invention. As will be appreciated by a
`person of ordinary skill in the art, the parameters can be varied considerably while still
`
`achieving the objects of the invention.
`
`In a currently preferred embodiment, the etch is
`
`designed to etch approximately 200 A per minute as measured on thermal oxide.
`
`‘
`
`Because of the retention of a substantially rectangular or “boxy" spacer portion 435, the
`
`sputter etch does not significantly erode the spacer portion 435 of the TEOS layer 420.
`
`
`pg. 26, In. 8-10
`
`_
`
`Figure 4(L) presents a cross-sectional planar side view of the structure of the
`
`invention wherein conductive contacts 480 have been deposited in the contact openings
`460.
`
`fl/7
`E. 26, In. 1:?)
`
`The process described above yields a structure wherein first and second
`
`conductive layers (e.g., polysilicon layers) are separated by a contact opening with an
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`area defined in the semiconductor substrate. An insulating layer is adjacent to and
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`encapsulates the first and second conductive layers. The invention contemplates that
`
`the insulating layer has spacer portions between the conductive layers and the contact
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`opening. The invention contemplates that high quality contacts can be achieved
`
`wherein the spacer portions have a minimum insulative material thickness of 400 A.
`
`In
`
`' the preferred embodiment, the spacer portions of the i