United States Patent [191
`Black et al.
`
`[11]
`[45]
`
`4,426,768
`Jan. 24, 1984
`
`[54] ULTRA-THIN MICROELECI‘RONIC
`PRESSURE SENSORS
`[75] Inventors: James F. Black, Newington; Thomas
`W. Grudkowski, Glastonbury;
`Anthony J. DeMaria, West Hartford,
`‘ all of Conn.
`United Technologies Corporation,
`Hartford, Conn.
`[21] Appl. No.: 334,759
`[22] Filed:
`Dec. 28, 1981
`
`[73] Assignee:
`
`[51] Int. Cl.3 .................... .. H01L 21/20; HOlL 21/22
`[52] US. Cl. ...................................... .. 29/583; 29/580;
`29/578; 357/26; 338/4
`7 [58] Field of Search ....................... .. 338/2, 4; 357/26;
`29/610 SG, 589, 578, 583, 376 J, 580
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,103,273 7/1978 Keller
`4,121,334 10/1978 Wallis
`Primary Examiner-Brian E. Hearn
`Assistant Examiner—David A. Hey
`
`.................. .. 338/2
`................... .. 29/589
`
`Attorney, Agent, or Firm——M. P. Williams
`[57]
`ABSTRACT
`A plurality of thin pressure sensors are made by pro
`cessing a ?rst large wafer (20, 110) to provide a plurality
`of electronic devices (28, 122, 124, 125) having a char
`acteristic which varies inversely with strain, and pro
`cessing a second wafer (40) to provide a plurality of
`cavities (46) each registered on the second wafer so as
`to be registerable with a corresponding device on the
`?rst wafer. The wafers (20, 40, 110) have thick undoped
`silicon substrates (21, 41, 114) which are utilized as
`handles or carriers during the processing, and are
`stripped off by etching to a highly doped boron etch
`stop layer (22, 42, 112) when the processing has pro
`ceeded to a point where the need therefore has been
`satis?ed. The ?rst wafers (20, 110) are provided with a
`suitable pattern of borosilicate glass (except in the re
`gion where the pressure sensors are formed) so that the
`two wafers may be joined by a ?eld assisted bonding at
`a suitable temperature in a vacuum. Electric contact to
`the devices is provided by holes (51, FIG. 9; 56-59,
`FIG. 13) through the entire wafer.
`
`2 Claims, 13 Drawing Figures
`
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`US. Patent Jan. 24, 1984
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`reproducible fashion on a mass production basis at low
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`cost. .
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`Other objects, features and advantages of the present
`invention will become more apparent from the follow
`ing detailed description of exemplary embodiments
`thereof, as illustrated in the accompanying drawings.
`BRIEF DESCRIPTION OF DRAWINGS
`FIG. 1 is a partial, sectioned, side elevation view, of
`a wafer being processed to provide electronic devices in
`accordance with a ?rst embodiment of the invention;
`FIG. 2 is a partial, sectioned, side elevation view, of
`a wafer being processed to provide electronic devices in
`accordance with the invention, taken on the line 2—2 of
`FIG. 10;
`FIGS’. 3-6 are partial, sectioned, side elevation views
`illustrating further processing of the wafer shown in
`FIGS. 1 and 2;
`.
`FIG. 7 is a partial, sectioned, side elevation view of a
`second wafer being processed in accordance with the
`present invention;
`FIGS. 8 and 9 are partial, sectioned, side elevation
`views of combining the wafers processed in accordance
`with FIGS. 1-7;
`FIG. 10 is a simpli?ed plan view of a portion of a
`wafer illustrating the topography of processing shown
`in FIG. 2;
`.
`.FIG. 11 is a partial plan view of a wafer being pro
`cessed to provide a device in accordance with a second
`embodiment of the invention;
`_
`FIG. 12 is a partial, sectioned, side elevation view of
`the processing illustrated in FIG. 11; and
`FIG. 13 is a partial, sectioned, side elevation view of
`combining the wafer of FIGS. 11 and 12 with the wafer
`of FIG. 7.
`
`ULTRA-THIN MICROELECI‘RONIC ‘PRESSURE
`SENSORS
`
`DESCRIPTION
`1. Technical Field
`This invention relates to pressure sensors, and more
`particularly to processes for manufacturing ultra-thin
`microelectronic pressure'sensors.
`2. Background Art
`There is an increasing need for reliable, electronic
`pressure sensors which can be utilized in adverse envi
`ronments, and which can be used in a manner that does
`not upset the environmental conditions, the pressure of
`which is to be measured. Recent advances in the pres
`sure sensor art have provided pressure sensors employ
`ing surface acoustic waves, piezoelectric bridges, and
`bulk acoustic waves. Microelectronic processing tech
`niques (of the sort utilized to provide large scale inte
`grated electronic circuits) have been employed to make
`such pressure sensors, as well as to make capacitive
`pressure sensors of a very small type. However, it is
`desirable to provide such pressure sensors in a wide
`variety of types to suit a large number of applications,
`and therefore it is desirable to fabricate pressure sensors
`employing electronic devices sensitive to strain in a
`fashion which protect the devices, are capable of being
`mass produced in a reliable, reproducible fashion at
`relatively low cost, and which can withstand adverse
`environments. Heretofore, one difficulty with small,
`microelectronic pressure sensors is that the overall di
`mensions thereof have impeded the ?ow of gases (such
`as in a jet engine) or have been unable to withstand
`adverse environments.
`
`25
`
`30
`
`35
`
`DISCLOSURE OF INVENTION
`Objects of the invention include provision of elec
`tronic pressure sensors which are ultra-thin, in which
`the electronic devices are inherently protected, and
`40
`which are reproducibly mass producible at relatively
`low cost.
`According to the invention, a ?rst wafer including a
`thick undoped silicon carrier substrate and an additional
`doped silicon layer is processed to provide a plurality of 45
`electronic devices sensitive to strain, and is provided
`with a suitable coating of borosilicate glass. The ?rst
`wafer is then joined by ?eld assisted bonding to a sec
`ond wafer having a thick, undoped silicon carrier sub
`strate, in which a plurality of cavities have been formed,
`to provide a composite wafer having a plurality of pres
`sure sensors, each including a device at a cavity. The
`wafer is diced to provide individual pressure sensors.
`The thick, undoped silicon carrier substrates are
`stripped off at appropriate stages of the process where
`they are no longer needed. According further to the
`invention, each of the wafers employs a highly doped
`silicon etch stop layer that facilitates stripping off the
`undoped silicon substrate. In still further accord with
`the invention, contact to the electronic devices made at
`a ?rst surface of one of the wafers is achieved by etch
`ing through the entire wafer from the opposite surface
`thereof, thereby permitting the devices to be in that
`surface of the wafer which is joined to the cavity-de?n
`ing wafer, thereby to protect the devices.
`The invention therefore provides ultra-thin micro~
`electronic pressure sensors, such sensors which have
`protected devices, and which can be manufactured in a
`
`50
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`55
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`60
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`65
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`BEST MODE FOR CARRYING OUT THE
`INVENTION
`Referring now to FIG. 10, a pair of wafers are pro
`cessed to provide a plurality of piezo-resistive bridges
`15 on thin diaphragms or membranes 16 so as to form a
`plurality of ultra-thin microelectronic pressure sensors,
`17-19. It should be noted that all of the illustrations
`herein are not to scale, and are distorted to permit illus
`tration of the various items and features. In FIG. 1, the
`starting wafer 20 is a buried layer epitaxial wafer includ
`ing a lightly‘doped, highly resistive silicon substrate 21,
`having a total impurity concentration less than
`1016/cm3. The substrate 21 may be on the order of 300
`microns (300x l0-6cm) thick, and serves as a handle or
`carrier during the process, but is ultimately stripped off
`as is described hereinafter. The wafer 20 has a buried
`epitaxial layer 22 of about 3 microns thickness doped for
`p+ conductivity by means of a boron concentration on
`the order of l020/cm3. On the wafer 20, the upper expi
`taxial layer 23 is about 5 microns thick and is n- type,
`such as may be provided with a l016/cm3 concentration
`of phosphorus. Buried layer epitaxial wafers of this
`general type are commonly used for solar cells, the
`buried layer providing high conductivity.
`The wafer 20 is oxidized in steam so as to provide
`silicon dioxide layers 24, 25 about 0.7 microns thick, on
`both surfaces thereof, which are relatively free of pin
`holes. Then, using standard photoresist and etch tech
`niques, windows 26, 27 are opened in the oxide layer 24
`to permit the diffusion of a resistor array 28 and bonding
`pads 29 (FIG. 2), respectively, to a depth of about 2
`microns, by doping with boron to achieve a p— conduc- '
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`interstices between the various units being fabricated on
`tivity on the order of 100 ohms per square. Each resistor
`the wafer, as well as over the areas of the bonding pads
`array 28 forms a square bridge 15 (FIG. 10), with each
`29, 32 of each device. A lift-off process is used in which
`arm parallel to one of the two orthogonal 110 orienta
`another thick coating of photo-resist 35 (FIG 4) is ap—
`tions of the silicon, each arm being about 0.5mm long
`plied in the area above the resistors 28, and extending
`and including 25-100 orthogonal legs of about 30 mi
`slightly over the PSG layer 34. Then a layer of alumi
`crons in length, formed by a diffusion line width of 5
`microns (only 3 legs are shown in FIGS. .2-10). The
`num 36 of about 0.5 micron thickness is evaporated over
`the entire wafer. Using a scrub etch, lift-off of the alumi
`bonding pads 29 may each be about 250 microns diame
`ter. During the etching of the layer 24, photoresist
`num above the photoresist 35 is achieved. This leaves
`the wafer as illustrated in FIG. 5, comprising the resis
`should be utilized to protect the layer 25.
`Before removing the diffusion mask registration from
`tor arrays 28 and diffused bonding pads 29 with alumi
`num bonding pads 32 deposited therein, the entire wafer
`the wafer, the wafer is provided with edge ?ats or saw
`having a layer of phosphosilicate glass 34 and additional
`cuts to permit subsequent mask alignment and align
`aluminum 36 thereover, except over the resistor arrays
`ment with the second wafer, as described hereinafter.
`Then, remaining oxide layer 24 (FIG. 1) is stripped
`28, which have only the thin silicon dioxide layer 30
`thereover.
`while taking care to protect the oxide layer 25, and a
`The ?nal steps in preparing the ?rst wafer are to
`new, thin layer 30 of silicon dioxide is deposited across
`provide borosilicate glass all over the wafer, except
`the entire upper surface of the wafer, such as by steam
`oxidation or chemical vapor deposition. This layer may
`over the resistor arrays 28. For that reason, another
`layer of photoresist 37 (FIG. 6) is selectively deposited
`be on the order of 0.2 microns thick and is permanently
`retained for protection of the resistors and the P/N
`over the area of the wafer which is to be the pressure
`sensitive membrane or diaphragm 16 (FIG. 10), extend
`junctions. Then, windows 31 (FIG. 2) are etched into
`ing slightly over the phosphosilicate glass layer 34.
`the layer 30 (the oxide layer 25, FIG. 1, being protected
`Then, 4 or 5 microns of a suitable borosilicate glass,
`with photoresist), as a ?rst step toward providing metal
`bonding pads 32 (FIG. 3). The windows 31 should be
`such as Coming 7070 or 7740 (Pyrex), is deposited in a
`layer 38; this will allow ?eld assisted bonding of the ?rst
`smaller than the bonding pads 29 by about 25 microns in
`each direction. Then, plasma etching is utilized to pro
`wafer 20 with a second wafer so as to form a composite
`vide a 0.5 micron deep well in each of the bonding pads.
`microelectronic pressure sensor in accordance with the
`The photoresist used during the oxide etch process may
`invention, as described hereinafter. After the borosili
`cate glass layer 38 is deposited, a scrubbing etch is used
`be retained during the plasma etching and may remain
`30
`to lift off that portion of it which is above the photore
`in place while about 0.2 to 0.5 microns of aluminum is
`sist layer 37. If dif?culty is encountered in the lift-off of
`evaporated into the wells; or the photoresist may be
`the unwanted borosilicate glass 38, the borosilicate glass
`repetitively stripped off and reapplied with the same
`may be deposited in several thin layers with a scrub etch
`mask. The etching of the wells and depositing of alumi
`between each deposition, or a suitable selective etching
`num is to provide metallic bonding surface having very
`low resistance conductivity to the p" bonding pads 29.
`process may be used, provided that care is taken not to
`etch through the silicon dioxide layer 30 above the
`After removing the photoresist used in the process pro
`resistor arrays 28. After the lift-off, leaving the borosili
`viding the aluminum pads 32, the wafer may be heat
`cate glass all over the wafer except above the resistor
`treated, at about 500° C. to 520° C., for a few minutes,
`arrays 28, the wafer 20 has the appearance illustrated in
`to alloy the aluminum pads 32 with the p" diffused pads
`FIG. 8, where it is inverted.
`29, to assure low resistance ohmic contact between
`A second wafer is prepared in a manner described
`them.
`with respect to FIGS. 7 and 8. In FIG. 7, a buried layer
`As seen in FIG. 3, the next step is to selectively apply
`epitaxial wafer 40 includes a highly resistive undoped
`a very thick layer of photoresist 33 above each of the
`silicon substrate 41 (similar to the substrate 21 in the
`resistor arrays 28 on the wafer. This photoresist layer
`wafer 20) which may be on the order of 300 microns
`maybe on the order of 3 microns thick. Then phospho
`silicate glass (PSG) is sputter deposited to a thickness on
`thick and serves, temporarily as a handle or carrier
`during the initial processing of the wafer 40. The buried
`the order of 0.5 microns. This thin layer of PSG 34 is
`epitaxial layer 42 is a p+ type layer doped with boron,
`placed over the bonding pads 29, 32 to protect the P/N
`junctions thereof from contamination by mobile sodium
`similar to the layer 22 in the wafer 20, and may be on the
`50
`ions, which accomplish ?eld assisted bonding employ
`order of 5 microns thick. The upper layer 43 is highly
`resistive undoped silicon, the same as the substrate layer
`ing borosilicate glass, as described hereinafter. After the
`PSG is deposited, a swabbing etch of the photoresist
`41, and may be on the order 0f 10 microns thick. The
`wafer 40 is oxidized in steam to provide two layers 44,
`will remove the photoresist and the PSG which is
`45 of silicon dioxide on the upper and lower surfaces of
`above the resistor arrays 28. The purpose of removing
`the wafer 40, each of which may be on the order of 0.7
`the PSG above the resistor arrays 28 is to retain the
`microns in thickness. The layer 44 has a plurality of
`ultimate pressure responsive membrane or diaphragm as
`windows photoetched therein (while protecting oxide
`consisting essentially of silicon, so that desired design
`layer 45), each de?ning a cavity‘ which is to register
`criteria for the intended pressure sensors can be pre
`with a corresponding array of resistors 28 in the wafer
`dicted using silicon model information. In order to en
`20. And then a standard ethylene diamene pyrocatechol
`sure protection of the P/N junctions of the diffused
`bonding pads 29, the PSG 34 should extend about 25
`and water mixture GEDPW)‘ is utilized for 15 to 30 min
`microns beyond the diffused pads 29, in each direction.
`utes to chemically etch away those portions of the un
`doped silicon layer 43 which are to form cavities 46 in
`In the next series of steps, a layer of aluminum 36
`the ?nished composite pressure sensor as described
`(FIG. 5) is laid down over the entire wafer, except for
`hereinafter. If desired, the standard EDPW etch can be
`the areas that eventually will be the pressure sensitive
`speeded up by mixing with a catalyst such as quinoxa
`membranes or diaphragms 16 (FIG. 10) near the resistor
`arrays 28. The aluminum layer 36 extends through the
`lene so as to reduce the etching time and to provide a
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`more uniform surface in the p+ layer 42 following the
`The composite wafer is then sawed into individual
`etch. During the etching processes, one aspect of the
`chips (FIG. 9), such as along the dash lines 49, FIG. 10.
`All remaining processing is performed individually on
`invention is that the p+ boron layer 42 acts as an etch
`stop since the rate of etching silicon heavily doped with
`each chip, although several chips may be processed at
`boron is about one hundred times slower than the rate
`one time in various steps, as is known in the art. Each
`of etching lightly doped silicon (layer 43).
`chip is vacuum bonded at about 350° C. to a piece of '
`gold-plated molybdenum shim stock 50 (FIG. 9), which
`After etching all of the cavities 46, while the wafer is
`still in its original registration, the wafer 40 is suitably
`may be on the order of 25 microns thick. This serves as
`a carrier for the pressure sensor during the remaining
`shaped with 90° offset etch ?ats or saw cuts so as to be
`processing and also permits utilization of the pressure
`registerable properly with the wafer 20. Then any re
`sensor in some particular applications described herein
`maining silicon dioxide in the layers 44, 45 is stripped
`after. The chip is then immersed in hydro?uoric acid
`from the top and bottom surfaces. Then a thin layer of
`for a few minutes to remove the silicon dioxide layer 25
`aluminum 47 (FIG. 8), which may be on the order of 0.2
`on the upper surface of the wafer 20 (FIG. 8), and then
`microns to 9.5 microns thick, is evaporated across the
`the entire chip is immersed in EDPW for several hours
`entire bottoni‘surface of the wafer 40, and the wafer 40
`to remove the undoped silicon substrate 21 (FIG. 8)
`is heat treated at about 500° C. for a few minutes to form
`down to the p+ etch stop 22 (FIG. 9). Then, a thin
`a low resistive ohmic contact between the layer 47 and
`photoresist is laid down over the upper surface of the
`the undoped silicon substrate 41. The purpose of the
`layer 22 (FIG. 9) and the lower surface of the molybde
`layer 47 is to apply a uniform electric ?eld with respect
`num shim stock 50; windows 51 are opened in the pho
`to the patterned aluminum layer 36 in the wafer 20, as
`toresist above the aluminum bonding pads 32; and each
`the two wafers are ' joined by ?eld assisted bonding.
`chip is plasma etched, with a freon gas formulation such
`Referring to FIG. 8, the wafer 20 is shown inverted
`as PDE-lOO, through the p+ etch stop 22, the n- layer
`from its position in FIGS. 1-6, and registered with
`23, the p- diffused bonding pads 29, to the aluminum
`respect to the wafer 40 so that each of the cavities 46 in
`bonding pad 32, which acts as an etch stop. This exposes
`25
`the wafer 40 is aligned with a corresponding membrane
`the aluminum bonding pads 32 to permit ultrasound or
`or diaphragm portion of the wafer 20 adjacent to the
`stitch bonding of conductors (not shown) to the alumi
`resistor arrays 28. At some remote part of the wafer 20,
`num bonding pads 32. The conductors may then be
`buffered hydrofluoric acid, EDPW and ammonia may
`secured in a desired fashion to the molybdenum shim
`be used to provide a window through the oxide 25
`stock 50 with a suitable epoxy. The entire chip should
`followed by use of plasma etching to provide a window
`not be encapsulated with a protective coating of epoxy
`through the undoped silicon substrate 21, the p+ epitax
`since that would desensitize the diaphragm 16. Pressure
`ial layer 22, the n— epitaxial layer 23, the silicon dioxide
`sensors in accordance with the present invention, being
`passivation layer 30'and the phosphosilicate glass layer
`only on the order of 55-60 microns thick, are particu
`34, so as to permit making electrical contactwith the
`larly useful, for instance, to sense pressure at particular
`aluminum layer 36 (see FIG. 10). The aluminum layer
`points within gas turbines, and may therefore be metal
`36 appears everywhere in the wafer 20_ except in the
`lic eutectic bonded directly to blades and vanes within
`regions near the resistor arrays 28. With the aluminum
`the engine. In such case, the bottom surface of the mo
`layer 47 of the wafer 40 connected to the positive side of
`lybdenum shim stock 50 (FIG. 9) should be kept clean
`a 40 to 50 volt DC supply, and the aluminum layer 36
`for bonding to other metal surfaces.
`40
`connected to the negative side, ?elds will exist between
`Another embodiment of the invention is illustrated in
`the two wafers everywhere except across the cavities
`FIGS. 11-13. This utilizes a fundamental mode bulk
`46. The wafers are heated to about 350° C. in a vacuum
`acoustic wave device, in place of the piezo-resistive
`of about 10*4 Torr, and then the voltage is applied
`bridge. The device and the manner of making it are
`between the aluminum layers 36, 47. This causes the
`fully set forth in a commonly owned copending U.S.
`two wafers to be attracted to each other and to seal
`patent application entitled Fundamental, Longitudinal,
`tightly, the borosilicate glass 38 bonding with the un
`Thickness Mode Bulk Wave Resonator, U.S. Ser. No.
`doped silicon ;layer 43, in which the cavities 46 are
`203,211, ?led on Nov. 3, 1980 by Black et al, now U.S.
`formed. Since- ?eld assisted bonding is not well suited to
`Pat. No. 4,320,365, which is incorporated herein by
`join borosilicate glass to metal, and since it cannot be
`reference. To facilitate correlation of the brief descrip
`performed through phosphosilicate glass, the borosili
`tion of such device herein and the more extensive de
`cate glass is preferably applied to the wafer 20, and not
`scription in the aforementioned application, reference
`to the wafer 40.
`numerals used in FIGS. 11-13 which correspond ex
`After the wafers 20, 40 are sealed together by ?eld
`actly or substantially with reference numerals in the
`assisted bonding, the resultant composite wafer (as seen
`aforementioned application are in a three digit, one
`inFIG. 8) includes a plurality of cavities 46 disposed
`hundred series, the last two digits of which in this de
`adjacent corresponding resistor arrays 28, so as to form
`scription correspond to the reference numerals in the
`a plurality. of absolute pressure sensors. Then, the alumi
`aforementioned application. Thus, reference to a wafer
`num layer 47 is stripped off the bottom surface of the
`110 herein corresponds to the wafer 10 in the aforemen
`wafer 40, such as -by immersion in hydrochloric acid.
`tioned application, etc.
`The entire undoped-silicon substrate 41 of the wafer 40
`Referring to FIGS. 11 and 12, an epitaxial wafer 110
`is etched off in EDPW (perhaps with some quinoxalene
`comprises a p+ layer 112 highly doped with boron, to
`catalyst) at about 115° C. for several hours. This'will
`act as an etch stop as described hereinbefore, and an
`etch through the silicon until‘it reaches the p+ layer 42,
`undoped highly resistive thick silicon substrate 114
`which acts as an etch stop. A bonding layer 48 (about 3
`joined at the line 116. A silicon dioxide isolation layer
`microns thick) of gold-germanium‘ eutectic is RF sput
`118 is grown thereon, after which a counterelectrode or
`ground plane 120 is deposited. This may preferably
`tered on the exposed lower surface of the p+ etch stop
`42. This completes processing'of the composite wafer.
`comprise a layer of gold sandwiched between thin lay
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`providing a layer of borosilicate glass over the entire
`second surface of said ?rst wafer except in the
`regions where said devices are formed;
`‘
`processing a second wafer having a second thick
`undoped- silicon substrate extending from a ?rst
`surface of said second wafer and a second highly
`doped silicon etch stop layer adjacent to said sub
`strate to provide a plurality of cavities in said sec
`ond waferextending from a second surface of said
`second wafer, each of said cavities disposed on said
`second wafer so that, with said ?rst and second
`wafers properly registered with their second ,sur»
`faces adjacent one another, each of said devices
`will be disposed adjacent to a corresponding one of
`
`said cavities;
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`ersof titanium. Then a thick layer of zinc oxide 122 is
`teristic which varies with strain at said second
`deposited :by RF diode sputtering. This provides the
`medium in which the ,bulk acoustic wave will subsist.
`On top of the zinc oxide, a chromium-aluminum
`chromium ?lm is deposited so as to provide a pair of
`closely spaced electrodes 124, 125 with corresponding
`connectors 126, 127 leading to bonding pads 128, 129.
`The chromium-aluminum-chromium ?lm also provides
`a conductive plane 55 everywhere on the wafer except
`where the devices are formed in the vicinity of the
`region which will become the diaphragm 15; the con
`ductive plane 55 serves to facilitate the ?eld assisted
`bonding. A photoresist lift-off (or other suitable pro
`cess) is used to provide a layer 38 of borosilicate glass
`(to permit that part of the wafer which forms the dia
`phragm 15 (FIG. 11)) adjacent the cavity 46 (FIG. 13).
`On some remote part of the wafer, which is out of the
`way, plasma etching may be utilized to make contact
`with the‘layer 55, in the same fashion as contact was
`made with the layer 36, in order to impress the suitable
`voltage for ?eld assisted bonding, as is described herein~
`before with respect to the embodiment of FIGS. 7-9.
`A second wafer 40 is prepared as described hereinbe
`fore ‘with respect to FIGS. 7 and 8, and then the wafer
`110, processed. as described with respect to FIGS. 11
`and 12, is registered with the wafer 40. The two wafers
`are joined by ?eld assisted bonding and the composite
`wafer is further processed, as illustrated in FIG. 13, in
`the same fashion as described hereinbefore with respect
`to FIGS. 8 and 9. The edge of the wafer is coated with
`epoxy to protect the zinc oxide 122 from EDPW used
`to etch away the substrate 114. Ultimately, the undoped
`silicon substrate 114 (FIG. 12) is stripped off in the same
`fashion as the substrate 21 is stripped in the preceding
`embodiment, and a plurality of access holes 56*59 are
`plasma etched tothe various layers (in the same fashion
`as providing the access holes of FIG. 9) to permit bond
`ing suitable leads, 130-133 for making contact with the
`pads 128, 129 and with the counterelectrode or ground
`plane 120. The access holes 58, 59 must'be away from
`the diaphragm 15; they are shown in FIG. 13 as being
`above and beyond the view of ,FIG. 11. The individual
`devices should have their access holes 56-59 and their
`edges suitably protected with glass or epoxy to protect
`the zinc oxide layer 122.
`» Thus the invention may be utilized with respect to
`piezo-resistive bridges or bulk acoustic wave devices.
`Similarly, the invention may be utilized in a case where
`the devices that provide an electrical characteristic
`which varies with strain may be suitable surface acous~
`tic wave devices, piezoelectric devices (formed from
`?lms of zinc oxide), or other electronic devices.
`Although the invention has been shown and de'
`scribed with respect to exemplary embodiments
`thereof, it should be understood by those skilled in the
`art that the foregoing and various other changes, omis
`sions and additions may be made therein and thereto
`without departing from the spirit and the scope of the
`invention.
`We claim:
`1. A method of forming a plurality of ultra-thin mi
`croelectronic pressure sensors comprising:
`processing a ?rst wafer having a ?rst thick undoped
`silicon substrate extending from a ?rst surfacev of
`said ?rst wafer and a ?rst highly doped silicon etch
`65
`stop layer adjacent to said substrate to provide a
`plurality of devices at a second surface of said ?rst
`wafer, each of which provides an electrical charac
`
`cutting said composite wafer into a plurality of chips,
`each having one of said pressure sensors;
`bonding each of said chips to a metallic carrier;
`stripping said ?rst‘ undoped silicon substrate from
`each of said chips by etching from said ?rst surface
`of said ?rst wafer to said ?rst etch stop layer; ‘and
`providing conductors on each of said chips to make
`electrical contact with the devices thereon.
`2. A method of forming a plurality of ‘ultra-thin, com—
`posite microelectronic devices comprising:
`processing a ?rst wafer having a thick undoped sili
`con substrate extending from a ?rst surface of said
`?rst wafer and a highly doped silicon etch stop
`layer adjacent to said substrate to provide a plural
`ity of electronic devices at a second surface of said
`
`contacting the borosilicate glass layer of said ?rst
`wafer with said second surface of said second wa
`fer, with said wafers registered so that each of said
`cavities is adjacent to a corresponding one of said
`
`20
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`45
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`7
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`devices;
`
`a
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`
`joining said wafers by ‘?eld assisted bonding in a vac¢
`uum vto provide a composite wafer including a
`plurality of absolute pressure sensors, each formed
`by a corresponding set of a device and'a cavity; '
`stripping said second undoped silicon substrate from
`'said' composite wafer by etching from said ?rst
`surface of said second wafer to ‘said second etch
`stop layer;
`'
`'
`‘
`
`?rst wafer; providing a layer of borosilicate glass over the entire '
`
`
`second surface of said ?rst wafer except in the
`regions where said devices are formed; '1
`processing a second wafer to provide a plurality of
`cavities in said second wafer extending from a
`second surface of said second wafer, eachv of said
`cavities disposed on said second wafer so that, with
`said ?rst and second wafers properly registered
`with their second surfaces adjacentone another,
`each of said devices will be disposed adjacent to a
`corresponding one of said’ cavities;
`'
`~
`contacting the borosilicate glass layer of ‘said ?rst
`wafer with said second surface of said‘second‘wa
`fer, with said wafers registered so that each of said
`‘cavities isadjacent to -a corresponding one ‘of said
`
`‘devices;
`
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`joining said wafers by ?eld assisted bonding in a vac
`uum to provide‘ a composite wafer including. a
`plurality of said devices each formed one surface
`adjacenta corresponding cavity;
`cutting said composite wafers into a plurality of
`chips, each having one of saidv devices;
`
`009
`
`

`
`4,426,768
`10
`9
`stripping said ?rst undoped silicon substrate from
`of said substrate to the electronic device on said
`each of said chips by etching from said ?rst surface
`chip, thereby to form access holes; and
`to said etch stop layer; '
`‘
`attaching electrical conductors to the devices on said
`etching through said chips from the surface of said
`chips through said access holes.
`* * * * *
`etch stop layer which became exposed by stripping 5
`
`15
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`30
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`35
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`40
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`50
`
`55
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`60
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`65
`
`010