min 25, 1961
`
`R. N. NOYCE
`SEMICONDUCTOR DEVICE-AND-LEAD STRUCTURE
`Filed July 30, 1959
`3 Sheets-Sheet J,
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`2,981,877
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`‘06- i
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`~ OXIDE
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`Sony Corp. v. Raytheon Co.
`IPR2016-00209
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`Raytheon2014-0001
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`will 25, 1961
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`'
`R. N. NOYCE
`SEMICONDUCTOR DEVICE-AND—LEAD STRUCTURE
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`2,981,877
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`Filed July 30, 1959
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`3 Sheets-Sheet 2
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`p 7 av ,
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`Raytheon2014-0002
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`prili 25, 119i
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`R. N. NOYCE
`SEMICONDUCTOR DEVICE-AND-LEAD STRUCTURE
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`2,981,877
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`Filed July so, 1959
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`s Sheets-Sheet 5
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`-/37
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`IN V EN TOR.
`P085497 /V. A/arc:
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`Array/WK!
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`Raytheon2014-0003
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`.1‘ L77
`Patented Apr. 25, 196i
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`it]
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`layer, in turn, overlies a still larger N~type region which
`constitutes the collector layer of the transistor. Between
`the emitter and base layers there is a dished, P~N junc
`tion 3, having a circular edge which extends to surface 2
`and there completely surrounds the emitter. Between
`the base and collector layers there is a dished, P-N junc
`tion 4, having a circular edge that extends to surface 2
`and there completely surrounds the base. The thick
`ness of the emitter and base layers has been exaggerated
`in the drawings: in actual practice each of these layers
`is but a few microns thick. The collector layer generally
`is considerably thicker, and in the example illustrated
`extends completely through the body 1 so that contact
`thereto may be made from the back side. Thus, the three
`extrinsic semiconductor layers described form a transistor
`equivalent to previously known types of double-diffused
`junction transistors.
`During diffusion of the donor and acceptor impurities
`into the semiconductor, at elevated temperature in an
`oxidizing atmosphere, the surface of the silicon oxidizes
`and forms an oxide layer 5, often one micron or more
`in thickness, congenitally united with and covering sur
`face 2. This layer may consist chie?y of silicon dioxide,
`or of disproportionated silicon suboxide, depending upon
`the temperature and conditions of formation. In any
`event, the oxide surface layer is durable and ?rmly adher
`ent to the semiconductor body, and furthermore it is a
`good electrical insulator.
`According to common prior practice in manufacturing
`diffused-junction transistors, the semiconductor body was
`deoxidized by chemical etching prior to deposition of
`metal contacts on the semiconductor surface. According
`to the present invention, only selected portions of the oxide
`layer are removed, as illustrated in Figs. 1 and 2, for ex
`ample, while other portions of the oxide layer are left
`in place to serve as insulation for electrical leads used
`in making connections to and between the several semi
`conductor regions.
`In particular, portions of the remaining oxide ?lm
`extend acrosstthe edges" of the P—N junctions at the sur
`face of the semiconductor body. to facilitate the making
`of electrical connections from one side of a junction to
`another without shorting the junction. Thus, as illus
`trated in Figs. 1 and 2, the remaining oxide ?lm com
`prises a tongue 5’ that crosses the edge of junction 4, and
`another tongue 5" that crosses the edges of both junc
`tions 3 and 4. On the other hand, at least a portion of
`the surface over each of the emitter and base layers must
`be cleared to permit the formation of base and emitter
`contacts.
`A convenient and highly accurate way to remove only
`selected portions of the oxide ?lm is to use photoengraving
`techniques. The phiotoengraving resist is placed over the
`oxide-coated surface, and this is then exposed through a
`master photographic plate having opaque areas cor
`responding to the areas from which the oxide is to be
`removed. In the usual photographic developing, the un
`exposed resist is removed; and chemical etching can then
`be employed to remove the oxide layer from the unex
`posed areas, while the exposed and developed resist serves
`as a mask to prevent chemical etching of the oxide areas
`that are to be left on the semiconductor surface.
`A discoid, metal, emitter contact 6 is adherent to sur
`face 2, wholly Within the edge of junction 3, centered
`upon and in electrical connection with the emitter re
`gion of the transistor.
`Electrical connections to this
`emitter contact are made through a metal strip 7 ex
`tending over and adherent to oxide layer 5. The strip
`7 extends over the tongue 5" of the insulating oxide
`layer across the junctions 3 and 4, and thus provides
`an electrical connection extending from one side of the
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`SEMICUUCTUR DlEVlllClE-AND-LIEAD
`STRUCTURE
`Robert N. Noyce, Los Altos, (Calif, assignor to Fair'child
`Semiconductor (Iorporation, Mountain ‘View, Calif“, a
`corporation of Delaware
`lFiled .lluly 30, 1959, Ser. No. 830,507
`‘110 tjlaims. (Cl. 317-235)
`
`This invention relates to electrical circuit structures
`incorporating semiconductor devices. Its principal ob
`jects are these: to provide improved device-and-lead
`structures for making electrical connections to the various
`semiconductor regions; to make unitary circuit structures
`more compact and more easily fabricated in small sizes
`than has heretofore been feasible; and to facilitate the
`inclusion of numerous semiconductor devices within a
`single body of material.
`‘
`In brief, the present invention utilizes dished junctions
`extending to the surface of a body of extrinsic semicon
`ductor, an insulating surface layer consisting essentially
`of oxide of the same semiconductor extending across the
`junctions, and leads in the form of vacuum-deposited or
`otherwise formed metal strips extending over and ad
`herent to the insulating oxide layer for making electrical
`connections to and between various regions of the semi
`conductor body without shorting the junctions.
`The invention may be'better understood from the fol—
`lowing illustrative description and the accompanying
`drawings.
`I
`Fig. 1 of the drawings is a greatly enlarged plan view
`of a transistor~and-lead structure embodying principles
`of this invention;
`Fig. 2 is a section taken along the line 2--2 of Fig._l;
`Fig. 3 is a greatly enlarged plan view of a multi-device
`semiconductor-and-lead structure embodying principles of
`this invention;
`Fig. 4 is a section taken along the line 4i——4l- of Fig. 3;
`Fig. 5 is a simpli?ed equivalent circuit of the structure
`shown in Figs. 3 and 4, with additional circuit elements
`external to said structure represented by broken lines;
`Fig. 6 is a greatly enlarged plan view of another tran
`sistor-and-lead structure embodying principles of the
`invention;
`Fig. 7 is a section taken along the line ‘7——7 of Fig. 6.
`Figs. 1 and 2 illustrate one example of a structure ac
`cording to this invention. A single-crystal body of semi
`conductor-grade silicon, represented at 1, has a high
`quality surface 2, prepared in accordance with known
`transistor technology. Within the body 1 there are high
`resistivity regions, designated I in the drawing, composed
`either of high-purity silicon having so few donor and
`acceptor impurities that it is a good insulator at ordinary
`temperatures and an intrinsic semiconductor at elevated
`temperatures, or of somewhat less-pure silicon containing
`a trace of a material such as gold that diminishes the
`effect of donor and acceptor impurities by greatly re
`ducing the carrier concentrations.
`Elsewhere within body 1, there are extrinsic N-type and
`extrinsic P-type regions, designated N and P respectively,
`formed in the well~known manner by diffusing N~type
`and P-type dopants through surface 2 into the crystal, with
`appropriate masking to limit the dopant to the desired
`areas.
`The smallest and uppermost N-type region con
`stitutes an emitter layer of the transistor. This emitter
`layer overlies a somewhat larger P-type region which
`constitutes the base layer of the transistor. The base
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`composite structure inward to the central emitter con
`tact, without shorting any of the transistor junctions.
`The base contact is a C-shaped, metal strip 8, adherent
`to surface 2 wholly between the edges of junctions 3 and
`4, substantially concentric with the emitter contact 6 and
`substantially encircling the junction 3.
`It will be noted
`that tongue 5" and lead 7 extend between the two ends
`of the C-shaped contact 8, so that lead 7 and the emitter
`contact are effectively insulated from the base contact
`even though the base contact substantially surrounds the
`emitter junction. Electrical connection to contact 8 is
`made through a metal strip 9 extending over and ad
`herent to the insulating oxide layer 5. Strip 9 extends
`over tongue 5’ across the collector junction 4, and thus
`provides an electrical connection from one side of the
`composite structure into the base layer, which in this em
`bodiment is completely surrounded by the collector lay
`er at the surface 2, without shorting the collector junc
`tion 4.
`Various methods may be employed for forming the
`base and emitter contacts and leads. By way of example,
`the contacts and leads can be deposited in the con?gura
`tion shown by direct vacuum evaporation of aluminum,
`or other suitable contact metal, through a mask of suit
`able size and shape. Alternatively, a metal coating may
`be deposited over the entire upper surface of the com
`posite structure, and the unwanted metal then removed
`by‘ known photoengraving techniques to leave only the
`contact-and-lead con?guration shown. After the contacts
`have been deposited upon surface 2 of the semiconductor,
`the structure is usually heated to form an alloy at the
`metal-silicon interface so that good, ohmic contact be
`tween the metal and the silicon is obtained.
`It will be noted that regions of high-resistivity silicon
`are made to underlie portions of the leads 7 and 9. The
`principal purpose in this is to reduce the shunt capacitance
`between the leads and the semiconductor body. Other
`wise, an undesirably high shunt capacitance may exist
`in some cases since the extrinsic semiconductor regions
`are fairly good conductors, and the insulating layer 5
`has a thickness of only one to two microns. The high
`resistivity regions act essentially as insulators rather than
`as conductors, and thus reduce the area of closely spaced
`conductors that lead to high shunt capacitances. Of
`course, in cases where the shunt capacitance is not ex
`cessive for the purposes desired, use of high-resistivity
`regions as disclosed is not required.
`The transistor structure is completed by' an electrical
`contact to the collector layer, which may take the form
`of a metal coating 10 plated over the entire back side
`of the silicon body.
`Even in a single transistor, as illustrated in Figs, 1 and
`2, the composite semiconductor-and-lead structure pro
`vided by this invention has signi?cant advantages. Ac
`cording to prior practice, electrical connection to the
`base and emitter contacts had to be made by fastening
`wires directly to the contact areas. This led to certain
`manufacturing di?iculties, particularly in the case of small
`devices wherein, for example, the emitter region might
`be only a few mils in diameter and a few microns in
`thickness. Merely to position the emitter lead on the
`emitter contact in such small structures required the
`use of microscopes and micro-manipulators; and the use
`of any considerable pressure or considerable heat in mak-
`ing the joint permanent could cause suf?cient damage to
`destroy the transistor.
`By means of the present invention, the leads 7 and
`9 can be deposited at the same time and in the same
`manner as the contacts themselves. Furthermore, leads
`'I and 9 can be made as large as may be desired at the
`point where wires or other external circuit elements are
`to be attached; and such attachments can be made at a
`distance from the active elements of the transistor proper,
`so that the chances of damage to the transistor are sig
`ni?cantly reduced.
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`2,981,877
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`4
`Further advantages accrue when it is desired to in
`corporate more than one circuit device into a single body‘
`of semiconductor. In this way exceptionally compact
`and rugged circuits can be constructed. One example of
`such a multi-device structure is illustrated in Figs. 3
`and 4.
`A single-crystal body 11 of silicon, largely P-type, has
`a. high-quality surface 12 prepared in accordance with
`well known transistor technology. The other side of body
`11 is plated with a metal coating 13, which serves as an
`electrical contact to the largest P-type region and as a
`ground plane for the electrical circuit. Various circuit
`elements may be formed within and on this body of sili
`con' N-type and P-type dopants, restricted to speci?c
`areas by known masking techniques, are diffused through
`surface 12 to form a plurality of N-type and P-type ex
`trinsic semiconductor regions, separated from the under
`lying P-type region and from each other by a plurality
`of dished, P-N junctions of various diameters and depths,
`all having, in this particular example, circular edges ex
`tending to surface 12 and there surrounding the over
`lying semiconductor regions.
`Toward the left end of the structure illustrated in Figs.
`3 and 4, there will be found an N-type region overlying
`a small P-type region and separated therefrom by a dished
`junction 14. The small P-type region overlies another
`N-type region; and the underlying N-type region in turn
`overlies the large, grounded P-type region and is sep
`arated therefrom by a dished junction 15. The junction
`between the two intermediate layers is shorted by con
`tact 17. Consequently, this structure provides two recti
`fying junctions connected in series, each equivalent to a
`crystal diode.
`Electrical connection to the upper N-type region is
`made through a discoid, metal contact 16, adherent to
`surface 12, wholly within junction 14 and substantially
`centered upon the N-type region. Electrical contact to
`the two regions between junctions 14 and 15 is made
`through a C-shaped metal contact 17, adherent to surface
`12, wholly between the edges of junctions 14 and 15,
`concentric with contact 16 and substantially encircling
`the edge of junction 14, which extends to the surface 12.
`Proceeding toward the right in the drawings, there will
`be found another N-type region, separated from the
`underlying, grounded, P-type region by a dished junc
`tion 18. Electrical connection to the N-type region in
`this case is made through a discoid, metal contact 19,
`adherent to surface 12 and substantially centered inside
`the edge of junction 18, which extends to the surface of
`the semiconductor.
`,
`Toward the right end of the structure illustrated, there
`‘will be found a small N-type region overlying a P-type
`region and separated therefrom by a dished junction
`20. The. last-mentioned P-type region in turn overlies a
`larger N-type region and is separated therefrom by a
`dished junction 21. The N-type region below junction
`21 in turn overlies the grounded P-type region and is sep
`arated therefrom by a dished junction 22. In this case,
`the width of the P-type region between junctions 20 and
`21 is less than a diffusion length, so that a substantial
`proportion of the electrons that cross junction 20 are
`collected by junction 21. The result is an N-P-N
`junction transistor, in which the small N-type region over
`lying junction 20 acts as the emitter, the P-type region
`between junctions 20 and 21 acts as the base, and the
`N-type region between junctions 21 and 22 acts as the
`collector. The width of the last-menttioned N-type region
`is greater than a diffusion length, and consequently there
`is little interaction between junctions 21 and 22. As will
`be explained hereinafter, junction 22 is normally reverse
`biased and acts much as a capacitor in the overall cir
`cuit.
`It serves the important function of isolating the
`collector of the transistor from the grounded, underlying,
`P-type region.
`Electrical connections to the three active regions of the
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`transistor are made as follows: A discoid, metal Contact
`plane 13 of the physical structure shown in Figs. 3 and
`23 is adherent to surface 12, Wholly Within the edge of
`4. Lead 28 conducts the signal through contact 17 into
`junction 20, centered upon and in electrical connection
`the two layers between junctions 14 and 15. As herein
`with the emitter layer of the transistor. A C-shaped
`before explained, each of the junctions 14 and 15 per
`contact 24 is a metal strip adherent to surface 12 between
`forms essentially the functions of a crystal diode recti
`junctions 20 and 21, substantially surrounding the circu
`?er, as schematically represented at 14' and 15', Fig. 5.
`lar edge of junction 20 that extends to the surface of the
`Thus, as is evident from the equivalent circuit shown in
`semiconductor body. This contact overlies and is in
`Fig. 5, the input signal is recti?ed or detected by the
`electrical connection with the base layer of the transistor.
`junctions 14 and 15, to provide at contact 16 a signal
`Another and larger‘ C-shaped contact 25, which overlies
`essentially corresponding to the modulation envelope of
`and is in’ electrical connection 'with the collector layer,
`the input signal. Because of its appreciable resistance,
`is likewise in the form of a metal strip, adherent to sur
`lead 3!) acts as a circuit resistor, represented in Fig. 5 as
`face 12 between junctions 21 and 22, and surrounding
`30'. It will be noted that the polarity of rectifying junc
`the circular edge of collector junction 21 that extends to
`tions 14 and 15 is such that the signal supplied to con
`the surface.
`tact 19 has a D.-C. component of the polarity required
`Still another contact is provided upon and adherent to
`to reverse-bias junction 18. Hence, the voltage across
`surface ‘12. This is the discoid, metal contact 26, di
`junction 18 is always in the high-resistance direction of
`rectly upon and in electrical connection with the grounded
`the junction, and there is no appreciable current ?ow
`P-type layer, for the purpose of providing a ground
`across this junction. However, there are charge layers
`terminal at the upper surface of the composite struc
`on both sides of the junction which form a capacitance,
`as is well known, and therefore the circuit function of
`ture.
`Except for the contacts described above, the entire
`junction 18 is to provide a capacitance, represented in
`surface 12 is covered with an insulating layer 27 of
`Fig. 5 at 18'. The value of this capacitance can be
`oxidized silicon, generally about one micron thick. This
`made greater or less, as desired, by increasing or de
`insulating layer may be formed upon the exposed sur
`creasing the area of junction 18.
`face of the silicon during di?usion of the N-type and P
`Lead 31 has an appreciable resistance and therefore
`type dopants into the silicon, at elevated temperatures
`acts as a circuit resistor, represented at 31', Fig. 5. This
`and in an oxidizing atmosphere. The presence of water
`leads to the base contact 24 of the transistor, shown at
`vapor will enhance oxidation of the silicon. Preferably,
`24’ in Fig. 5. The emitter contact of the transistor is
`in accordance with this invention and contrary to prior
`connected through lead 32 and contact 26 to the grounded
`practice, after diffusion is completed the oxide layer is
`P-type semiconductor region. This is represented in
`never removed from the silicon, except for the areas to
`Fig. 5 by the emitter terminal 23' connected through
`be covered by the contacts herein described. The con
`resistor 32' to the ground line 13’. The value of the
`tact areas are cleared by photoengraving, after which
`resistor 32’ is the sum of the resistances of contacts 23
`the contact metal can be deposited by various known
`and 26, lead 32, and the current path through the P-type
`processes, e.g., by the vacuum deposition of an alumi
`layer between contact 26 and ground plane 1?».
`num ?lm covering both the cleared and oxide-coated
`Normal operation of the N-P-N transistor requires
`areas. Afterwards, unwanted metal can be removed
`that the N-type collector be supplied with a relatively
`from the oxide-coated areas by photoengraving. The
`positive voltage, as is accomplished in the equivalent
`40
`aluminum contacts may be alloyed to the silicon to make
`circuit illustrated in Fig. 5 by the external voltage sup
`ply 36 connected to the collector terminal 25’ through
`ohmic contacts in a known manner.
`The circuit structure is completed by providing metal
`any appropriate load 35. It is evident that this supply
`strips extending over and adherent to the insulating oxide
`voltage reverse-biases junction 22, and therefore, for
`layer 27 and making electrical connections to and be
`reasons already explained, the junction 22 acts essential~
`tween the various contacts heretofore described. These
`ly as a capacitor, represented at 22' of the equivalent
`metal strips may be deposited by vacuum evaporation
`circuit shown in Fig. 5.
`and deposition, and may conveniently be parts of the de
`It should now be apparent that the structure shown
`posited ?lm from which contacts are made. The leads
`in Figs. 3 and 4 comprises, within a single, rugged, com~
`come from portions of the film that are deposited onto
`pact .unit, detector, ?ltering, and transistor-ampli?er
`the oxide ?lm and are thereby insulated from‘the semi
`stages. It is believed to be evident that the principles
`conductor body. As hereinbefore explained, photoen
`of this invention make feasible the construction of an
`graving can be used to remove the unwanted metal, leav
`endless variety of circuit combinations, including com
`ing only the leads and contacts.
`binations much more elaborate and complex than the
`In the structure illustrated, there is an input lead 28
`simple circuit employed for purposes of illustration, all
`electrically connected to contact 17, and an output lead
`within a highly compact and rugged, essentially unitary,
`29 electrically connected to contact 25. A lead 30 inter
`solid body.
`connects contacts 16 and 19;‘ if desired, lead 30 can be
`Figs. 6 and 7 show an example in which the emitter
`made sufliciently thin and narrow to have an appreciable
`and base contacts are parallel strips. A single-crystal
`resistance, and thereby serve as a resistance element in
`body 37 of silicon contains a P-type, emitter layer over
`the circuit. A similar lead 31 interconnects contacts 19
`lying an N-type, base layer and separated therefrom by
`and 241, and still another lead 32, which may be made to
`a dished junction 38, which extends to the upper surface
`have an appreciable resistance if desired, interconnects
`of the semiconductor and there surrounds the P-type,
`contacts 23 and 26.
`emitter layer. In this case, the edge of junction 38 does
`The solid lines in Fi g. 5 represent the simpli?ed, equiva
`not form a circle at the surface, but forms an elongated,
`lent circuit for the structure shown in Figs. 3 and 4, while
`closed ?gure. The N-type, base layer overlies a P-type,
`the broken lines in Fig. 5 represent typical external cir
`collector layer and is separated therefrom by a flat junc
`cuit components added for purposes of explanation.
`tion 39‘.
`The solid-line parts are identi?ed by reference numbers
`identical to the reference numbers of corresponding parts
`The emitter contact 40 is a straight strip of metal,
`in the structure of Figs. 3 and 4, with the addition of a
`vacuum-deposited or otherwise placed upon the upper
`prime to the reference numbers in Fig. 5.
`surface of the silicon, and preferably alloyed thereto to
`Any desired source of an amplitude~modulated, A.-C.
`form an ohmic contact. The base contact 41 is a similar
`signal is represented at 34- in Fig. 5. This A.-C. signal
`strip of metal, parallel to contact 40. The edge of junc
`is applied between the input lead 28' and the ground
`tion 38 extends between the two contacts, and around
`connection 13', corresponding to lead 2d and ground m contact 40, as shown. The collector contact 412. may be
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`a metal layer plated onto the bottom surface of the
`silicon.
`Except for the areas covered by contacts 40‘ and 41,
`the upper surface of the silicon is covered by an insulat
`ing oxide layer, congenitally united with the silicon and
`actually formed by heating the silicon in an oxidizing at
`mosphere. The oxide layer completely covers the edge
`of junction 38, and protects the junction against acci
`dental shorting in addition to providing insulation be
`tween the electrical leads and the silicon.
`Electrical connection to contact 40 is made by a metal
`strip 43, extending over and ?rmly adherent to the
`oxide layer. Electrical connection to contact 41 is made
`by a metal strip 44, similarly extending over and ?rmly
`adherent to the oxide layer. These metal strips can be
`formed by vacuum deposition through a mask, or by
`plating the entire surface and then removing unwanted
`metal by photoengraving, or by any other method pro
`viding metal strips that adhere securely to the oxide
`surface.
`The invention in its broader aspects is not limited to
`the speci?c examples illustrated and described. What
`is claimed is:
`1. A semiconductor device comprising a body of semi
`conductor having a surface, said body containing adja
`cent P-type and N-type regions with a junction therebe
`tween extending to said surface, two closely spaced con
`tacts a adherent to said surface upon opposite sides of
`and adjacent to one portion of said junction, an insulat
`ing layer consisting essentially of oxide of said semicon
`ductor on and adherent to said surface, said layer ex
`tending across a different portion of said junction, and
`an electrical connection to one of said contacts com
`prising a conductor adherent to said layer, said con
`ductor extending from said one contact over said layer
`across said different portion of the junction, thereby
`providing electrical connections to both of the closely
`spaced contacts.
`2. A semiconductor device comprising a body of ex
`trinsic semiconductor having a surface, said body con
`taining adjacent P-type and N-type regions, one overly
`ing the other, with a junction therebetween extending to
`said surface and there completely encircling said over
`lying region, the underlying one of said regions extend
`ing to said surface and there surrounding said junction,
`a ?rst metal contact adherent to said surface in ohmic
`electrical connection with said overlying region, an in
`sulating layer consisting essentially of oxide of said semi
`conductor united with said surface and extending across
`said junction, a metal strip adherent to said layer, said
`strip being electrically connected to said ?rst contact
`and extending therefrom over said layer across said
`junction, and a second metal contact adherent to said
`surface in ohmic electrical connection with said underly
`ing region, said second contact substantially encircling
`said junction from one side of said strip to the other.
`3. A semiconductor device comprising a body of
`extrinsic semiconductor having a surface, said body con
`taining adjacent P-type and N-type regions with a dished
`junction therebetween having a substantially circular
`edge at said surface, a discoid metal contact adherent
`to said surface whollv within and substantially con
`centric with said ctlgc, a C-shaped metal contact ad
`herent to said surface and substantially concentric with
`said discoid contact, said (;-shaped contact being wholly
`outside of and substantially encircling said edge, said
`C-shaped contact having two ends de?ning a gap there
`between, an insulating layer consisting of oxide of said
`semiconductor on said surface extending through said
`gap and across said junction, and a metal strip over and
`adherent to said layer extending through said gap and
`across said junction to said discoid contact, said contacts
`being in direct electrical connection with respective ones
`of said regions, and said metal strip being in direct elec
`
`trical connection with said discoid contact but spaced and
`insulated from the ends of said C-shaped contact.
`4. A diffused junction transistor comprising a body of
`extrinsic silicon having a surface, said body containing
`adjacent base and emitter regions, with a discoid emitter
`junction therebetween having a substantially circular
`edge at said surface encircling said emitter region, a
`discoid metal contact to said emitter region adherent to
`said surface wholly within said edge, a C-shaped metal
`‘contact to said base region adherent to said surface and
`substantially encircling said edge, said C-shaped contact
`having two ends de?ning a gap therebetween, an insulat
`ing layer of oxidized silicon on said surface, said layer
`being congenitally united with said body and extending
`across said junction, and a metal strip adherent to said
`layer, said strip extending from said discoid contact over
`said layer across said junction and between said ends
`forming an electrical connection to said emitter region.
`5. A semiconductor device comprising a single-crystal
`body of semiconductor material having a surface, said
`body containing a high-resistivity region and extrinsic
`P-type and extrinsic N-type regions with a P-N junction
`therebetween extending to said surface, a metal contact
`to one of said extrinsic regions adherent to said surface,
`an insulating layer consisting essentially of oxide of said
`material on said surface, said layer being congenitally
`united with said body and extending across said junction,
`and an electrical connection to said contact comprising
`a metal strip adherent to said layer, said strip extending
`from said contact over said layer across said junction,
`said high-resistivity region underlying a portion of said
`strip, reducing the shunt capacitance between said strip
`and said body.
`6. A semiconductor device comprising a body of semi
`conductor having a surface, said body containing adjacent
`P-type and N-type regions, one overlying the other, with
`a junction therebetween extending to said surface, a ?rst
`metal contact adherent to said surface in electrical con
`nection to said overlying region, a second metalcontact
`in electrical connection with the’underlying one of said
`regions, an insulating layer consisting essentially of oxide
`of said semiconductor on-said surface, said layer being
`congenitally united with said body and extending across
`said junction, an electrical connection to said ?rst con
`tact comprising a metal strip adherent to said layer, said
`strip extending from said ?rst contact over said layer
`across said junction, and circuit means for applying be
`tween said strip and second contact a DC. voltage of the
`polarity that reverse-biases said junction, so that said
`junction acts as a capacitor connected between said strip
`and said second contact.
`7. A semiconductor device comprising a body of ex
`trinsic semiconductor having a surface, said body con
`taining adjacent, ?rst, second and third regions, one over
`lying the other, P-typc and N-type alternately, with a
`?rst, dished, P-N junction between said ?rst and second
`regions having an edge extending to said surface and
`there surrounding said ?rst region, and a second, dished,
`P-N junction between said second and third regions ex
`tending to said surface and there surrounding said second
`region, a ?rst metal contact adherent to said surface in
`electrical connection with said ?rst region, a second metal
`contact adherent to said surface in electrical connection
`with said second region, a third metal contact in elec
`trical connection with said third region, an insulating
`layer consisting essentially of an oxide of said semicon
`ductor on said surface, said layer being congenitally
`united with said body and extending across both of said
`junctions, an electrical connection to said ?rst contact
`comprising a ?rst metal strip adherent to said layer, said
`?rst strip extending from said ?rst contact over said layer
`across both of said junctions, and an electrical connection
`to said second contact comprising a second metal Strip
`adherent to said layer, said second strip extending from
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`55
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`60
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`70
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`75
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`Raytheon2014-0007
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`

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`2,981,877
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`said second contact over said layer