`IPR2016-00209
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`Raytheon2009-0001
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`thorough trade space analysis, the inherent advantages of Si PIN staring FPA technologies for this application led RVS
`to our present design.
`
`Hybrid FPAs using Silicon PIN (Si PIN) diodes are an excellent choice for high sensitivity space applications. Being
`backside illuminated, Si PIN detectors have 100% fill factor and very high quantum efficiency clear through the near IR
`wavelengths. Between 450 nm and 850 nm, Si PIN detectors combined with Raytheon’s anti-reflective coating,
`produces detectors with 8% spectral flatness and peak quantum efficiencies above 92% in the spectral range of interest.
`Excellent signal performance, coupled with Si PIN’s inherent radiation tolerance, makes them an excellent choice for
`space-based applications requiring high sensitivity. Another advantage of using a hybrid technology is the ability to
`utilize a modern CMOS foundry for the readout integrated circuit (ROIC), enabling great flexibility, high density, and
`low power. The detector is then fabricated in a dedicated detector foundry where the processes can be optimized for best
`performance without regard for the needs of the separate CMOS circuit. In the case of this FPA, this approach enables an
`architecture which combines the ability to readout multiple windows at a relatively high frame rate thru a single analog
`output while retaining a simple electrical interface and 120 mW power budget.
`
`RVS responded to these challenges by designing a radiation tolerant, four mega-pixel, mixed-signal FPA for this high
`sensitivity visible imaging application. Each pixel is composed of a Si PIN detector connected to a snap-shot source
`follower unit cell in the readout electronics. Relatively small 10 um pixels are used to collect the incoming photon
`signal. The readout architecture contains one full-speed voltage mode analog output operating at 5 MPPS as well as one
`reference output. Details of this sensor performance as well as an update for Raytheon’s Si PIN visible sensor efforts
`will be given in this paper.
`
`2
`
`READOUT INTEGRATED CIRCUIT DESIGN
`
`The readout electronics were designed to support both STC
`and HRIC using a 2048 X 2048 active pixel array with a
`10 um x 10 um unit cell. The basic design incorporates both
`snapshot as well as integrate-then-read operation at the output
`rate of 5 MPPS readout speed. As shown in the Fig. 2 block
`diagram of the readout, the active sensing array is situated in
`the upper right-hand portion allowing the possibility of one or
`two sided butting. All the control and output pads are located
`at the bottom of the layout. The full array is read out on one
`analog output and one optional reference output is provided
`for calibration and noise mitigation. The 5.5 V CMOS process
`provides a full well capacity greater than 120,000 e- with a
`charge conversion gain of approximately 20 j.LV;"e-. Very low
`noise,
`less than 100 e- RMS with a goal of 60 e- RMS, is |
`obtained with this source-follower unit cell design. A 7'2 bit
`I
`°“"'“’""°" "'°°""°"°°"‘“‘"5""°"‘
`serial command register allows programmable mode controls
`I
`“mm” mm s‘°°'""'" "mm
`and adjustments of reference biases,
`integration time, and
`-
`other
`critical performance parameters.
`Programmable
`I
`P°‘"°"B'”'°°""“P°d5
`windowing on a frame by frame basis is also controlled
`through the same command word. Windowed frames can
`overlap and window sizes can vary from 1 to 2048 in the row direction with one row resolution and from 128 to 2048
`with 64 column resolution. Using extensive experience working with the ROIC foundry, RVS incorporated designs that
`have been proven to be total dose radiation, Single Event Upset (SEU) and Single Event Latchup (SEL) tolerant. The
`ROIC is designed to provide full specification operation from -5 to 25° C and non-specification performance over the
`temperature range of -60 to 40° C,
`
`Fig 2.
`
`Block diagram of the readout integrated electronics.
`
`3 DETECTOR DESIGN AND WAFER PERFORMANCE
`
`The fabrication of high-performance visible sensors starts with the ability to process low—defect, highly uniform PIN
`detectors on high resistivity six inch silicon substrates. The device structure for the visible PIN detectors consists of a p-
`type junction implanted in the detector side and a very thin n- type junction implanted into the light collection side. As
`
`Raytheon2009-0002
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`Proc. of SPIE Vol. 7439 7-4390A-2
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`2048 x 2048 Pixel Active Array
`10 pm 1: 10 um Pixels
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`Raytheon2009-0002
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`shown in Fig. 3, these layers are implanted into a nearly intrinsic silicon wafer, creating the P Intrinsic N structure (PIN).
`The interconnection to the ROIC is also shown. The detector was designed to be fully depleted at low voltages, but can
`be biased from 5 to 100 V to enhance performance and lower crosstalk. The final detector is thinned to approximately
`40 microns to ensure less degradation from proton and neutron damage. This thickness combined with the excellent
`uniformity results in reduced red flinging, and enhanced red and near infiared response. Fig. 4 shows that the absolute
`quantum efiiciency of typical thinned Si PIN detectors provides excellent QB over the entire 400 to 950 nm spectral
`range, and QE > 80% from 450 to 900 nm. The detector was also designed to provide excellent modulation transfer
`function (MTF) at all detected wavelengths, but this performance parameter has not been measured at this time.
`
`
`
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`fill
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`Fig 3.
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`Physical layout of the SiPIN detector.
`
`Typical 293K «detector spectral response characteristics
`Fig 4.
`for a thinned SiPIN detector meet program requirements.
`
`the detectors demonstrated high quantum efficiency (>80% for
`As will be shown from the FPA performance,
`antireflection coated devices) with excellent spectral response.
`
`4
`
`SENSOR CHIP ASSEMBLY DESIGN AND PERFORMANCE
`
`As shown in Fig. 5, the detector and ROIC are fabricated separately, then bonded together to form a single hybrid
`structure. The traditional approach has been to deposit bumps on both the detector and the ROIC, and then hybridize the
`two sections together. This technique has been used for many years, but presents challenges when the pixel size is less
`than about 15 um. Fig. 6 shows an array of high density indium bumps that can be used for sensors with less than 15 um
`unit cells. However, this qualified approach still presents the challenges of interconnect yield and leaves a gap that
`would require epoxy wicking for mechanical stability during the detector thinning operation. For this application, RVS
`has developed a novel oxide bond interconnect solution to eliminate the need for indium bumps altogether. This
`technique has previously demonstrated extremely high interconnect yield and also has the advantage that it leaves no air
`gap between the detector and the ROIC. Fig. 7 shows a SEM picture of a detector direct bond interconnected to a ROIC.
`The five layers of metal in the ROIC can be seen in the lower 80% of the picture and the upper portion is the thinned
`silicon detector that has been oxide bonded to the ROIC and interconnected with metal vias.
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`’ F|*0|l|.2Mll / Pin|tziua,2o-Is} Column Amplifiers
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`Direct Bonding Interconnect (DB|}
`
`Fig 5.
`
`Block diagram of the ROIC interfaced with the detector using direct bond interconnect.
`
`Not to scale
`
`
`
`Fig 6.
`
`Traditional indium bump solution.
`
`SEM of high density Direct Bond Interconnect showing
`Fig 7.
`no air gap between detector in upper portion and ROIC in lower.
`
`For this work, sensor chip assembly (SCA) performance was evaluated using bare ROICs and the first two pathfinder
`engineering SCAs. The science grade sensors were not yet available in time for this paper; however, a subsequent paper
`presenting final performance and radiation data sets is intended to be submitted at the completion of the program.
`
`Initial testing was perfonned on bare readout integrated circuits (ROIC) without detectors, four of which are depicted in
`Fig. 8 bonded in 124 pin leadless chip carriers. The design validation testing was performed on three separate ROICS to
`verify the functionality. Power was designed to be less than 120 mW and was measured to be an average of 97 mW for
`ten devices.
`In Fig. 9, a graph of the unit cell reset voltage versus the output voltage of a bare ROIC at room temperature
`shows that the dynamic range is > 2V and excellent linearity of i 1% has been achieved. Other parameters validated at
`this stage of testing include performance of the command word operation, internal and output amplifier range, normal
`response to variations in integration time, as well as the windowing functions. All of these performance parameters were
`verified operational at both room and operating temperatures.
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`Proc. of SPIE Vol. 7439 7-4390A-4
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`I 0
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`.8
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`0.6
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`0.4
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`STC S3412 Extended Dynamic Range
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`yl 1.216730 0.5859
`R’ 20.9905
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`0.2 Lllhllily[K]
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`D -
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`-0.4 -0.6
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`0.2
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`I
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`1.5
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`2 wmc 2.5
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`3
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`3.5
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`Fig 8.
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`Bare R0lCs mounted on leadless chip carriers for test
`
`Excellent linearity and dynamic range was verified at
`Fig. 9.
`293K on a bare ROIC
`
`Typically, the SCAS are tested at 273K, although they are capable of operating from 200-300K. The SCAS were tested
`under several different flux conditions and spectral ranges to simulate the variety of expected modes of operation. For
`this application, the sensor was designed to operate with detector currents ranging from a minimum of 1 X 106 phfsfpixel
`to a maximum of 2 X 109 phfsfpixel. This photon flux range results in detector currents ranging from 160 fix to 320 pA.
`For the quantum efficiency (QE) measurements, the test conditions used Ff]? optics, pass band filters ranging from 450
`to 900 D111, and an integrating sphere source. These test conditions resulted in a flux level hitting the detector ranging
`from 6 X 10" phfcmz-s to 2 X 10" phfcmz-s.
`
`To begin to analyze the sensor chip assembly test data, the first concern is the number of pixels that are interconnected
`and respond to visible light. For basic signal response, a pixel was considered operable if the measured response was 0.5
`to 1.5 times the mean response of the array. Applying this operability criteria, the functional operability for the two
`pathfinder engineering arrays was found to be 99.96% and 99.99%, respectively. The histogram and grey-scale data is
`shown in Figs. 10 and 11 for SCA ENG-0] and SCA ENG-02. These plots demonstrate very high pixel interconnect
`yield with only 278 and 1835 of more than 4.23 million pixels unresponsive.
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`Raythe0n2009-0005
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`Proc. of SPIE Vol. 7439 7439DA-5
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`[W
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`2.0
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`215
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`I I
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`llfi
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`I2 IZMH
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`2.0I:I|‘ls
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`1.31105
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`Elanunle §5 §.°l‘o‘
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`Nmlbnrot
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`0
`
`Mean :
`St Dev :
`High:
`Low :
`
`2.05430
`3.1De—2
`3.0730
`1.9230
`
`High Limit :
`Low Limit :
`‘ll; Operability
`
`3.0880
`1.0390
`99.96
`
`In :
`High :
`Low:
`Masked .'
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`4192439
`1835
`0
`[I
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`Fig. 10. SCA ENG-01 Signal Unifonnity at 273K shows 99.96% of the array operating within the response specification.
`
`
`
`Mean :
`S104-w :
`High:
`Low :
`
`22590
`5.99s-2
`3.3?a0
`1.3990
`
`High Limit :
`Low Limit '.
`‘ll: Operability
`
`3.3380
`1.13e(‘.|
`99.99
`
`In :
`Huh :
`Low:
`Masked '.
`
`4194026
`2?8
`0
`0
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`Fig. 1 l. SCA ENG-02 Signal Unifomiity at 293K shows 99.99% of the array operating within the response specification.
`
`The absolute QE for SCA ENG-01 and -02, using a band-pass filter at 750 nm, is shown in histogram and grey-scale
`formats in Figs. 12 and 13, respectively. For the quantum efficiency (QE) measurements, the test conditions used Ft‘ 1?
`optics, band-pass filters ranging from 450 to 900 nm, and an integrating sphere source. These test conditions resulted in
`a flux level impinging on the detector ranging from 6 X 10" phfcmz-s to 2 X 10” ph/cmz-s.
`In the analysis of this
`specific test data, the criteria applied to determine whether a pixel was considered operable was :I: 3 sigma from the
`mean.
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`Raytheon2009-0006
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`Proc. of SPIE Vol. 7439 7-4390A-6
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`Mean :
`St Dev :
`High:
`Low:
`
`8.8691
`2.‘fOe0
`9.72e1
`3.0091
`
`High Limit :
`Low Lhnlt :
`% Operabilily :
`
`91261
`‘(.9991
`90.61
`
`In :
`High :
`Low:
`Masked :
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`41??B?2
`628?
`1o1-15
`0
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`Fig. 12. SCA ENG-01 QE at 273 K at 750 nm with 99.61% of the array within 3 sigma of the mean.
`
`
`
`Mean :
`St Dav :
`Hiw :
`Low:
`
`3.2461
`5.5090
`1.0182
`6.33e1
`
`:
`Him L'I‘I1il.
`Law Linlt :
`‘K: Operabiliy :
`
`1.0192
`6.3381
`99.51
`
`In :
`High :
`Law:
`Masked :
`
`41?3821
`90
`20393
`0
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`Fig. 13. SCA ENG-02 QE at 213 K. at 750 nm with 99.51% of the array within 3 sigma of the mean.
`
`input. The root mean square analysis was
`For the noise measurements, the test conditions used a sealed optical
`performed on 128 consecutive frames of data on a per pixel basis.
`In the noise test data, a 3 sigma from the mean
`
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`Proc. of SPIE Vol. 7439 74-390A-7
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`criteria was applied to determine whether a pixel was considered operable. Fig. 14 depicts anay SCA-01 as having a
`good Gaussian noise distribution and 99.8% operability.
`-4
`-a
`-s
`-.1
`-a
`4
`semi
`2.0210
`Llhtlll
`Lmn mute
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`Lani
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`Nmbrotihnum
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`H16
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`Cunulllmfii
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`400
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`6101104 1.OIlO-3 1.511104 2.01106 l.§ulO-3 3.01104
`Stymvolls
`
`Mean:
`St Dev 1
`High :
`Low:
`
`1.286-3
`2.6134
`3.008-3
`3.48-e-4
`
`High Limit:
`Low Limit 1
`‘Kw Operahlllly :
`
`3.003-3
`2003-4
`99.80
`
`In:
`High :
`LOW Z
`Masked :
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`4185119
`6005
`180
`0
`
`Fig 14. SCA ENG-0] noise at 273 K showing a 3 sigma operability of 99.8%.
`
`For the linearity measurement in Fig. 15, the integration time was varied using the command word to step the array from
`starvation to saturation levels. Excellent uniformity and linearity is demonstrated.
`
`Integration time vs output offset @ 260K
`
`4.2
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`4 _
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`
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`3.3 —
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`E 3.6 -
`'5
`g 3.4 —
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`y=392.4Tx+ 2.3854
`R2 = 0.9996
`
`.
`.
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`Fig. 15. SCA ENG-02 Integration time
`versus output offset voltage shows good
`linearity
`
`
`
`1.0E-{J4
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`6.0 E-04
`
`1.1E-03
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`1.6E-03
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`2.1 E-03
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`Integration 11me (sec)
`
`5
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`SYSTEM INTEGRATION
`
`The sensor chip assembly will be integrated into both the Stereo Camera as well as the High Resolution Imaging
`Camera. The primary difference being the filter sets. Both the mechanical units have been assembled and tested and are
`depicted in Fig. 16.
`
`Raytheon2009-0008
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`Proc. of SPIE Vol. 7439 7439DA-8
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`system packages.
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`The FPA is
`Fig 16.
`integrated into each of the
`
`6
`
`SUMMARY
`
`RVS continues to pioneer large-format FPAs for use in ground and space-based astronomy applications by
`demonstrating the latest state-of-the-art Si PIN FPA. Using a novel interconnect solution combined with the large
`investment in Si:PiN process technology, RVS has fabricated and demonstrated performance of a low power analog
`output 2048 X 2048, 10 um sensor with total operabilities as high as 99.9% for high flux conditions. We anticipate this
`device will provide excellent total dose radiation performance with no centroid shift, low gamma noise, and immunity to
`upset or latch-up conditions.
`
`7 ACKNOWLEGEMENTS
`
`RVS wishes to thank the Selex-Galileo science team for providing the opportunity to work with them to design the
`newest addition to the standard astronomy array offerings. This array will provide the ability to unlock mysteries during
`many science missions in the fiiture. RVS also wishes to thank ASI for funding this endeavor.
`
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