United States Patent
`
`Braaten
`
`'
`
`[15]
`
`[45]
`
`3,696,409
`Oct. 3, 1972
`
`[54] FINGER-TOUCH FACEPLATE
`[72] Inventor: Norman J. Braaten, Rosemount,
`Minn.
`v
`
`[73] Assignee: Linquist & Vennum, Minneapolis,
`Minn.
`Dec. 28, 1970
`[22] Filed:
`[21] Appl. No.: 101,752
`
`[52] US. Cl ................. ..340/365, 178/19, 340/324 A
`[51] Int. Cl. ............................................. ..G08c 9/02
`[58] Field of Search .................... ..340/365 C; 178/19
`
`[56]
`
`References Cited
`
`UNITED STATES PATENTS
`
`FOREIGN PATENTS OR APPLICATIONS
`1,176,212
`8/1964 Germany ............. ..340/365 C
`
`Primary Examiner-Thomas B. Habecker
`Attorney-Thomas G. Devine and Lew Schwartz
`
`ABSTRACT
`[5 7]
`A system for identifying a particular position on the
`face of a display device by simply touching the area
`with the ?nger. The area is a conductive pad con
`nected to a relaxation oscillator whose frequency is
`lowered by the touch. The oscillator is therefore
`identi?able and a digital computer is enabled to per
`form a prescribed act such as new information trans
`ferred to the display device, dependent upon the loca
`tion of the area touched.
`
`3,437,795 v
`
`4/1969
`
`Kuljian ................. ..340/365 C
`
`, 6 Claims, 13 Drawing Figures
`
`65
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`Samsung USP 7,973,773
` Exhibit 1012 Page 1
`
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` Exhibit 1012 Page 6
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` Exhibit 1012 Page 7
`
`

`
`1
`FINGER-TOUCH FACEPLATE
`
`3,696,409
`
`2
`and then charges again. Electric charge collected on
`the pad as a result of the electron beam of a cathode
`ray tube, if a cathode ray tube is used, will be con
`ducted from the pad and discharged through the
`unijunction transistor, thus keeping the faceplate free
`of charge.
`An object of this invention is to provide an economi
`cal and reliable means for selecting a given area on the
`face of a display device.
`Another object is to electronically identify a pad that
`has been touched by a person.
`Another object is to permit a person to touch a
`desired word or symbol appearing on the face of a dis
`play device and have a change in the information dis
`played as a result of the touch.
`Still another object is to prevent the buildup of elec
`tric charge on the face of the display device.
`These and other objects will become more apparent
`in the detailed description that follows.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`10
`
`25
`
`BACKGROUND OF THE INVENTION
`Management systems and teaching systems utilizing
`a digital computer lend themselves very well to the use
`of a ?nger-touch faceplate. It is an excellent, simple
`manner of communicating with a digital computer
`where the interface between the operator and the com
`puter has been the subject of much effort over the years
`to be made simpler.
`In the prior art, there have been many efforts made
`to recognize a particular area on the face of a cathode
`ray tube display for example by touching the selected
`area with a conductor, with a “light pen” and with the‘
`?nger. Using only the ?nger as a pointer‘has presented
`problems which have been successfully overcome in
`this invention. In prior art devices, the circuitry has
`been extensive and complex, but most important has
`not been as reliable as desired. Efforts have been made
`to detect a position by wire grids over the face of-a dis
`play device which indicate a position when intersecting
`wires are pressed together to contact each other. There
`have also been light grids used to attempt to locate
`where the operator’s ?nger is placed by interrupting
`the circuit of a photosensitive device. Another interest
`ing prior art approach to solving the problem is found
`in U.S. Pat. No. 3,382,588 in which one or more
`capacitors are made a part of the faceplate of the dis
`play and are intentionally of a high leakage character.
`When the leakage field is interrupted by the operator’s
`?nger, the capacitive reactance is changed and a bridge
`circuit is upset. Another prior art approach is one
`where, in essence, a transmitter is placed in the area of
`the faceplate of the display device and the ?nger acts as
`an antenna. These devices are all highly complex. Ad
`ditionally, it has been found that in many of the prior
`art devices which utilize cathode ray tubes as the dis
`play device, that the electron beam of the cathode ray
`tube causes an undesirable static charge on the areas of
`the faceplate to be touched.
`It will be seen that the invention described herein
`substantially reduces or eliminates these problems.
`
`30
`
`35
`
`FIG. 1 is a block diagram of the system.
`FIG. 2 is a perspective view of the conductive pads
`installed on a display device and the electronics
`package.
`FIG. 3 is a schematic diagram of the relaxation oscil
`‘ lators used in the invention. >
`7 FIG. 3A, FIG. 3B and, FIG. 3C illustrate waveforms
`as seen on the face of an oscilloscope at various
`points within the oscillator of FIG. 3.
`FIG. 4 is a logic diagram of an AND circuit made up
`of a NAND circuit and an inverter.
`FIG. 5 is a logic diagram of a typical counter used in
`this invention.
`FIG. 6 illustrates the use of a ?ip-?op circuit in con
`
`junction with a
`counter, as typically used throughout
`this invention.
`FIG. 7 is a logic diagram of the selectmatrix of FIG.
`1.
`FIG. 8 is a logic diagram of the digital comparator of
`FIG. 1.
`FIG. 9 is an analog representation of the output of
`eight oscillators with none of the associated pads
`touched and of the output of eight oscillators with one
`of the pads touched.
`‘
`
`SUMMARY OF THE INVENTION
`A plurality of conductive pads are attached to the
`face of a display device forming a ?nger-touch
`faceplate. Each pad is electrically connected to an
`oscillator. It has been determined that the human body
`is basically capacitive. Therefore when a person
`touches one of the conductive pads, capacity is added
`in parallel to the capacitance in the RC charge path of a
`relaxation oscillator. The frequency of the oscillator
`output is therefore lowered. A recognition of the fact
`that the frequency has been lowered and of the indenti
`ty of the oscillator with which the touched pad is as
`sociated results in an exact identi?cation of the pad and
`the fact that it has been touched by the operator. This
`knowledge in the form of electric signals
`can then be
`transmitted to a digital computer which will respond in
`a prescribed way. In the preferred embodiment it is or
`dinarily expected that new information will be
`presented on the face of the display device
`replacing
`that which the operator pointed to through the trans
`parent conductive pad.
`In the preferred embodiment, the capacitor in the
`charge path discharges through a unijunction transistor
`
`45
`
`50
`
`55
`
`60
`
`65
`
`DETAILED DESCRIPTION OF THE INVENTION
`FIG. 1 is a block diagram of the system. The
`preferred embodiment has 32 touchplates and there
`fore 32 oscillators. Oscillator 1 and oscillator 32 are
`shown with respective outputs 33 and 64 connected to
`select matrix 91. Oscillators 2 through 31 and connec
`tions 34 through 63 are not shown to avoid confusion.
`The select matrix 91 has outputs 92, 93, 94 and 95
`which terminate in AND circuit 96.
`The system has a master clock 65 whose output 66 is
`connected to AND circuit 68 which has .additional
`input line 67 and output line 69 which is an input to the
`A section 71 of the sequence counter 70. An output 72
`of the A section 71 is an input to AND circuit 73, which
`has additional inputs 87 and 88. The output 89 of AND
`circuit 73 is an input to B section 90 of sequence
`counter 70. Output lines 74 and 85 from the B section
`90 serving as inputs to select matrix 91 are shown. Out
`put lines 75 through 84 from the B section 90 are not
`shown for the sake of simplicity.
`
` Exhibit 1012 Page 8
`
`

`
`4
`to the positive voltage source at one side through con
`ductors 217, 230 and 231. At its other. end, resistor 216 ,
`is connected to resistor 214 through conductor 215.
`The other side of resistor 214 is connected to point A 1
`through conductor 213. The combination of resistors
`216 and 214, together with capacitor 210 form the
`delay circuit for the oscillator.
`‘
`The other plate of capacitor 224 ‘Y is connected
`through conductor 223 to point B. The base of
`transistor 236 is connected to the positive voltage
`source through conductors 235 and234, and through
`resistor 233 and conductors 232 and 231. The emitter
`of transistor 236 is connected through conductor 238
`to ground. The collector'of transistor 236 is connected
`to the positive voltage source through, conductor 237,
`resistor 239, conductor 240-and conductor 231. The
`output from transistor 238 is'taken from its collector
`through conductor 241 to point C and out on conduc
`tor 243. Point C is kept at a speci?ed positive voltage
`by diode 245 connected at its anode to point C through
`conductor 242 and at its cathode through conductor
`244 to a positive voltage source. a
`‘
`'
`’
`'FIG. 3A is a representation of the voltage waveform
`at point ‘A of FIG. 3. The waveform 246 is a plot of volt
`age in the Y direction versus time in the X direction.
`FIG. 3B is a representation of the voltage waveform
`at point B of FIG. 3. Waveform 247 is representative of
`voltage in the vY direction and time in the X direction.
`FIG. 3C is representative of the voltage at point C of
`FIG. 3. Wave 248 represents voltage in the Y direction
`and time in the X direction, illustrating the pulse output
`of the relaxation oscillator of FIG. 3.
`Throughout this discussion, the AND circuit is
`discussed. In practice, the NAND circuit is more readily
`available in integrated circuits. FIG. 4 illustrates AND
`circuit 68 having NAND circuit 205 with inputs A, B
`and C and output D. When A, B andC are all “up”, D
`is “down”, mathematically expressed as a Boolean
`equation:
`
`20
`
`25
`
`35
`
`40
`
`3,696,409
`
`> 3
`Referring "again to AND circuit 68, it can be seen
`that an additional output line 86 terminates in AND
`circuit 100 which has additional input line 99. AND
`circuit 100 has an output line 101 which is connected
`to P counter 98. The output of AND circuit 96 is line
`97 which serves as an input to the P counter 98., Digital
`comparator 103 has an input 102 from P counter 98
`and an input 104 from thumb-wheel threshold 105.
`Digital comparator 103 has an output 106 connected to
`output line 107 which serves as one input to AND cir
`cuit 110, the other inputs being line 108 and line 109.
`The output 111 of AND circuit 110 serves' as the“
`clear” input of delay ?ip-?op 1 12.
`Referring back to .digital comparator 103, it can be
`seen that its output 106 also is connected to input line
`134 of inverter127 whose output line 128 is connected '
`to AND circuit 130'.‘ AND circuit 130 has additional in
`puts 129, 131 and 132, and has an output line 133 '
`which is a “clear” input to Q counter 115 which has an
`additional input 1 16.
`‘
`With reference to delay flip-?op 112, it is-apparent
`that the “clear” output line 1 14 terminates at AND cir
`cuit 119 which has another input line 117 which is an
`output of Q counter 115. AND circuit 119 has an out
`put line 118 that terminates in the output gate 120
`which has inputs ‘121 through 125 and output lines 126.
`FIG. 2 illustrates a typical display device 200 having
`a screen 197. Attached to screen 197 are transparent,
`conductive touchplates ~ 133 through 164. The
`touchplates are typically comprised of metal oxide, .
`well-known in the art and cemented to the face of the
`display device . with transparent cement, also well
`known. To each of the touchplates is connected a con
`ductor. For example, conductor 165 is connected to
`touchplate 133, conductor 180 is connected .to
`touchplate 148, conductor 181 is connected to
`touchplate 149, and conductor 196 is connected to
`touchplate 164. There is a conductor attached to each
`of the other touchplates which are not shown. Each
`conductor is connected to a separate oscillator. For ex
`ample, conductor 165 is connected to oscillator 1, con
`ductor 180 is connected to oscillator 32. Conductors
`165 through {196 are shown generally as entering chas
`sis 198- Chassis 198 contains printed circuit boards
`199, 201, 202 and 203. All of the oscillators and other
`components (not shown) are mounted on the printed
`circuit boards 199, 201, 202 and 203. The chassis 198
`need not be remote from the display device 200.
`FIG. 3 is the schematic diagram of oscillator 1 of
`FIG. 1. It is identical to the other 31 oscillators of the
`preferred embodiment. Except for the value of capaci
`tor 210 and the deletion of touchplate 133 and conduc
`tor 165, it is also identical to master clock 65 of FIG. 1.
`The transparent,gc0nductive touchplate 133 is con
`nected to the oscillator through conductor 165 at point
`A. Delaying capacitor 210 is connected through con
`ductor 211 to point A and from its other plate con
`nected to ground through conductor 212. Unijunction
`transistor 226 has its emitter connected through con—
`ductor 225 to paint A. Its base 2 is connected to a posi
`tive voltage source through conductor 222, conductor
`220, resistor 219, conductor 218, conductor 230 ‘and
`conductor 231. Its base 2 is also connected to coupling
`capacitor 224v through conductor 221. Its base 1 is con
`nected to ground through conductor 227, resistor 228
`and conductor 229. Variable resistor 216 is connected
`
`A simple inverter 206 whose input is D and whose
`outputis E is connected to the NAND circuit 205 in se
`ries. When D is “up”, E is “down’iand vice versa. Ex
`pressed mathematically in Boolean form:
`
`This is readily understood to be a design choice in
`the use of integrated circuits. FIG. 4 shows a simple
`AND circuit which is comprised of a NAND circuit,and
`an inverter. All of the AND circuits referred to herein
`are of similar con?guration.
`FIG. 5 is a logic diagram of a well-known counter,
`old in the art. Flip-?ops 309, 310, 311 and 312 have set
`inputs from circuits 301, 303, 305 and 307 respective
`ly. They have "‘clear” inputs from circuits 302, 304,
`306 and 308 respectively. This counter is indicated
`generally as A section 71 of FIG. 1. Outputs are in;
`dicated at 317, 318, 319 and 320 in ascending order.
`The ?ip-?ops are provided with force-set inputs in
`dicated as 313, 314, 315 and 316. The ?ip-?ops also
`have force-clear inputs indicated at 322,323, 324 and
`325. The input signal coming from AND circuit 67 of
`FIG. 1 enters through ampli?er 300.
`
`50
`
`55
`
`60
`
`65
`
` Exhibit 1012 Page 9
`
`

`
`3,696,409
`
`6
`output of the P counter 98 is run into a digital-to
`analog converter (not shown) and the pulse train from
`each of the eight pads shown scanned may then be
`viewed on an oscilloscope as an amplitude rather than a
`frequency. This is old in the art and is only for purposes
`of illustration.
`' FIG. 9A shows the resultant amplitude output of
`eight oscillators with
`no touchplate (referred to as “
`pa ” in this ?gure) being touched. FIG. 9B shows the
`pad for oscillator No. 4 being touched and its represen
`tation of frequency now as an amplitude is shown being
`quite low and below a threshold frequency set by the
`thumb-wheel threshold switches of thumb-wheel
`threshold 105.
`The delay ?ip-?op 112 of FIG. 1 is identical to the
`?ip-?op 333 of FIG. 6. It also is old in the art and need
`not be shown in detail. The Q counter 115 of FIG. 1 is
`made up of counters identical to the con?guration of
`the sequence counter 70 and therefore need not be
`described in detail.
`The output gate 120 of FIG. 1 is simply ?ve AND cir
`cuits which have been described in FIG. 4. Outputs 126
`of output gate 120 are available as inputs to any desired
`device. Typically, the application is to the buffer re
`gister of a digital computer. The output is of course not
`limited to such an application.
`
`20
`
`25
`
`MODE OF OPERATION .
`
`5
`FIG. 6 is a logic diagram showing the B section 90
`(FIG. 1) of the sequence counter 70. The lower four
`stages of the B section are con?gured exactly the same
`as the four stages of the A section 71 shown in detail in
`FIG. 5. The uppermost stage of the B section is com
`prised of AND circuit 330, whose inputs are the lower
`section outputs 326, 327, 328 and 329, and ?ip-?op
`333, whose inputs are AND circuit 331 and on the “
`set” side, AND circuit 332 on the “clear” side and ter
`minal 334 which conditions ?ip-?op 333. The set out
`put of ?ip-?op 333 is shown at terminal 335.,
`Referring now to FIG. 7, the select matrix 91 of FIG.
`1 is shown in logic form. Decoder 350 has as its inputs
`the highest order bit (B5) on line 72 and the next
`highest bit (B4) on line 73 and an “enable” on line 351
`which permits the decoder to operate when _t_he_ A __§ec
`ti_on of the sequence counter 70 of FIG. 1 is 0, l, 14 or
`15. Decoder 350 has four outputs, line 352 which is
`connected to multiplexer 356, line 353 which is con
`nected to multiplexer 357, line 354 which is connected
`to multiplexer 358, and line 355 which is connected to
`multiplexer 359. The three remaining lower order bits
`of the B section (B3, B2 and B1) are connected to each
`of the four multiplexers. The inputs are shown at lines
`74, 75 and 76 of multiplexer 356; lines 77, 78 and 79 of
`multiplexer 357; lines 80, 81 and 82 of multiplexer 358;
`lines 83, 84 and 85 of multiplexer 359. The output line
`from each of the oscillators 1 through 32 of FIG. 1 are
`shown as lines 33 through 64, eight being an input to
`each of the four multiplexers.
`Each of the multiplexers has an output through
`which the output of a selected oscillator passes. The
`operation will be described later. Multiplexer 356 has
`an output66, multiplexer 357 has an output 67, mul
`tiplexer 358 has an output 68 and multiplexer 359 has
`an output 69. The outputs are connected as the inputs
`to OR circuit 96 of FIG. 1 whose output is line 97. An
`OR circuit is. simply one that is responsive to any one of
`a multiplicity of inputs.
`The P counter 98 of FIG. 1 is made the of _a pair of
`counters in identical con?guration with the sequence
`counter 70 except that not as many counter stages are
`used. The operation will be fully described later.
`The thumb-wheel threshold 105 of FIG. 1 is a simple
`rotary thumb-wheel switch, old in the art. In the
`preferred embodiment, the thumb-wheel threshold 105
`has ?ve outputs each of which is adjustable to ground
`or an open circuit. Line 104 of FIG. 1 represents the
`five outputs of thumb-wheel threshold 105. In similar
`fashion, line 102 of FIG. 1 represents ?ve outputs from
`P counter 98.
`_ FIG. 8 is a detailed logic diagram of digital compara
`tor 103 of FIG. 1. It is well-known in the art and there
`55
`fore will not be described in detail. Its inputs from the P
`counter 98 are shown as P6, P5, P4, P3 and P2. The
`lowest stage of P is not used in this application. Its in
`puts from the thumb-wheel threshold 105 and shown as
`TW,, TW,, Twa, TWz and TW,. The stages are shown
`generally as 375, 374, 373, 372 and 371. In each stage
`the inputs are compared to each other and at the out
`put 370 it can be determined whether P is less than
`TW, whether P equals TW or whether P is greater than
`TW. In the preferred embodiment, only the output in
`dicated as P is greater than TW is used.
`FIG. 9 is of interest only as a graphic illustration of
`an analog representation of eight of the oscillators. The
`
`30
`
`FIG. 3 is a detailed schematic diagram of the oscilla
`tors 1 through 32 of FIG. 1 as well as master clock
`oscillator 65 of FIG. 1. As indicated earlier, the dif
`ference between the master clock oscillator 65 and all
`other oscillators 1 through 32 is that the capacitor 210
`is of a higher capacitance and-there is no touchplate
`133 or conductor 165. The relaxation oscillator here
`shown is of itself old in the art, particularly with
`reference to the master clock oscillator 65.
`Simply stated, in the case of the master clock oscilla
`tor 65, adjustable resistor 216, resistor 214 and capaci
`tor 210 form a charging path for capacitor 210. When
`capacitor 210 is charged ,to a critical value, the poten
`tial thereby appearing at paint A causes the unijunction
`
`transistor 226 to conduct providing a discharge
`path
`through the unijunction transistor 226, resistor 228,
`back to the other plate of capacitor 210. The discharge
`is rapid, dropping the potential at point A resulting in
`the cutoff of unijunction transistor 226. The charge
`cycle starts again, resulting in capacitor 210 again
`becoming charged to cause the conduction of unijunc
`tion transistor 226 permitting a discharge path through
`resistor 228. This is a typical relaxation oscillator. The
`charge and discharge of capacitor 210 results in the
`waveform of point A shown in FIG. 3A.
`The output of base 2 of unijunction transistor 226 is
`coupled to point B via capacitor 224 and is shown in
`FIG. 3B as it appears at point B of FIG. 3. That
`waveform is inverted and amplified in NPN transistor
`236. The output waveform is shown at FIG. 3C which is
`the collector output at point C of transistor 236. The
`diode 245 conducts when point C tends to go beyond
`+5 volts, resulting in a shaped waveform of FIG. 3C.
`The frequency of the pulsesof FIG. 3C may be varied
`by varying the charge path of capacitor 210 by chang
`ing the resistance of variable resistor 216.
`
`35
`
`40
`
`45
`
`50
`
`60
`
`65
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` Exhibit 1012 Page 10
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`

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`3,696,409
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`5
`
`20
`
`25
`
`7
`The oscillators 1 through 32 are each provided with a
`touchplate and a conductor as an input. In FIG. 3 the
`touchplate 133 is connected to the circuit through con
`ductor 165.
`It has been determined that the human body. is basi
`cally capacitive. The capacitance varies with the size of
`the body-but not signi?cantly. When a person touches
`touchplate 133, capacitance is added in parallel with
`capacitor 210. This added capacitance results in ‘a
`larger RC time constant in the charge path. A
`preselected frequency of output pulses as shown .in
`FIG. 3C is thereby‘ lowered with the addition of
`capacitance at touchplate 133. The operation as
`described above for the master clock oscillator 65 is
`identical to that of oscillators 1 through 32 except that
`the frequency is lowered by adding capacitance in the
`latter case. Recognizing the oscillator (and therefore
`the touchplate) and the fact that its frequency is
`lowered, is at the heart of this invention.
`Referring to FIG. 1, sequence counter 70, P counter
`98, and Q counter 115 are shown. In the preferred em
`bodiment, the A section 71 ‘of sequence counter 70 has
`four binary stages and the B section 90 of sequence
`counter 70 has ?ve binary stages. The P counter 98 has
`six binary stages and the Q counter 115 has nine binary
`stages. As is well-known in the art, each binary stage
`can be represented by two different voltage amplitudes.
`An arbitrary selection can be made assigning, for exam
`so
`ple, a “one” to a voltage and a “zero” to a ground
`potential. If all four stages are “one” the binary number
`represented is 1 ll 1, but for simplicity it will be
`referred to in its decimal equivalent as 15. Likewise the
`B section when ?lled is 31, the P counter when ?lled is
`35
`63 and the Q counter when ?lled is 1023. The Q
`counter 115 is ordinarily set at 1023 because its input
`1 l6 depends upon amtput from the master clock 65
`and the fact that Q=l023.
`'
`as shown in
`The master clock 65 produces pulses
`FIG. 3C in a manner described above at a rate of 4X103
`PPS in this preferred embodiment. These pulses are
`transmitted over output line 66 to ‘the AND circuit 68.
`AND circuit 68 is shown in FIG. 4 with the Boolean ex
`pressions set out above. When there is a pulse out of
`45
`master clock 65 on line 66 and when Q=l023 on line
`67 the output of the AND circuit 68 on line 69 is active
`only when both of such inputs are present. Determining
`that Q=l023 is simply done by appropriate AND cir
`cuits logically arrayed in
`one of a variety of possible
`con?gurations; well known in the prior art. Another
`output 86 of AND circuit 68 goes to AND circuit 100
`which has another input 99 requiring that A=0 in order
`for the output line 101 to be activated which is a “clear
`input” to P counter‘ 98.
`FIG. 5 shows the A section 71 of sequence counter
`70 in logic detail. The signal coming in on line 69 is am
`pli?ed through ampli?er 300 and sets the ?rst stage of
`the counter, de?ned as circuits 301 and 302,. to receive
`the inputs and ?ip-?op 309 whose output “A,” is
`shown at 317. The reception of another pulse through
`ampli?er 300 toggles the ?rst stage and sets the second
`stage whose output “A2” is shown at 318. Another
`input pulse sets the ?rst stage so that output A; is again
`A,. Another pulse toggles the ?rst and second stage and
`sets the third stage whose “one output” at “A3” is
`shown at 319. In like manner the stages are toggled
`
`40
`
`8
`back and forth until all four are “l’s”. When A=l5
`(?lled) line 72 is activated. AND circuit 73 receives an
`input from AND circuit 68 anda signal that the digital
`comparator 103 is “high” as shown on line 88. This will
`be explained later. Assuming that line 88 has a signal
`present and assuming that line 87 has a clock pulse,
`then AND circuit 73 passes a pulse on line 89 to the B
`section 90 of sequence counter 70. This is merely an
`extension of the A section 71.
`>
`The B section 90 is shown is greater detail in FIG. 6.
`The four lower order bits of the Bsection are identical
`to the con?guration of the A section 71 of FIG. 5 and
`need not be shown. A ?fth stage is supplied by a ?ip
`?op 333. The ?ip-?op 333 is well-known inthe prior
`art. It is conditioned at terminal 334 from line 336
`when the lower four stages of the B section 90 are ?lled
`(IS-=15), then the four inputs to AND circuit 330 are
`activated and the last stage 333 is toggled to a “1”
`state.
`However, prior to the toggling of any of the stages in
`the B section 90, when B=0, output lines 74 through 85
`convey that fact to select matrix 91.
`Select matrix 91 is shown in logical detail in FIG. 7.
`Decoder 350 is a device well-known in
`the prior art
`which simply provides the fourpossible combinations
`for two binary signals. When B=0, then B5 on input line
`72 equals 0 and B4 on input line 73 equals 0. The four
`possible outputs are B5B.” B5B}, B5B, and
`With
`B5=0 and B4=0 then line 355 is activated as an enable
`input to multiplexer 359. Multiplexer 359 has inputs
`B3, B2 and B1 on input lines 83, 84 and 85 respectively.
`- The multiplexer 359 is a device well known in the prior
`art which takes three ‘control inputs and combines
`those three inputs in the eight possible gating combina
`tions to gate as an output one of the eight inputs. Addi
`tionally, the enable input on line 355 is also placed on
`all eight outputs 57 through 64. The eight possible
`combinations of B1, B2 and B3 are as follows:
`
`When B=0 output 64 carrying the function B5B,~
`Ba'BgBfiS activated. This permits the oscillator con
`nected to line 64 to send its pulses through the mul
`tiplexer and on line 69 to OR circuit 96, out on line 97.
`The selection of line 64 has been shown for illustrative
`purposes. Multiplexers 356 through 359 operate in
`identical fashion on each of the eight inputlines except
`that the conditioning signals from decoder 350 are dif
`ferent. In each case, one line of any one multiplexer
`can be selected thereby selecting a specific oscillator.
`Referring to FIG. 1, P counter 98 accepts the pulses
`from the selected oscillator from line 97 to P counter’
`and begins counting the pulses from the selected oscil
`lator. The time period during which the pulses are
`counted is measured by the counting of the clock pul
`ses by the A section 71.
`7
`It hasbeen determined that approximately 60 pulses
`counted in the P curve 98 (high count capacity. = 63) is
`very workable in the preferred embodiment. The
`master clock 65 operates at 4X10a PPS those pulses
`being transmitted into the A section 71. However, vari
`ous counts of A are not available for measuring the
`
`55
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`65
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` Exhibit 1012 Page 11
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`3,696,409
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`9
`time of counting in the P counter 98. When A=0, the P
`counter 98 is cleared. When A=l4, the output of digital
`comparator 103 is gated out at AND circuit 110 and
`AND circuit 130. When A=l5, AND circuit 73 is ena
`bled, permitting a pulse to go through line 89 into the B
`section 90. Therefore, the time period measured by the
`A section 71 is from A=2 to A=l 3, a count of 12 clock
`pulses.
`
`Where
`T= period
`F = frequency
`
`Total time (l2 pulses)
`Total time
`Total time
`
`15
`
`Since 60 pulses is a good number for counting in the
`P counter, a minimum frequency is required to provide
`at least 60 pulses within the count period time of 3X10‘
`3 seconds. The period (T) of one of 60 pulses equals the
`total time available divided by the number of pulses;
`therefore:
`
`20
`
`25
`
`The oscillators must be able to provide a minimum of
`20,000 pulses per second to meetthe design require
`
`30
`
`35
`
`40
`
`45
`
`10
`In the preferred embodiment, only the P>TW output
`is used. That is, when the count of the P counter, when
`A=l4, is greater than the count of the thumb-wheel
`threshold 105, line 106 has a positive pulse present. As
`suming that the selected oscillator had not been
`touched and its frequency remained therefore at
`20><l03 PPS, 60 pulses would have been counted in the
`prescribed time in the P counter, such a count being
`higher than the thumb-wheel threshold 105 setting of
`40 resulting in a “comparator high” signal out on line
`106. This condition would result in a signal present on
`line 107 to AND gate 110 enabled by the master clock
`at 109 and by A=l4 at 108. The output of AND circuit
`110 is 111 and is a “clear” input to delay ?ip-?op 1 12
`resulting in a “clear” output on line 114 into AND cir
`cuit 119.
`Referring again to output 106 of digital comparator
`103, when the comparator is “high”, a signal is
`presented through line 134 to inverter 127 which then
`presents a ground level to line 128 which does not per
`mit enabling of AND circuit 130 and ' therefore Q
`counter 1 15 is not “clear" but remains at a count 1023.
`The output 117 of 0 counter 115 is enabled only when
`Q=m and therefore is not enabled in this situation.
`Therefore AND circuit 1 19 does not present a signal to
`output gate 120 over line 118. As a result, there are no
`output signals permitted through the output lines 126.
`Now assume a person