Paper No. _______
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`
`SK hynix Inc., SK hynix America Inc., SK hynix memory solutions Inc., and
`Hynix Semiconductor Manufacturing America Inc.
`Petitioners,
`v.
`
`DSS Technology Management, Inc.
`Patent Owner.
`
`Patent No. 6,784,552
`Issued: August 31, 2004
`Filed: March 31, 2000
`Inventors: James E. Nulty, Christopher J. Petti
`Title: STRUCTURE HAVING REDUCED LATERAL SPACER
`EROSION
`______________________
`
`
`
`Inter Partes Review No. ______
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`

`
`TABLE OF CONTENTS
`
`
`Page
`
`I. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(a)(1) .......................... 1
`A.
`Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1) ............................ 1
`B.
`Related Matters Under 37 C.F.R. § 42.8(b)(2) ..................................... 2
`C.
`Lead and Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) and
`Service Information Under 37 C.F.R. § 42.8(b)(4) ............................... 3
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.15 ......................................... 3
`II.
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ............................ 3
`A. Grounds for Standing Under 37 C.F.R. § 42.104(a) ............................. 3
`B.
`Identification of Challenge Under 37 C.F.R. § 42.104(b) and
`Relief Requested .................................................................................... 4
`IV. CLAIM CONSTRUCTION UNDER 37 C.F.R. § 42.104(B)(3) .................... 5
`A.
`Insulating spacer in the contact region (claims 1, 4, 5)/insulative
`spacer in the contact opening (claims 8-10) .......................................... 6
`Etch stop material (claims 1-5, 8-10) .................................................... 8
`Etch stop material over said first insulating layer and adjacent
`to the insulating spacer (claim 1) .......................................................... 9
`SUMMARY OF THE ʼ552 PATENT ........................................................... 10
`A. Description of the Alleged Invention .................................................. 10
`B.
`Summary of the File History ............................................................... 11
`VI. AT LEAST ONE CLAIM OF THE ʼ552 PATENT IS
`UNPATENTABLE ........................................................................................ 13
`A. GROUND 1 – Claims 1-12 are anticipated by Havemann under
`35 U.S.C. § 102 ................................................................................... 14
`1.
`Overview of Havemann ............................................................ 14
`B. GROUND 2 – Claims 1, 2, 4-10 are anticipated by Heath under
`35 U.S.C. § 102 ................................................................................... 34
`1.
`Overview of Heath .................................................................... 34
`C. GROUND 3 – Claim 3 is unpatentable over Heath in view of
`Havemann under 35 U.S.C. § 103 ....................................................... 49
`
`B.
`C.
`
`V.
`
`
`
`i
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`

`
`D. GROUND 4 – Claims 1, 4, and 5 are anticipated by the APA
`D.
`GROUND 4 — Claims 1, 4, and 5 are anticipated by the APA
`of the ʼ552 Patent under 35 U.S.C. § 102 ........................................... 53
`ofthe ’552 Patent under 35 U.S.C. § 102 ......................................... ..53
`1.
`Overview of the APA ................................................................ 53
`VII. REDUNDANCY ........................................................................................... 58
`VIII. CONCLUSION .............................................................................................. 58
`
`
`1.
`
`Overview of the APA .............................................................. ..53
`
`VII. REDUNDANCY ......................................................................................... ..58
`
`VIII. CONCLUSION ............................................................................................ ..5 8
`
`
`
`ii
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`

`
`EXHIBITS
`
`HYNIX-1001 - U.S. Patent No. 6,784,552 to Nulty et al., filed Mar. 31, 2000
`
`HYNIX-1002 - DSS Technology Management Inc. v. SK Hynix, Inc. et al., Case
`
`No. 6:15-cv-00691, Plaintiff’s Original Complaint for Patent Infringement (July
`
`16, 2015)
`
`HYNIX-1003 – Declaration of Dr. Vivek Subramanian
`
`HYNIX-1004 - U.S. Patent No. 5,482,894 to Havemann, filed Aug. 23, 1994
`
`HYNIX-1005 - U.S. Patent No. 4,686,000 to Heath, filed Feb. 19, 1986
`
`HYNIX-1006 – Prosecution History of U.S. Patent No. 6,784,552 to Nulty et al.,
`
`filed Mar. 31, 2000
`
`HYNIX-1007 - Gary W. Jones and Sanjay Tandon, Multilevel Metal
`
`Interconnection Utilizing CVD Tungsten and Liftoff Processing, 29 Journal of
`
`Electronic Materials (1990)
`
`HYNIX-1008 – Claim Chart A (cited in Declaration of Dr. Vivek Subramanian)
`
`HYNIX-1009 – Claim Chart B (cited in Declaration of Dr. Vivek Subramanian)
`
`HYNIX-1010 – Claim Chart C (cited in Declaration of Dr. Vivek Subramanian)
`
`HYNIX-1011 – Claim Chart D (cited in Declaration of Dr. Vivek Subramanian)
`
`
`
`iii
`
`

`
`
`
`SK hynix Inc.; SK hynix America Inc.; SK hynix memory solutions Inc.;
`
`and Hynix Semiconductor Manufacturing America Inc., (collectively, “Petitioner”
`
`or “Hynix”) respectfully petitions for Inter Partes Review (“IPR”) under 35 U.S.C.
`
`§§ 311–319 and 37 C.F.R. § 42 of claims 1-12 (the “Challenged Claims”) of U.S.
`
`Patent No. 6,784,552 (the “’552 Patent”) (Ex. HYNIX-1001), of apparent assignee
`
`DSS Technology Management, Inc. (“Patentee” or “DSS”). As explained in this
`
`Petition, there exists a reasonable likelihood that Hynix will prevail with respect to
`
`at least one of the Challenged Claims.
`
`I. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1)
`A. Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1)
`The real parties of interest of this petition are: SK hynix Inc. with its
`
`
`
`principal place of business and home office at 2091, Gyeongchung-daero, bubal-
`
`eub, Icheon-si, Gyeonggi-do, South Korea; SK hynix America Inc. with its
`
`principal place of business at 3101 North First Street, San Jose, CA 95134; SK
`
`hynix memory solutions Inc. with its principal place of business at 3103 North
`
`First Street, San Jose, CA 95134; and Hynix Semiconductor Manufacturing
`
`America Inc. with its principal place of business at 1830 Willow Creek Circle,
`
`Eugene, Oregon 97402.
`
`
`
`1
`
`

`
`B. Related Matters Under 37 C.F.R. § 42.8(b)(2)
`Hynix is not aware of any terminal disclaimers for the ’552 Patent. The ’552
`
`
`
`Patent has been involved in at least five litigations1; one naming Hynix as a
`
`defendant: The following judicial matters may affect or be affected by a decision in
`
`this proceeding: DSS Tech. Mgmt., Inc. v. SK Hynix, Inc., et al., Case No. 6:15-cv-
`
`691 (hereinafter, “the Hynix Litigation”) in the U.S. District Court for the Eastern
`
`District of Texas, filed on July 16, 2015, currently pending; DSS Tech. Mgmt., Inc.
`
`v. Samsung Elec. Co., Ltd. et al., Case No. 6:15-cv-690 in the U.S. District Court
`
`for the Eastern District of Texas, filed on July 16, 2015, currently pending; DSS
`
`Tech. Mgmt., Inc. v. Qualcomm, Inc., Case No. 6:15-cv-692 in the U.S. District
`
`Court for the Eastern District of Texas, filed on July 16, 2015, currently pending;
`
`and DSS Tech. Mgmt., Inc. v. Intel, Corp. et al., Case No. 6:15-cv-130 in the U.S.
`
`District Court for the Eastern District of Texas, filed on February 16, 2015,
`
`currently pending.
`
`
`1 One of the five litigations includes Avago Tech. U.S., Inc. et al v. Cypress
`
`Semiconductor Corp., et al., Case No. 1:11-cv-00071 in the U.S. District Court for
`
`the District of Delaware, filed on January 21, 2011, which was dismissed by
`
`stipulation.
`
`
`
`2
`
`

`
`C. Lead and Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) and
`Service Information Under 37 C.F.R. § 42.8(b)(4)
`
`
`
`Petitioner designates Heath J. Briggs, Reg. No. 54,919, as Lead Counsel and
`
`Patrick J. McCarthy, Reg. No. 62,762, as Backup Counsel. Mr. Briggs is available
`
`for service at Greenberg Traurig, LLP, 1200 17th Street, Suite 2400, Denver,
`
`Colorado 80202 (T: 303-572-6500). Mr. McCarthy is available for service at
`
`Greenberg Traurig, LLP, 2101 L Street NW, Washington, D.C. 20037 (T: 202-
`
`331-3100). Mr. Briggs and Mr. McCarthy are available for electronic service by
`
`email at HynixGTIPR@gtlaw.com.
`
`II.
`
`
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.15
`
`Petitioner authorizes the U.S. Patent & Trademark Office to charge Deposit
`
`Account No. 50-2775 for the fee set in 37 C.F.R. § 42.15(a) for this Petition and
`
`further authorizes for any additional fees to be charged to this Deposit Account.
`
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`A. Grounds for Standing Under 37 C.F.R. § 42.104(a)
`Hynix certifies that the ’552 Patent is available for IPR. Hynix also certifies
`
`
`
`that it is not barred or estopped from requesting an IPR challenging the ’552 Patent
`
`claims on the grounds identified in this petition. The present petition is being filed
`
`within one year of when Hynix was served with the Complaint in the co-pending
`
`Hynix Litigation. See Ex. HYNIX-1002.
`
`
`
`3
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`

`
`B.
`
`Identification of Challenge Under 37 C.F.R. § 42.104(b) and Relief
`Requested
`
`
`
`Hynix requests IPR of the Challenged Claims of the ’552 Patent on the
`
`grounds set forth in the table below, and requests that each of the claims be found
`
`unpatentable. An explanation of how these claims are unpatentable under the
`
`statutory grounds identified below, including an identification of where each
`
`element is found in the prior art Patents and/or printed publications and the
`
`relevance of each prior art reference, is provided in the detailed description that
`
`follows. Citations in support of each ground are to the declaration of Dr. Vivek
`
`Subramanian, Ex. HYNIX-1003 (“Subramanian Decl.”).
`
` Ground of
`Unpatentability
`
`ʼ552 Patent
`Claim(s)
`
` Ground 1
`
`1-12
`
`Ground 2
`
`Ground 3
`
`Ground 4
`
`1, 2, 4-10
`
`3
`
`1, 4, 5
`
`Basis for Rejection
`Anticipated by U.S. Patent No.
`5,482,894 to Havemann
`(“Havemann”) under 35 U.S.C. §
`102
`Anticipated by U.S. Patent No.
`4,686,000 to Heath (“Heath”)
`under 35 U.S.C. § 102
`Obvious over Heath in view of
`Havemann under 35 U.S.C. § 103
`Anticipated by the Admitted Prior
`Art of the ʼ552 Patent (“APA”)
`under 35 U.S.C. § 102
`
`
`
`
`
`The ’552 Patent issued on August 31, 2004, from Application No.
`
`09/540,610 filed on March 31, 2000. The ’552 Patent claims priority as a
`
`divisional to Application No. 08/577,751, now U.S. Patent No. 6,066,555, filed on
`
`
`
`4
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`

`
`December 22, 1995. Thus, the earliest priority date of the ʼ552 Patent appears to
`
`be December 22, 1995 (“the Priority Date”).
`
`
`
`Havemann (U.S. Patent No. 5,482,894, Ex. HYNIX-1004) qualifies as prior
`
`art at least under pre-AIA 35 U.S.C. § 102(e). Havemann issued from a U.S.
`
`application filed on August 23, 1994, which predates the Priority Date of the ʼ552
`
`Patent, and is therefore prior art at least under pre-AIA 35 U.S.C. § 102(e).
`
`
`
`Heath (U.S. Patent No. 4,686,000, Ex. HYNIX-1005) qualifies as prior art at
`
`least under 35 U.S.C. § 102(b). Heath issued on August 11, 1987, more than one
`
`year before the Priority Date, and thus is prior art at least under 35 U.S.C. § 102(b).
`
`
`
`At least Figures 1(A)-1(C), 2(A)-2(B) and 3 and the description at column 1,
`
`line 14 to column 6, line 65 of the ʼ552 Patent are admitted prior art (“the
`
`Admitted Prior Art”, or “APA”) because the ʼ552 Patent acknowledges these
`
`disclosures as being prior art. Application of Nomiya, 509 F.2d 566, 570-571
`
`(C.C.P.A. 1975).
`
`IV. CLAIM CONSTRUCTION UNDER 37 C.F.R. § 42.104(B)(3)
`
`The ’552 Patent will expire on December 22, 2015. The Board’s review of
`
`the claims of an expired patent is similar to that of a district court’s review. In re
`
`Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012); see also IPR2015-00633, Decision
`
`Instituting Inter Partes Review, paper 11 at 9 (citing to In re Rambus, Inc., 694
`
`F.3d 42, 46 for the proposition that “the Board’s review of the claims of an expired
`
`
`
`5
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`

`
`patent is similar to that of a district court’s review.”). Because the ’552 Patent will
`
`expire shortly, Hynix has analyzed the claims under Phillips v. AWH Corp., 415
`
`F.3d 1303, 1312, 1327 (Fed. Cir. 2005), consistent with a district court’s
`
`review. See also IPR2015-00633, Decision Instituting Inter Partes Review, paper
`
`11 at 9 (stating that because the patent is set to expire before the Board will issue a
`
`final written decision, the Board will construe the claims of the patent under the
`
`standard set forth in Phillips.) Under Phillips, the words of a claim “are generally
`
`given their ordinary and customary meaning” as understood by a person of
`
`ordinary skill in the art in question at the time of the invention. Id.
`
`
`
`The following claim terms should be construed as set forth below. Hynix
`
`understands that these terms are proposed consistently with their plain and ordinary
`
`meaning and the rest of the claim terms also should take on their plain meaning.
`
`A.
`
`Insulating spacer in the contact region (claims 1, 4, 5)/insulative
`spacer in the contact opening (claims 8-10)
`
`
`
`Claims 1, 4, and 5 recite an “insulating spacer.” Claims 8-10 similarly recite
`
`an “insulative spacer.” These two terms are used interchangeably and Petitioner
`
`understands they should be interpreted the same way. Petitioner proposes that
`
`these terms be construed as “electrically insulating material next to a conductive
`
`portion and within the contact region/opening.”
`
`
`
`The idea of insulating spacers is discussed at length in the background of the
`
`invention. Particularly, the ʼ552 Patent teaches “Contact structures can be inserted
`6
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`

`
`to the source/drain regions and interlays can overlie the contact structures and
`
`connect neighboring contact structures. These contact structures to the diffusion
`
`region are isolated from the adjacent gate by dielectric spacer or shoulder
`
`portions.” Ex. HYNIX-1001 (“’552 Patent”) at 3:21-25. In other words, the
`
`Patent admits that the prior art includes substrates with contact regions for
`
`transistor electrodes and insulator spacing material is laterally placed in those
`
`contact regions. Ex. HYNIX-1001 (ʼ552 Patent) at Title, Abstract, and 7:16-
`
`18. An example of the disclosed prior art insulating spacer 235 with respect to a
`
`contact region in blue is shown below in annotated figure 2(A). Ex. HYNIX-1001
`
`at 4:38-43.
`
`As shown in the cross-sectional view above, the
`
`insulating spacer is electrically insulating material
`
`next to a conductive portion and within the contact
`
`region. The detailed description of the invention
`
`confirms this understanding. For example, with
`
`respect to the preferred embodiment of Figure 4, the
`
`Applicants explained that “The spacer portions 435 of the TEOS layer 430 are
`
`demarked by ghost lines in FIG. 4(D). The spacers 435 serve to insulate the
`
`polysilicon layers 415 from the conducting material that will fill the contact
`
`openings and prevent the gates from overlapping the diffusion regions 405.” Ex.
`
`
`
`7
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`

`
`HYNIX-1001 at 11:40-44. By viewing Figure 4(C) aligned on top of Figure 4(D),
`
`the spacer portions 435 of the TEOS layer 430 are seen.
`
`A person of ordinary skill in the art
`
`would also understand insulating
`
`spacer and insulative spacer to mean
`
`“electrically insulating material next to
`
`a conductive portion and within the
`
`contact region/opening.” Ex. HYNIX-
`
`1003 (“Subramanian Decl.”) at p. 20,
`
`n.1.
`
`
`
`Etch stop material (claims 1-5, 8-10)
`
`B.
`Claims 1-5, 8-10 all recite an “etch stop material.” Hynix understands this
`
`claim term to be “etch resistant material applied to permit subsequent etching of
`
`the substrate without risk of exposing the device structures and layers.” Hynix’s
`
`understanding comes directly from the specification. Ex. HYNIX-1001 at 4:13-
`
`18. Particularly, the specification explains that “A distinct dielectric etch stop
`
`layer 125 overlies the encapsulating dielectric layer 120. The etch stop layer 125
`
`permits subsequent etching of the substrate without risk of exposing the device
`
`structures and layers because the device structuring and layers are protected from
`
`excessive etching by the etch stop layer 125.” Id. (emphasis added). A person of
`
`
`
`8
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`

`
`ordinary skill in the art would also understand etch stop layer to mean “etch
`
`resistant material applied to permit subsequent etching to the substrate without risk
`
`of exposing the device structures and layers.” Ex. HYNIX-1003 (“Subramanian
`
`Decl.”) at p. 23 n.2.
`
`C. Etch stop material over said first insulating layer and adjacent to
`the insulating spacer (claim 1)
`
`
`
`Independent claim 1 recites an “etch stop material over said first insulating
`
`layer and adjacent to the insulating spacer.” Petitioner proposes that this phrase
`
`means “etch stop material (as construed) over at least a portion of an electrically
`
`insulating layer and next to at least a portion of the insulating spacer (as
`
`defined).” As shown in Figure 4(K), the etch stop material 440 is over the
`
`insulating layer 420.
`
`Etch stop of the same material is also next
`
`to the insulating spacer, which is demarked
`
`as region 435 in Figure 4(D) above and
`
`colored in yellow in Figure 4(L) below.
`
`
`
`9
`
`
`
`

`
`
`A person of ordinary skill in the art would also understand etch stop material over
`
`said first insulating layer and adjacent to the insulating spacer to mean “etch-
`
`resistant material applied before etching and over at least a portion of an
`
`electrically insulating layer and next to at least a portion of the insulating spacer
`
`(as defined).” Ex. HYNIX-1003 (“Subramanian Decl.”) at p. 23, n.2.
`
`V.
`
`
`
`SUMMARY OF THE ʼ552 PATENT
`A. Description of the Alleged Invention
`The ʼ552 Patent is directed to a semiconductor device with purported
`
`reduced lateral spacer erosion. Ex. HYNIX-1001, Abstract. Figure 4(L) of the
`
`ʼ552 Patent, reproduced below with highlighted sections, illustrates a cross-
`
`sectional planar side view of the disclosed semiconductor device:
`
`
`
`10
`
`

`
`
`
`
`
`As illustrated in Figure 4(L), the semiconductor device includes insulating
`
`spacers in yellow having a side with an angle relative to the substrate surface that
`
`is between 85 and 90 degrees. An etch stop layer with etch resistant properties is
`
`highlighted in red. There is also disclosed an insulating layer in orange which
`
`insulates the conducting layer 415. Ex. HYNIX-1001, 10:31-65; 11:63 – 12:20.
`
`Shown in blue is a transistor contact point which is within what the ʼ552 Patent
`
`calls a contact region or contact opening. Ex. HYNIX-1001, 13:43-45. As shown,
`
`the etch stop materials are etched away from the bottom of the contact opening and
`
`allow electrical contact with the conductive region, such as a source or drain 445.
`
`Ex. HYNIX-1001, 12:48-52. Independent claims 1 and 8 of the ʼ552 Patent recite
`
`the basic structure of the semiconductor device described above.
`
`Summary of the File History
`
`B.
`In the first Office Action, the Examiner rejected all but one of the submitted
`
`
`
`claims as anticipated by U.S. Patent No. 5,338,700 to Dennison (“Dennison”)
`
`under 35 U.S.C. § 102(b). Ex. HYNIX-1006 at 80. The remaining claim was
`
`
`
`11
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`

`
`rejected by the Examiner as being obvious by Dennison in view of U.S. Patent No.
`
`5,234,856 to Gonzalez (“Gonzalez”). Ex. HYNIX-1006 at 82. The Applicants
`
`submitted that the “claimed invention includes an etch stop material that is distinct
`
`from the insulating spacer” and that the combination of Dennison with Gonzalez
`
`does not disclose this feature. Id.
`
`
`
`The Examiner maintained his initial rejections in the second Office Action
`
`and the Applicants amended the claims to explicitly recite “the etch stop material
`
`being a different material from the insulating spacer.” Ex. HYNIX-1006 at 154,
`
`166. The amendment did not result in patentability. In the third Office Action,
`
`the Examiner applied a new reference, U.S. Patent No. 5,488,011 to Figura et al.
`
`(“Figura”), in combination with Dennison and Gonzalez for disclosing an etch stop
`
`material that is a different material from the insulating spacer. Ex. HYNIX-1006 at
`
`182. The Applicants attempted to traverse the rejection through argument only,
`
`alleging that the silicon oxide of Figura was an ineffective etch stop. Ex. HYNIX-
`
`1006 at 192. The Applicants were unsuccessful.
`
`
`
`In a fourth Office Action, the examiner explained that the Applicants’
`
`arguments were unpersuasive and, particularly, that silicon oxide could act as an
`
`etch stop material. Ex. HYNIX-1006 at 200. In response, the Applicants filed a
`
`Notice of Appeal and amended the claims to explicitly recite that the insulated
`
`spacer is “substantially rectangular.” Ex. HYNIX-1006 at 224, 230. To support
`
`
`
`12
`
`

`
`alleged patentability, the Applicants alleged that in the prior art “the properties of a
`
`highly selective etch of the overlying etch layer can transform a substantially
`
`rectangular spacer adjacent to the contact region into a sloped spacer.” Ex.
`
`HYNIX-1006 at 222. There was a follow-up amendment to clarify that
`
`“substantially rectangular” meant either a right angle or an acute angle of more
`
`than 85 degrees. After this amendment, the Examiner issued a Notice of
`
`Allowance. Ex. HYNIX-1006 at 242.
`
`VI. AT LEAST ONE CLAIM OF THE ʼ552 PATENT IS
`UNPATENTABLE
`
`
`
`The references presented in this Section demonstrate that the limitations of
`
`claims 1-12 were known in the art and therefore establish a reasonable likelihood
`
`that claims 1-12 are unpatentable.
`
`
`
`As more fully described below, the references disclose insulating spacers
`
`having a side with an angle relative to the substrate surface that is either a right
`
`angle or an acute angle of more than 85 degrees—the key limitation the Applicants
`
`used to purportedly overcome the prior art. Additionally, each of these references
`
`have etch stop material that is a different material than the insulating spacer—
`
`another key limitation the Applicants relied on during prosecution. Arguably both
`
`of these key limitations were well known in the art by 1995, but, nevertheless, they
`
`are clearly disclosed by the cited art in this Petition.
`
`
`
`13
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`

`
`A. GROUND 1 – Claims 1-12 are anticipated by Havemann under 35
`U.S.C. § 102
`1. Overview of Havemann
`Havemann describes a semiconductor device incorporating “organic
`
`
`
`dielectric materials to form self-aligned contacts (SACTs)” in deep, narrow gaps.
`
`Ex. HYNIX-1004, Abstract. As explained in the ’552 Patent, it too is particularly
`
`directed to self-aligned contacts: “The structure contemplated by the invention is
`
`an effective device for small feature size structures, particularly self-aligned
`
`contacts.” Ex. HYNIX-1001 at 8:4-6. Figure 2D of Havemann illustrates an
`
`embodiment of its self-aligned contact:
`
`Figure 2D is annotated below.
`
`Figure 2D shows conductors
`
`26 (purple) with insulating
`
`conductor caps 28 (orange)
`
`formed over a silicon substrate 20 (green). Ex. HYNIX-1004, Abstract. A
`
`conformal dielectric layer 30 shown in yellow is formed as shown. Ex. HYNIX-
`
`1004, Abstract. An insulating layer 32 shown in lime green is also deposited. Ex.
`
`HYNIX-1004, Abstract. As shown in red (42), a conformal overlayer is taught.
`
`Havemann discloses that the conformal layer in red is a nitride, whereas the
`
`underlying dielectric insulator shown in yellow is an oxide: “If conformal layer 30
`
`and overlayer 42 differ in materials (e.g., thermal oxide and nitride), relative
`
`
`
`14
`
`

`
`selectivity between the two materials may also be exploited to design a structure
`
`wherein conductor caps 28 are extremely thin.” Ex. HYNIX-1004 at 5:27-31; Ex.
`
`HYNIX-1003 (“Subramanian Decl.”) at ¶ 38. Havemann discloses that the gap 43
`
`can be used for a “contact plug” to make electrical connection with the substrate.
`
`Ex. HYNIX-1004, at 4:62-5:1; Ex. HYNIX-1003 (“Subramanian Decl.”) at ¶ 38.
`
`This optional contact plug is shown in blue.
`
`Also shown below is colored figure 4(L) from the ’552 Patent—the two are
`
`strikingly similar.
`
`Claim 1
`
`[1.0] “A structure, comprising”
`
`
`
`Havemann discloses “a structure for self-aligned contacts on semiconductor
`
`devices.” (emphasis added). Ex. HYNIX-1004, 2:10-11. As explained above, the
`
`’552 Patent is also directed to self-aligned contacts in semiconductor devices. Ex.
`
`HYNIX-1001, Abstract, 8:4-6.
`
`[1.1] “(a) a conductive layer disposed over a substrate;”
`
`
`
`Havemann discloses a SACT embodiment with “[c]onformal dielectric 30
`
`deposited on the sidewalls of conductors 26….” (emphasis added). Ex. HYNIX-
`
`
`
`15
`
`

`
`1004, 5:10-11. Figure 2D of Havemann illustrates the conductors 26, in purple, as
`
`a conductive layer disposed over a substrate 20 shown in green:
`
`
`Thus, Havemann discloses the claim
`
`limitations recited in [1.1].
`
`[1.2] “(b) a first insulating layer
`on the conductive layer;”
`
`Havemann discloses a structure that includes insulating conductor caps 28.
`
`
`
`(emphasis added). Ex. HYNIX-1004, 3:62-65. The insulating conductor caps 28
`
`on the conductive layer 26 are illustrated in Figure 2D below in orange:
`
`
`As shown in the table at column 6
`
`line 5 in the Havemann patent, the
`
`preferred material for these
`
`insulating caps is CVD oxide,
`
`which is explicitly listed as an alternative material. This aligns with the ’552
`
`Patent’s disclosure that the insulating layer is made up of a TEOS oxide, which is a
`
`type of CVD oxide. Ex. HYNIX-1004, 10:64-65; Ex. HYNIX-1003
`
`(“Subramanian Decl.”) at ¶ 43.
`
`
`
`16
`
`

`
`
`Thus, Havemann discloses the claim limitations recited in [1.2].
`
`
`
`[1.3] “(c) a contact region in said first insulating layer;”
`
`
`
`Havemann discloses that “preferably a short anisotropic etch of the
`
`conformal layer follows these steps if contact is to be made to the substrate in the
`
`gap (which may then be followed by a deposition of conducting material in the gap
`
`to form an electrical contact to the substrate).” Ex. HYNIX-1004, 2:62-66. The
`
`contact region identified in Figure 2D below is an example of a gap between the
`
`first insulating layers 28. Ex. HYNIX-1003 (“Subramanian Decl.”) at ¶ 44.
`
`In fact, Havemann discloses
`
`“contact plug 40, formed of a
`
`conducting material (e.g. a
`
`composite comprised of a
`
`refractory metal underlayer with
`
`a tungsten overlayer) may be deposited in cap window 39 and contact window 41
`
`
`
`17
`
`

`
`(which includes the portion of insulated gap 29 underlying window 39) to form a
`
`contact to the substrate at gap bottom 43.” Ex. HYNIX-1004, 4:63-5:1. Thus,
`
`Havemann discloses the claim limitations recited in [1.3].
`
`[1.4] “(d) at least one insulating spacer in the contact region adjacent to the
`
`first insulating layer; and”
`
`
`
`As shown in the table at column 6, line 16 (pictured above), Havemann
`
`discloses a conformal layer 30 made of a material, such as CVD oxide. (emphasis
`
`added). Ex. HYNIX-1004, 6:16.
`
`As explained in the ’552 Patent, oxide layers (e.g., TEOS oxide layers) are
`
`insulators. Ex. HYNIX-1001, 2:14-17. The conformal layer 30, shown in yellow
`
`below (annotated Figure 2D) is electrically insulating material next to a conductive
`
`portion and within the contact region/opening:
`
`As illustrated in Figure 2D, the
`
`conformal layer 30 is adjacent to
`
`the insulating conductor caps 28
`
`(i.e., the first insulating layer).
`
`Ex. HYNIX-1004, Figure 2D; Ex.
`
`HYNIX-1003 (“Subramanian Decl.”) at ¶ 45. Notably, in the table in column 6,
`
`the insulating spacers 30 are disclosed as the same material as insulating layer
`
`28—CVD oxide. Likewise, in the ’552 Patent, the insulating spacers and the first
`
`insulating layer are both TEOS oxides, which is a type of CVD oxide. Ex.
`18
`
`
`
`

`
`HYNIX-1001, 11:41-42. In fact, the only thing that distinguishes the insulating
`
`layer and the insulating spacers in the ’552 Patent is that the spacers are
`
`distinguished by “ghost lines.” Id. Thus, Havemann discloses the claim limitations
`
`recited in [1.4].
`
`[1.5] “(e) an etch stop material over said first insulating layer and adjacent
`
`to the insulating spacer, the etch stop material being a different material
`
`from the insulating spacer,”
`
`Havemann discloses that “[a]dditional material may subsequently be
`
`
`
`deposited as a conformal dielectric overlayer 42, e.g., using thermal oxide or
`
`silicon nitride (see FIG. 2C).” (emphasis added). Ex. HYNIX-1004, 5:16-18. The
`
`’552 Patent explains that silicon nitride is a known etch stop. Ex. HYNIX-1001,
`
`4:42-44. This is also disclosed in Havemann, which says “[i]f conformal layer 30
`
`and overlayer 42 differ in materials (e.g., thermal oxide and nitride), relative
`
`selectivity between the two materials may also be exploited to design a structure
`
`wherein conductor caps 28 are extremely thin.” ʼ894 Patent at 5:27-31.
`
`
`
`As shown in Figure 2D below, layer 42 is over the first insulating layer 28
`
`and adjacent to the insulating spacer 29. Ex. HYNIX-1004, 5:15-22; Ex. HYNIX-
`
`1003 (“Subramanian Decl.”) at ¶ 47.
`
`
`
`19
`
`

`
`Importantly, the table in column 6 identifies “silicon nitride” as the preferred
`
`material for layer 42.
`
`
`
`
`Havemann even clarifies that the etch stop and insulators should be different
`
`materials: “If conformal layer 30 and overlayer 42 differ in materials (e.g.
`
`thermal oxide and nitride), relatively selectively between the two materials may
`
`also be exploited to design a structure wherein conductor caps 28 are extremely
`
`thin.” (emphasis added). Ex. HYNIX-1004, 5:27-31; Ex. HYNIX-1003
`
`(“Subramanian Decl.”) at ¶ 48.
`
`[1.6] “wherein a side of the insulating spacer has an angle relative to the
`substrate surface that is either a right angle or an acute angle of more
`than 85°.”
`
`
`
`Figure 2D of Havemann illustrates that the insulating spacers, in yellow, are
`
`perpendicular to the substrate surface 20:
`
`
`
`20
`
`

`
`Specifically, Havemann
`
`discloses that “[c]ap window
`
`39 supplies a pattern for
`
`etching a contact window
`
`through organic-containing
`
`layer 32 by a suitable anisotropic (substantially in one direction, usually vertical)
`
`etch.” Ex. HYNIX-1004, col. 4, lines 37-40. Havemann further discloses that
`
`“limited etch anisotropy” is the “ability to etch in one direction only, e.g.
`
`vertically.” (emphasis added). Ex. HYNIX-1004, col. 2, lines 4-5. As shown
`
`above, Havemann discloses the limitations recited in [1.6].
`
`Claim 2
`
`[2.0] “The semiconductor apparatus of claim 1 wherein said etch stop
`
`material comprises silicon nitride.”
`
`
`
`Havemann discloses that “silicon nitride and silicon dioxide (of different
`
`varieties) are used for the dielectric layers;….” (emphasis added). Ex. HYNIX-
`
`1004, 1:56-60. As explained above, the table in column 6 clarifies that the
`
`preferred material for the etch stop layer 42 is silicon nitride. Thus, Havemann
`
`discloses the claim limitations recited in [2.0].
`
`Claim 3
`
`[3.0] “The semiconductor apparatus of claim 1 wherein said etch stop
`
`material comprises silicon dioxide.”
`
`
`
`
`21
`
`

`
`
`
`Havemann discloses that “[s]ilicon nitride and silicon dioxide (of different
`
`varieties) are used for the dielectric layers;….” (emphasis added). Ex. HYNIX-
`
`1004, 1:56-60 The etch stop layer is disclosed as a dielectric layer. Ex. HYNIX-
`
`1004, 5:15-20.
`
`Havemann further clarifies that either silicon nitride or silicon dioxide are
`
`useable as an etch stop in its table at column 6. Ex. HYNIX-1004, Table at 6:30-
`
`31. The table shows silicon nitride and thermal oxide as alternatives for forming
`
`the etch stop material. Thermal oxidation and CVD oxide are and were well-
`
`known methods in the art for producing silicon dioxide. Ex. HYNIX-1003
`
`(“Subramanian Decl.”) at ¶ 56.
`
`
`
`Thus, Havemann discloses the claim limitations recited in [3.0]. Ex.
`
`HYNIX-1003 (“Subramanian Decl.”) at ¶ 56.
`
`Claim 4
`
`[4.0] “The structure of claim 1, wherein the insulating spacer has a surface
`
`portion in the contact region without overlying etch stop material.”
`
`
`
`As illustrated below, Figure 2D of Havemann discloses that after etching the
`
`top portion of the insulating spacer is not covered by etch stop material. Ex.
`
`HYNIX-1004, 5:6-9, Figure 2D; Ex. HYNIX-1003 (“Subramanian Decl.”) at ¶ 59.
`22
`
`
`
`

`
`The surface of th