United States Patent [19]
`Real et a1.
`
`US005377184A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,377,184
`Dec. 27, 1994
`
`[73] Assignee:
`
`[54] METHOD OF CONTROLLING TWA LINK IN
`A COMIVIUNICATIONS ADAPTER BY
`MONITORING BUFFER FILL LEVELS
`[75] Inventors: Peter D. Beal, Endicott, N.Y.;
`Karlheinz Dutke, Deckenpfronn,
`Germany; Brian W. Noordyke,
`Owego; Michael L. Shupert, Vestal,
`both of N.Y.
`International Business Machines
`Corporation, Armonk, N.Y.
`'[211 App]. No.: 343,772
`[22] Filed:
`Mar. 2, 1992
`[51] Int. Cl; ............................................ .. H04J 15/00
`[52] US. Cl. ...................................... .. 370/24; 370/26;
`370/31
`[58] Field of Search ..................... .. 370/24, 36, 37, 31,
`370/32, 84, 94.1, 94.2, 60, 60.1, 61, 29, 108;
`375/7, 8; 178/71 R, 71 A, 71 B
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`1,264,378 4/1918 Dixon .............................. .. 178/17 B
`3,956,589 5/1976 Weathers et al.
`370/31
`4,368,512 l/1983 Kyu et a1.
`364/200
`4,422,171 12/1983 Wortley et al. ..
`371/32
`
`4,597,073 6/ 1986 Staples . . . . . . . . . . . . .
`
`. . . .. 370/24
`
`. . . .. 370/24
`4,599,719 7/ 1986 Breen et a1. . . . . . .
`.. 370/85.7
`4,651,316 3/1987 Kocan et al. ....... ..
`371/41
`4,701,923 10/1987 Fukasawa et a1.
`4,712,229 12/ 1987 Nakamura ....................... .. 379/58
`4,771,417 9/ 1988 Maxwell et a1. .................... .. 370/ 13
`4,796,255 l/ 1989 Westbrook et a1. .
`370/ 100
`4,852,088 7/1989 Gulick et a1. . . . .
`. . . .. 370/29
`
`. . . .. 370/ 32
`4,924,456 5/ 1990 Maxwell et a1. . . . . . . . . .
`370/ 108
`5,054,034 10/ 1991 Hughes-Hartogs .... ..
`5,179,556 1/ 1993 Turner ........................ .. 370/84
`5,245,636 9/ 1993 Sari et a1. .......................... .. 370/ 108
`
`OTHER PUBLICATIONS
`IBM TDB, vol. 34, No. 1, Jun. 1991, “Half-Duplex
`Wrap Test, Walking-Reset Error-Forcing Tech
`niques”, pp. 245-251.
`IBM TDB, vol. 33, No. 5, Oct. 1990, “Method For
`Consistent Data Replication For Collection Manage
`ment In A Dynamic Partially Conneceted Collection”
`pp. 454-464.
`
`IBM TDB, vol. 33, No. 5, Oct. 1990, “Only In Chain
`Full-Duplex LU7 And Increased RU Size”, pp. 67-68.
`IBM TDB, vol. 32, No. 6A, Nov. 1989, “Method For
`Forward-Transistive Fully-Connected Collection
`Management”, pp. 341-347.
`IBM TDB, vol. 32, No. 3A, Aug. 1989, “Communica
`tions ‘Port Manager’ For Computer Systems”, pp.
`104-108.
`IBM TDB, vol. 26, No. 3B, Aug. 1983, “Multicon?gu
`ration Funnel Circuits”, pp. 1507-1511.
`IBM TDB, vol. 24, No. 8, Jan. 1992, “Testing of a Half
`Duplex Communication System”, pp. 4116-4118.
`IBM TDB, vol. 23, No. 12, May 1981, “Pseudo-Duplex
`Communications”, pp. 5639-5641.
`IBM TDB, vol. 21, No. 3, Aug. 1978, “Half-Duplex To
`Full-Duplex Asychronous Adapter Architecture For
`Fast Turnaround Data Channels”, pp. 1171-1173.
`IBM TDB, vol. 20, No. 10, Mar. 1978, “Typewriter
`With Detached Portable Keyboard”, pp. 4250-4251.
`Primary Examiner-Douglas W. Olms
`Assistant Examiner-Shick Hom
`Attorney, Agent, or Firm—Arthur J. Samodovitz
`[57]
`ABSTRACT
`A communications adapter interconnects a ?rst device
`exhibiting a two way alternate (TWA) protocol and a
`second device exhibiting a two way simultaneous
`(TWS) protocol. The communications adapter com
`prises a transmit buffer for storing data received from
`the ?rst device via a ?rst communication link for trans
`mission to the second device via a second communica
`tion link, and a receive buffer for storing data received
`from the second device via the second communication
`link for transmission to the ?rst device via the ?rst
`communication link. Data can be transferred in either
`direction between the transmit or receive buffer and the
`?rst device faster than in the same direction between the
`transmit or receive buffer and the second device. To
`optimize the overall transfer rate in both directions
`between the ?rst and second devices, the second com
`munication link is kept busy in both directions by pre
`venting the receive buffer from ?lling with data from
`the second device while the ?rst device transmits data
`to the transmit buffer, and preventing the transmit
`buffer from emptying due to reading by the second
`device while the ?rst device reads data from the receive
`buffer.
`
`28 Claims, 9 Drawing Sheets
`
`

`
`US. Patent
`
`Dec. 27, 1994
`
`Sheet 1 of 9
`
`5,377,184
`
`30-\
`
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`HOST COMPUTER
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`

`
`US. Patent
`
`Dec. 27, 1994
`
`Sheet 2 of 9
`
`5,377,184
`
`24
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`U.S. Patent
`
`Sheet 3 of 9
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`5,377,184
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`
`US. Patent
`
`Dec. 27, 1994
`
`Sheet 5 bf 9
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`5,377,184
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`
`US. Patent
`
`Dec. 27, 1994
`
`Sheet 6 of 9
`
`5,377,184
`
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`

`
`US. Patent
`
`Dec. 27, 1994
`
`Sheet 7 of 9
`
`5,377,184
`
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`

`
`US. Patent
`
`Dec. 27, 1594
`
`Sheet 8 of 9
`
`5,377,184
`
`400 \ RECEIVE
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`
`54
`
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`
`

`
`US. Patent
`
`Dec. 27, 1994
`
`Sheet 9 of 9
`
`5,377,184
`
`30
`
`HOST-CPU
`
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`
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`
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`DRIVERS
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`DATA
`
`ADDRESS
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`CONTROL
`
`COMMUNICATION
`ADAPTER
`
`

`
`1
`
`5,377,184
`
`METHOD OF CONTROLLING TWA LINK IN A
`COMNIUNICATIONS ADAPTER BY
`MONITORING BUFFER FILL LEVELS
`
`The invention relates generally to communications
`systems, and deals more particularly with a communica
`tions adapter between a two way alternate or half du
`plex communication link and a two way simultaneous
`or full duplex communication link.
`Many communication links operate according to a
`two way alternate (TWA) orhalf'duplex protocol in
`which communication can occur in both directions
`between two devices but at different times. Usually,
`two separate conductor paths are provided, one for
`communication in each direction. Other communica
`tion links operate according to a two way simultaneous
`(TWS) or full duplex protocol in which communication
`can occur in both directions at the same time. Two
`separate conductor paths are provided, one for commu
`20
`nication in each direction. An international standard for
`both of the TWA and TWS protocols is collectively
`known as “High Level Data Link Control or HDLC”
`and a similar IBM standard for both is collectively
`known as “Synchronous Data Link Control or SDLC”.
`25
`Both of the IBM standards are described in detail in a
`manual entitled “Synchronous Data Link Control Con
`cepts” which is available from IBM Corp. at Me
`chanicsburg, Pa. by publication number GA27-3093.
`Either type of communication protocol can be used
`between two computers, between one computer and a
`communications device or between two communica
`tions devices.
`Some computers such as an IBM System/ 370 or Sys
`tem/390 computer with a virtual telecommunications
`access method (VTAM) program exhibit a TWA proto
`col. It is desirable in some circumstances to permit such
`a computer (or other device which exhibits a TWA
`communication protocol) to communicate with another
`device which exhibits a TWS protocol. In such a case,
`40
`a communications adapter is required between the two
`devices.
`Typically, the TWA computer transmits and receives
`data via a bus which is many bits wide whereas the
`other, TWS device transmits and receives data serially,
`45
`one bit at a time. Consequently, the TWA computer can
`usually transmit and receive data at a faster rate than the
`other, TWS device, can transmit and receive data, re
`spectively.
`An object of the present invention is to provide a
`communications adapter between a ?rst device or com
`munications link which exhibits a TWA protocol and a
`second device or communications link which exhibits a
`TWS protocol.
`'
`Another object of the present invention is to provide
`such a communications adapter which maximizes the
`overall throughput.
`Still another object of the present invention is to
`provide such a communications adapter which does not
`require changes to either of the devices coupled to it.
`
`50
`
`10
`
`35
`
`55
`
`60
`
`2
`sion to the second device, and a receive buffer for stor
`ing data received from the second device for transmis
`sion to the ?rst device. The adapter also includes a host
`interface program and a bus interface for transferring
`data between the transmit and receive buffers and the
`?rst device via a ?rst communication link according to
`the TWA protocol, and a line interface program and a
`controller for transferring data between the transmit
`and receive buffers and the second device via a second
`communication link according to the TWS protocol.
`To optimize the overall transfer rate in both direc
`tions between the ?rst and second devices, the second
`communication link is kept busy in both direction by the
`following procedure. The ?ll levels of the transmit and
`receive buffers are monitored. The transfer of data from
`the ?rst device to the transmit buffer is halted when the
`receive buffer ?lls to a predetermined level even though
`the ?rst device has additional data to transfer to the
`transmit buffer, and transfer of data from the receive
`buffer to the ?rst device is begun. Thus, the receive
`buffer maintains space to store additional data from the
`second device. Also, the transfer of data from the re
`ceive buffer to the ?rst device is halted when the trans
`mit buffer empties to a predetermined level and transfer
`of data from the ?rst device to the transmit buffer is
`begun. Thus, the transmit buffer continues to have data
`to transmit to the second device.
`According to one feature of the present invention, the
`?rst communication link is parallel and the second com
`munication link is serial. Thus, data can be transferred in
`either direction between the transmit or receive buffer
`and the ?rst device faster than in the same direction
`between the transmit or receive buffer and the second
`device. This increases the need for the foregoing opti
`mization procedure.
`
`BRIEF DESCRIPTION OF THE FIGURES
`FIG. 1 is a block diagram illustrating a standard host
`computer including a standard communication link
`which exhibits a TWA protocol, a standard remote
`device including a standard communication link which
`exhibits a TWS protocol, a standard electrical transmis
`sion line connected to the communication link of the
`remote device, and a communications adapter accord
`ing to the present invention, which adapter is connected
`between the communication link of the host computer
`and the transmission line to adapt the two different
`protocols to each other.
`FIG. 2 is a more detailed block diagram of the com
`munications adapter of FIG. 1.
`FIG. 3 is a flow chart illustrating the function of a
`telecommunication access program within the commu
`nication link of the host computer of FIG. 1, which
`program establishes a TWA communication mode.
`FIG. 4 is a ?ow chart illustrating a TWA host inter
`face routine of a computer program executed by the
`communications adapter of FIG. 1.
`FIG. 5 is a ?ow chart of a transmit subroutine of a
`line interface routine of the computer program executed
`by the communications adapter of FIG. 1.
`FIG. 6 is a ?ow chart of an exit busy subroutine of the
`line interface routine of the computer program executed
`by the communications adapter of FIG. 1.
`FIG. 7 is a ?ow chart illustrating the remainder of the
`line interface routine of the computer program executed
`by the communications adapter of FIG. 1.
`
`SUMMARY OF THE INVENTION
`The invention resides in a communications adapter
`for interconnecting a ?rst device exhibiting a two way
`alternate (TWA) protocol and a second device exhibit
`65
`ing a two way simultaneous (I‘W S) protocol. The com
`munications adapter comprises a transmit buffer for
`storing data received from the ?rst device for transmis
`
`

`
`5,377,184
`3
`FIG. 8 is a ?ow chart illustrating a TWS mode of
`communication from and to the remote device of FIG.
`1.
`FIG. 9 is a block diagram of a bus to bus adapter
`within the communication link of the host computer.
`
`5
`
`15
`
`25
`
`4
`. the System/ 370 or System/390 architecture to the bus
`26 which exhibits a Micro Channel (R) bus architecture.
`Adapter card 48 includes a buffer which receives the
`data blocks from the host computer internal bus 49
`pursuant to the channel program 40 and provides the
`data to communications adapter 24 at a time and rate
`determined by the Micro Channel (R) bus 26 and the
`communications adapter. Adapter card 48 is described
`in more detail below and in copending patent applica
`tion entitled “Interprocessor Buffer Which Receives
`10V
`Data From One Processor At One Rate And Dynami
`cally Packetizes The Data For Transmission To The
`Other Processor” Ser. No. 07/341,503 ?led Apr. 21,
`1989 by Clark et. 21., now U.S. Pat. No. 5,117,486 which
`patent is hereby incorporated by reference as part of the
`present disclosure.
`Communications adapter 24 comprises a transmit
`buffer 50, a receive buffer 51 and other hardware de
`scribed in detail below. The hardware is publicly avail
`able (for more than one year) as IBM Portmaster Adap
`ter/A Hardware, Part Number 53F2604 or 53F2607.
`The hardware within adapter 24 is also described in an
`IBM publication entitled “Realtime Interface Co
`Processor Portmaster Adapter/A Hardware Technical
`Reference which is available from IBM Corp. at Me
`chanicsburg, Pa. by order number S33F-5337, which
`document is hereby incorporated by reference as part of
`the present disclosure.
`Transmit buffer 50 receives data from the host com
`puter 20 for transmission to the remote device 22, and
`receive buffer 51 receives data from the remote device
`22 for receipt by the host computer 20. Communica
`tions adapter 24 is also programmed according to the
`present invention to adapt the TWA protocol of host
`computer 20 to the TWS protocol of remote device 22.
`Accordingly, communications adapter 24 includes a
`host interface routine 52 to interface to the TWA proto
`col of the host (or any communications device exhibit
`ing the TWA protocol), and a line interface routine 54
`to interface to the TWS protocol of the remote device
`22 (or any other communications device exhibiting the
`TWS protocol). These two routines are described in
`detail below and each provides a basic and optimizing
`function.
`_
`The basic function of the host interface routine 52 is
`to control the transfer of data from the host computer
`20 to the transmit buffer 50 pursuant to the write
`CCWs, and the transfer of data from the receive buffer
`51 to the host computer 20 pursuant to the read CCWs,
`both according to the TWA protocol. The basic-func
`tion of the line interface routine 54 is to control the
`transfer of data from the transmit buffer to the remote
`device, and the transfer of data from the remote device
`to the receive buffer according to the TWS protocol.
`The optimizing function of each routine attempts to
`make full use of the transmission line 28 in both direc
`tions at all possible times for the following reasons. The
`rate at which data can be sent (in either direction) across
`bus 26 is much higher than the rate at which data can be
`sent in one direction across transmission line 28. This is
`due to the fact that bus 26 is many bits wide (for exam
`ple 16) whereas transmission line 28 has a single conduc
`tor path for each direction. Also, transmission line 28
`may have a limited bandwidth. The rate that data can be
`sent alternately in both directions across internal bus 26
`is high enough to fully occupy transmission line 28 with
`simultaneous transmission in both directions. However,
`if the host computer 20 were to spend too much contin
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Referring now to the Figures in detail wherein like
`reference numerals indicate like elements throughout
`the several views, FIG. 1 illustrates a host computer 20
`which exhibits a TWA protocol in accordance with the
`prior art, a remote computer 22 which exhibits a TWS
`protocol in accordance with the prior art and a commu
`nications adapter 24 in accordance with the present
`invention. The communications adapter 24 is locally
`coupled to the host computer 24 via an internal, parallel
`bus 26 and is remotely coupled to the remote device 22
`via a serial transmission line 28 (electrical, optical or
`satellite). Optionally, the transmission line 28 may in
`clude a modem (not shown) at each end. The communi
`cations adapter 24 provides an interface between the
`TWA protocol of the host computer 20 and the TWS
`protocol of the remote device 22. In the illustrated
`embodiment, the TWA and TWS protocols are de?ned
`by the IBM standards for Synchronous Data Link Con
`trol but could also be de?ned by the similar HDLC or
`other industry standard.
`By way of example, host computer 20 is an IBM
`System/370 or System/390 computer with a CPU 30
`30
`and a VM or VSE operating system 31. A customer
`application program 32 executes on the CPU 30 and
`requests to transfer data to remote device 22. The re
`quest is in the form of a call to a telecommunications
`access program 34 which, in the illustrated embodi
`ment, is an IBM virtual telecommunications access
`method (VTAM) program. The VTAM program is
`described in more detail in the following documents
`which are all published by IBM Corp. and available
`from IBM Corp. at Mechanicsburg, Pa. by the associ
`ated order number: “Network Program Products Gen
`eral Information” (GC30-3350), “ACF/VT AM Gen
`eral Information Concepts” (GC27-0463), and “VTAM
`Diagnosis Reference”(LY30-5582). Chapter 2 of “Net
`work Program Products General Information” is
`hereby incorporated by reference as part of the present
`disclosure. In response to the call, VTAM program 34
`generates a channel program 40 in accordance with
`System/370 and System/ 390 architecture which chan
`nel program includes a series of write channel command
`50
`words (CCWs) to order writing of data from the host
`computer to the remote device. Each channel command
`word orders the writing of a block of data so the
`VTAM program 34 includes enough write CCWs
`(within a limit) in the channel program to write all the
`55
`data requested to be written by the customer applica
`tion program 32. A VTAM buffer space 42 serves as a
`staging area for the writing of the data from the cus
`tomer application program 32. The customer applica
`tion program 32 also requests VTAM program 34 to
`read data from remote device 22, and in response
`VTAM program 34 adds read CCWs to the channel
`program. The channel program ends with a status CCW
`to request from the communications adapter the status
`of the write and read operations pursuant to the previ
`ous CCWs.
`Host computer 20 also includes an adapter card 48
`which adapts an internal host system bus 49 exhibiting
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`uous time in the transmit mode without intervening
`operation in the receive mode, the transmit buffer may
`become full of data from the host computer and this
`would stop the use of bus 26, or the receive buffer may
`become full of data from the remote device and this
`would stop use of the transmission line 28 for receiving
`data from the remote device. Similarly, if the host com
`puter were to spend too much continuous time in the
`receive mode without intervening operation in the
`transmit mode, the receive buffer may become empty
`and this would stop the use of bus 26 in the receipt
`mode. Also, the transmit buffer may become empty, and
`this would stop use of the transmission line 28 for trans
`mitting data to the remote device. Any of these four
`situations, if allowed to occur, would limit the overall
`throughput. Consequently, the optimizing portions of
`the routines monitor the ?ll level of each buffer, and
`manipulate the transmit and receive operations of the
`host computer to avoid ?lling the transmit buffer 50 or
`receive buffer 51 beyond predetermined levels, and to
`avoid emptying the transmit buffer 50 or the receive
`buffer 51 below predetermined levels. Thus, each time
`the host computer transmits a block of data to the trans
`mit buffer pursuant to a write CCW, the host interface
`routine checks the ?ll level of the transmit buffer and
`25
`the ?ll level of the receive buffer, and if both have
`reached respective predetermined levels, “?ushes” the
`remaining write CCWs in the channel program by
`quickly responding to VTAM that all of the remaining
`write CCWs have been executed. Then, the channel
`program proceeds to the read CCWs. Similarly, each
`time the host computer reads a block of data from the
`receive buffer pursuant to a read CCW, the host inter
`face routine checks the ?ll level of the transmit buffer
`and the ?ll level of the receive buffer and if both have
`fallen to respective predetermined levels, ?ushes the
`remaining read CCWs by responding to VTAM that
`there is no data left to be read. This will permit the
`channel program to quickly proceed to subsequent
`write CCWs, if any. The last CCW in the channel pro
`gram is a status request, and the host interface routine
`responds to VTAM that the data corresponding to the
`?ushed write CCWs must be resent, and VTAM gener
`ates the requisite write CCWs to accomplish this. This
`process is repeated continuously throughout the com
`munication.
`It should be noted that execution of neither routine
`requires change to the code of VTAM 34 or the com
`munication link of the remote device. While the data is
`transferred alternately from the host computer 20 to
`transmit buffer 50 and from the receive buffer 51 to the
`host computer 20 according to the TWA protocol, data
`is transferred in both directions simultaneously between
`the remote device 22 (via transmission line 28) and the
`transmit and receive buffers 50 and 51 according to the
`TWS protocol. Assuming neither buffer becomes full or
`empty, the time of the transmission from the remote
`device 22 to the receive buffer is determined by the
`remote device and the time of the transmission from the
`transmit buffer to the remote device is determined by
`the line interface routine.
`FIG. 2 illustrates the communications adapter 24 in
`more detail. In addition to transmit buffer 50 and re
`ceive buffer 51 which are located in RAM 140, adapter
`24 comprises a RAM controller 142 for RAM 140, a bus
`interface 144 for the Micro Channel (R) bus 26, and a
`CPU 146 which executes the host interface routine and
`the line interface routine. The RAM controller 142 and
`
`6
`bus interface 144 control at a relatively low level the
`transfer of data between the transmit and receive buff
`ers 50 and 51 and VTAM 34 via the Micro Channel (R)
`bus and the adapter card 48. The higher level control is
`provided by the host interface routine which executes
`on CPU 146. Communications adapter 24 also includes
`a dual universal serial communications controller
`(DUSCC) 148 which provides low level interface to the
`transmission line 28, i.e. DUSCC 148 provides full du
`plex channels, SDLC protocol support, NRZ and
`NRZI data encoding, and CRC checking and genera
`tion. Communications adapter 24 also includes a
`DMA/peripheral interface 150 which provides direct
`memory access (DMA) to the transmit and receive
`buffers to transfer data stored therein to and from
`DUSCC 148. A counter/timer and parallel I/O unit
`(CIO) 161 provides control leads for the interface to
`remote device 22. A PROM 163 stores bootstrap and
`diagnostics programs for the communications adapter,
`and LAT 165 is an address latch.
`‘The following is a more detailed, ?ow description of
`the present invention. FIG. 3 is a ?ow chart illustrating
`the VTAM program 34. Initially, VTAM starts a com
`munication link with the remote device by sending an
`open command to the remote device (to which the
`remote device responds with an acknowledge) (step
`199). Next, VTAM builds a channel program compris
`ing, in order, a polling CCW, multiple read CCWs and
`a status CCW (step 200). Also, VTAM stores a channel
`address word in a predetermined location in host mem
`ory 25. The channel address word identi?es a location
`in host memory that begins the channel program. Then,
`VTAM issues a start I/O to the communications
`adapter 24 (step 201), and then waits for either a re
`sponse from the communications adapter or a command
`from the host application program 32 (step 202).
`In response to the start I/O, the bus interface 144
`interrupts the host interface routine, and the host inter
`face routine directs the bus interface 144 to fetch the
`?rst channel command word in the channel program. In
`response, the bus interface requests the next CCW from
`the adapter card 48, and the adapter card 48 obtains the
`CCW from the host memory, stores the data in a buffer
`within the adapter card 48 and makes the data available
`to the Micro Channel (R) bus. Then, the bus interface
`144 fetches the data from the adapter card, and the
`RAM controller 142 writes the data into a CCW buffer
`311. Then, the bus interface noti?es the CPU 146 that
`the CCW has been obtained from the host computer,
`and the host interface routine begins to execute the
`CCW (step 290 of FIG. 4). The ?rst channel command
`word is a polling command (decision block 292) which
`noti?es the communications adapter (although it was
`intended by VTAM to notify the remote device) that
`the communications adapter can now transfer data to
`VTAM. This polling is required by the TWA protocol
`of the host computer to ensure that both the host com
`puter and its partner do not try ‘to transfer data at the
`same time. If the communications adapter has no data to
`send (decision block 294), the host interface routine
`directs the bus interface to fetch the next CCW. How
`ever, if the communications adapter has data to send to
`the host computer, the host interface routine directs the
`bus interface to fetch a subsequent read CCW from the
`channel program (step 296). Then, the bus interface
`fetches the read CCW (step 290) and processes it (in the
`same manner that it processes any subsequent read
`CCW). After determining that the current CCW is a
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`read CCW (decision blocks 302 and 340), the host inter
`face routine determines if a read CCW flushing indica
`tor has been set (decision block 342). Such an indicator
`is set when the ?ll levels of the transmit buffer 50 and
`the receive buffer 51 have both fallen to respective
`predetermined levels, for example, 12% of capacity of
`each. The ?ll level of each buffer is measured by count
`ing the amount of data that is added to the bu?'er and
`subtracting the amount of data that is read out of the
`buffer. If the fill levels of both buffers are below the
`predetermined levels, the read CCW is ?ushed, i.e. not
`processed by the communications adapter. The reason
`for flushing the read CCW is to proceed quickly to a
`subsequent write CCW before the transmit buffer 50
`becomes empty because in such a case, there would be
`no data to send over the transmission line 28 and the
`overall transfer rate or throughput would be reduced.
`However, if the read CCW ?ush indicator has not been
`set, the host interface routine proceeds to determine if
`the receive buffer 51 is empty (decision block 344). If so,
`then there is no data to sendto the host, the read ?ush
`ing indicator is set (step 358) and this read CCW is not
`processed further. However, if there is a frame of data
`in the read buffer, then it is sent to the host computer
`(step 346) in the following manner.
`When the data arrived at the communications adapter
`from the remote device 22 for transmission to host com
`puter 20, the line interface routine wrote control infor
`mation into the registers within DUSCC 148 and
`DMA/peripheral Interface 150. The control informa
`tion indicated the nature of the communication link to
`the remote device, i.e. TWS, the direction of the com
`munication, a description of control lead handshaking, a
`linkage between DUSCC 148 and DMA/Peripheral
`interface 150 and a requirement to send an interrupt to
`the line interface routine at the end of each data frame.
`Then, the line interface routine directed the DMA/Per
`ipheral interface 150 to DMA the data into a speci?c
`location in the receive buffer 51.
`Subsequently, when the CPU 146 executes step 346,
`CPU 146 noti?es the bus interface where the data is
`located in the receive buffer and directs the bus inter
`face 144 to send the data to the adapter card 48 via the
`Micro Channel (R) bus 26. After bus interface 144 com
`pletes the transfer to the adapter card 48, the bus inter
`face noti?es the CPU, and the CPU sends an interrupt
`to VTAM at step 202.
`Then, the host interface routine calls a line interface
`exit busy subroutine at step 350 of FIG. 6. The purpose
`of this call is as follows. It was possible that before this
`last frame was sent from the receive buffer 51 to the
`host computer that the receive buffer was full. In such
`a case, the communications adapter would have noti?ed
`the remote device that it was busy and could not receive
`any more data from the remote device. The call to the
`exit busy line interface subroutine checks if the commu
`nications adapter is in this busy state (decision block
`350) and if so, resets the busy indicator and noti?es the
`remote device that the communications adapter is no
`longer busy (step 352). Then the line interface exit busy
`subrout