Petition for Inter Partes Review of USP 8,252,675
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`In re Inter Partes Review of:
`U.S. Patent No. 8,252,675
`Issued: August 28, 2012
`Application No.: 12/942,763
`Filing Date: November 9, 2010
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`For: Methods of Forming CMOS Transistors with High Conductivity
`Gate Electrodes
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`FILED VIA PRPS
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`SECOND PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,252,675
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`For ease of reference, Petitioner refers to this Petition as the “Second ’675
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`Petition” challenging claims 1-8 and 10-15 of the ’675 patent.
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`

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`Second Petition for Inter Partes Review of USP 8,252,675
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`TABLE OF CONTENTS
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`I.
`
`II.
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`Introduction ...................................................................................................... 1
`
`Requirements For Petition For Inter Partes Review ....................................... 1
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`A. Grounds for Standing (37 C.F.R. § 42.104(a)) ..................................... 1
`B.
`Notice of Lead and Backup Counsel and Service Information ............. 1
`C.
`Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1)) .................. 2
`D. Notice of Related Matters (37 C.F.R. § 42.8(b)(2)) .............................. 2
`E.
`Fee for Inter Partes Review ................................................................... 3
`F.
`Proof of Service ..................................................................................... 3
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`III.
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`Identification Of Claims Being Challenged (37 C.F.R. § 42.104(b)) ............. 3
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`IV. Description Of The Purported Invention ......................................................... 4
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`A.
`B.
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`Technology Background ....................................................................... 4
`The ’675 Patent Disclosure ................................................................... 7
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`V. Overview Of The Prior Art ............................................................................ 11
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`A. Hsu’s March 12, 2008 Priority Date ................................................... 12
`B.
`Forming the Gate Electrodes in Hsu ................................................... 12
`C.
`’675 Patent Prosecution History .......................................................... 16
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`VI. Claim Construction ........................................................................................ 17
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`VII. Level Of Ordinary Skill In The Art In The Relevant Timeframe ................. 18
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`VIII. Differences Between Hsu And U.S. Patent No. 2009/0065809
`(“Yamakawa”) ............................................................................................... 19
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`IX. Precise Reasons For The Relief Requested ................................................... 20
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`A. Ground 1: The Challenged Claims Are Anticipated By
`U.S. Patent No. 8,536,660 (“Hsu”) ..................................................... 20
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`Second Petition for Inter Partes Review of USP 8,252,675
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`Second Ground Of Invalidity – Claim 12 Is Rendered Obvious By
`Hsu ................................................................................................................. 56
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`X.
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`A.
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`Claim 12 .............................................................................................. 56
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`XI. Conclusion ..................................................................................................... 59
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`Second Petition for Inter Partes Review of USP 8,252,675
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`EXHIBIT LIST
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`1101 U.S. Patent No. 8,252,675 (the “’675 patent”)
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`1102 File History for the ’675 Patent
`1103 Declaration of Dr. Jack Lee in support of Petition for Inter Partes Review
`of U.S. Patent No. 8,252,675 (“Lee Decl.”)
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`1104 Curriculum Vitae of Dr. Jack Lee
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`1105 U.S. Patent No. 8,536,660 (“Hsu”)
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`1106 Excerpt from File History for Hsu (U.S. Patent Application No. 12/047,113)
`(the “Hsu application”)
`1107 Memorandum Opinion, Samsung Electronics Co., Ltd. et al. v. NVIDIA
`Corp. et al., No. 3:14-cv-00757-REP (E.D. Va. July 30, 2015), Dkt. No. 221
`(“Claim Construction Op.”)
`1108 Y.F. Hu et al., A Study of Titanium Nitride Diffusion Barriers Between
`Aluminum and Silicon by X-ray Absorption Spectroscopy: the Si, Ti and N
`Results, 8 J. SYNCHROTRON RADIATION 860 (2001)
`1109 Wen-Fa Wu et al., Novel Multilayered Ti/TiN Diffusion Barrier for Al
`Metallization, 34 J. ELEC. MATERIALS 1150 (2005)
`1110 Non-Confidential Excerpts from Rebuttal Expert Report of Dr. Richard B.
`Fair Regarding U.S. Patent No. 8,252,675, Samsung Electronics Co., Ltd. et
`al. v. NVIDIA Corp. et al., No. 3:14-cv-00757-REP (E.D. Va. Oct. 9, 2015)
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`Second Petition for Inter Partes Review of USP 8,252,675
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`INTRODUCTION
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`I.
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`On behalf of NVIDIA Corporation (“NVIDIA”) and in accordance with 35
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`U.S.C. § 311 and 37 C.F.R. 42.100, inter partes review of claims 1-8 and 10-15 of
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`United States Patent No. 78,252,675 (“the ’675 patent”), titled “Methods of
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`Forming CMOS Transistors with High Conductivity Gate Electrodes” is hereby
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`requested. According to United States Patent and Trademark Office (“Patent
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`Office”) records, the ’675 patent was originally assigned to, and is currently owned
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`by, Samsung Electronics Co., Ltd. (“Samsung”). A copy of the ’675 patent is
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`attached as Ex. 1101, and the prosecution history is attached as Ex. 1102.
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`Petitioner previously filed a Petition for Inter Partes Review of U.S. Patent No.
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`8,252,675 on June 1, 2015. See IPR2015-01318; see also Section II.D, infra.
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`II. REQUIREMENTS FOR PETITION FOR INTER PARTES REVIEW
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`A. Grounds for Standing (37 C.F.R. § 42.104(a))
`Petitioner certifies that the ’675 Patent is available for inter partes review
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`and that Petitioner is not barred or estopped from requesting inter partes review of
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`the challenged claims of the ’675 Patent on the grounds identified herein.
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`B. Notice of Lead and Backup Counsel and Service Information
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`Pursuant to 37 C.F.R. §§ 42.8(b)(3), 42.8(b)(4), and 42.10(a), Petitioner
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`provides the following designation of Lead and Back-Up counsel.
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`Second Petition for Inter Partes Review of USP 8,252,675
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`LEAD COUNSEL
`Robert Steinberg (Reg. No. 33144)
`(Bob.Steinberg@lw.com)
`Postal & Hand-Delivery Address:
`Latham & Watkins LLP
`355 South Grand Avenue
`Los Angeles, CA 90071-1560
`T: 213-485-1234, F: 213-891-8763
`
`BACKUP COUNSEL
`Clement Naples (Reg. No. 50663)
`Clement.Naples@lw.com
`Latham & Watkins LLP
`885 Third Avenue
`New York, NY 10022-4834
`212.906.1200
`212.751.4864 (Fax)
`
`Julie Holloway (Reg. No. 44769)
`Julie.Holloway@lw.com
`Latham & Watkins LLP
`505 Montgomery Street
`Suite 2000
`San Francisco, CA 94111
`415.391.0600
`415.395.8095 (Fax)
`
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`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney is attached hereto.
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`C. Notice of Real-Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
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`The real-party-in-interest is NVIDIA Corporation. No other party exercised
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`or could have exercised control over this petition; no other party funded or directed
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`this petition. (See Office Patent Trial Practice Guide, 77 Fed. Reg. 48759-60.)
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`D. Notice of Related Matters (37 C.F.R. § 42.8(b)(2))
`Samsung Electronics Co., Ltd. et al v. NVIDIA Corp. et al., No. 3:14-cv-
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`00757-REP (E.D. Va.). Petition for Inter Partes Review of U.S. Patent No.
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`8,252,675, No. IPR2015-01318 (filed June 1, 2015). According to Patent Office
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`records, no applications claim the benefit of priority to the filing date of the ’675
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`patent.
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`Second Petition for Inter Partes Review of USP 8,252,675
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`Fee for Inter Partes Review
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`E.
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`The Director is authorized to charge the fee specified by 37 C.F.R. §
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`42.15(a) to Deposit Account No. 506269.
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`F.
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`Proof of Service
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`Proof of service of this petition on the patent owner at the correspondence
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`address of record for the ’675 Patent is attached hereto.
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`III.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED (37 C.F.R. §
`42.104(B))
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`Claims 1-8 and 10-15 of the ’675 patent (“challenged claims”) are
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`unpatentable in view of the following prior art: U.S. Patent No. 8,536,660 (“Hsu”
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`attached as Ex. 1105), which issued from U.S. Patent Application No. 12/047,113.
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`The Hsu application was published as U.S. Publication No. 2009/0230479 on
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`September 17, 2009. Petitioner was unaware of the Hsu reference when the
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`previous petition, No. IPR2015-01318, was filed on June 1, 2015. The first
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`petition relied primarily on the Yamakawa reference. As explained by Dr. Lee,
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`Hsu makes disclosures regarding the portion of third metal gate electrode layer of
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`the PMOS transistor (layer 262 of Hsu) and the upper metal gate electrode (layers
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`160 and 162 of Hsu) that may be more relevant to the invalidity of the ’675 patent.
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`See Lee Decl. at ¶ 77. For this reason, while Yamakawa on its own fully
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`anticipates the claims of the ’675 patent, Hsu is the stronger reference between the
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`two.
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`Second Petition for Inter Partes Review of USP 8,252,675
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`Specifically, the challenged claims are invalid under 35 U.S.C. §§ 102 and
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`103 on the following grounds:
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`Ground 1: claims 1-8 and 10-15 are anticipated under 35 U.S.C. § 102(e)
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`by Hsu, and
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`Ground 2: claim 12 is rendered obvious under 35 U.S.C. § 103 by Hsu in
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`view of the knowledge of a POSITA at the time.
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`IV. DESCRIPTION OF THE PURPORTED INVENTION
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`The ’675 patent relates generally to a method for forming the layers of a
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`metal gate electrode. See Ex. 1103 (Declaration of Dr. Jack Lee in support of
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`Petition for Inter Partes Review of U.S. Patent No. 8,252,675) (“Lee Decl.”) at ¶¶
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`33-41.
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`A. Technology Background
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`1.
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`NMOS and PMOS Transistors
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`There are two basic types of metal-oxide-semiconductor (MOS) transistors,
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`in accordance with the channel type which is induced beneath the gate electrode:
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`NMOS transistors and PMOS transistors. ’675 patent at 1:24-26; see also Lee
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`Decl. at ¶ 23-25. When an NMOS or PMOS transistor is turned on, a channel is
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`formed in which electrons (-) or holes (+) flow through the body region from
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`source to drain, respectively. See id. at ¶ 24. An NMOS transistor is turned on by
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`applying a large enough positive voltage to the gate electrode, and a PMOS
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`transistor is turned on by applying a large enough negative voltage to the gate
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`electrode. See id.
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`2.
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`Photolithography and Etching
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`NMOS and PMOS
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`transistor gates are formed using a series of
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`photolithography steps. Lee Decl. at ¶ 26. Photolithography typically involves
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`depositing a light sensitive but etchant resistive film, called a photoresist, onto the
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`wafer surface. Id. The photoresist is then exposed to ultraviolet (“UV”) light
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`through a mask and the areas where the photoresist was exposed to the UV light
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`are washed away. Id. This produces a photoresist pattern. Id. The photoresist
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`pattern is then used as a mask to etch materials in the areas where the photoresist
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`had been washed away. Id.
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`During etching, both the film being etched and other materials under or
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`within the film being etched can be etched by the etchant. Id. at ¶ 27. The etching
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`occurs from top to bottom because the etchant must first etch through upper layers
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`before it can reach lower layers. Id. Thus, for example, if top, middle, and bottom
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`layers had been deposited, etching through all three layers would require etching
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`those layers sequentially, i.e., etching the top layer first, etching the middle layer
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`second, and etching the bottom layer last. Id.
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`3.
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`Chemical-Mechanical Polishing
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`In a CMP process, the wafer is mounted face down on a rotating carrier, and
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`is pressed against a rotating plate containing a polishing pad. Id. at ¶ 28.
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`An abrasive aqueous slurry is continuously dripped onto the pad. Id. CMP also
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`removes material from top to bottom because it must polish through the top layer
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`of material before the next underlying layer is exposed to the polishing pad and
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`slurry. Id. Depending on the complexity of the materials being polished, a multi-
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`step polishing sequence with different types of slurry might be used. Id.
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`4. Gate-First Versus Gate-Last
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`In the most simple terms, gate-first and gate-last refer to whether the
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`transistor gate is formed before or after a high temperature annealing process
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`required to form the source and drain regions of a transistor. Id. at ¶ 29-30. In a
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`gate first process, the gate is formed early in the process, and it then acts as a mask
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`for the source and drain implants. Id. After implanting the source and drain, the
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`wafer must be annealed to repair damage done during implantation, and activate
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`the implanted source/drain dopants to establish the desired dopant profile. The
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`main problem with a gate-first approach is that the high temperatures required for
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`this annealing step can cause undesired changes in the gate stack. Id.
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`Gate-last is an approach to solving that problem. In gate-last, a sacrificial
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`gate (aka “dummy gate”) serves as the mask for the source and drain implants. Id.
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`at ¶ 31. After the annealing process, the sacrificial gate is removed and a new gate
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`stack is formed. Id. In other words, the real gate is built last, after the source and
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`drain have been formed.
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`As discussed below, the ’675 patent and the Hsu reference (U.S. Patent No.
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`8,536,660) (Ex. 1105) both disclose a process in which the bottommost layer of the
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`NMOS and PMOS gates is formed before the source/drain annealing process, and
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`the remaining layers are formed after removal of a dummy gate and after the
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`source/drain annealing process. Id. at ¶ 32. Because all but one layer of the gates
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`are formed using a gate-last approach, the approach disclosed in both the ’675
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`patent and the Hsu reference is generally considered a gate-last process. Id.
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`B.
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`The ’675 Patent Disclosure
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`In the gate-last process of the ’675 patent, gate insulating layer 18, buffer
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`gate electrode 201, and dummy gate electrode 22 are formed on substrate 10. See
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`’675 patent at 7:1-5, Fig. 19 (annotated); Lee Decl. at ¶ 33.
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`The layers are patterned by photolithography to form dummy gate stack 24.
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`1 The second embodiment disclosed in the ’675 specification refers to layer 20 as
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`the “buffer gate electrode,” which corresponds to the “metal buffer gate electrode
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`layer” in claim 1 and the “first metal gate electrode layer” in claim 6.
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`Lee Decl. at ¶ 34. Dummy gate stack 24 includes gate insulating layer 18, buffer
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`gate electrode 20, and dummy gate electrode 22. Id.
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`Spacers 28 are formed on sidewalls of the dummy gate stack 24. ’675 patent
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`at 7:47-48, Fig. 23 (annotated); see Lee Decl. at ¶ 35.
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`Source and drain regions 30 are subsequently formed using the dummy gate
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`electrodes and spacers as an implantation mask. ’675 patent at 7:55-8:11, Fig. 25
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`(annotated); see Lee Decl. at ¶ 36.
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`Mold insulating layer 32 is formed and dummy gate electrode 22 is
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`removed, thus forming trench 35. ’675 patent at 8:17-27, Fig. 27 (annotated); Lee
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`Decl. at ¶ 37.
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`First metal layer 36 is then blanket deposited on inner sidewalls of spacers
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`28 and on an upper surface of buffer gate electrode 20. ’675 patent at 8:38-51,
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`Fig. 28 (annotated); Lee Decl. at ¶ 38.
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`Dummy fill layer 38 is formed in trench 35 and first metal layer 36 is
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`removed from mold insulating layer 32. ’675 patent at 8:52-64. A portion of the
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`second metal gate electrode layer 36 in trench 35 is also removed. Id. at 8:64-67,
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`Fig. 31 (annotated); see Lee Decl. at ¶ 39.
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`Next, dummy fill layer 38 is removed and second metal layer 42 is
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`deposited. ’675 patent at 9:9-20, Fig. 33 (annotated). Second metal layer 42 “may
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`comprise at least one of aluminum, tungsten and titanium.” Id. at 9:22-24. Second
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`metal layer 42 is removed from mold insulating layer 32 and planarized. Id. at
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`9:31-33, Fig. 34 (annotated); see Lee Decl. at ¶ 40.
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`Finally, dummy gate electrode 22 is then removed, and third metal layer 44
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`is deposited to fill the trench. ’675 patent at 9:47-49, 59-61. Third metal layer 44
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`“may comprise at least one of aluminum, tungsten, titanium, and tantalum.” Id. at
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`9:61-63. Third metal layer 44 is then removed from mold insulating layer 32 and
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`planarized. Id. at 10:1-4, Fig. 37 (annotated); see Lee Decl. at ¶ 41.
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`V. OVERVIEW OF THE PRIOR ART
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`For the Board’s ease of reviewing the prior art references, the declarant, Dr.
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`Lee, has provided a glossary mapping terms in the ’675 patent to corresponding
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`terms used by the Hsu reference discussed herein. See Lee Decl. at ¶ 52-68.
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`A. Hsu’s March 12, 2008 Priority Date
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`U.S. Patent No. 8,536,660 (“Hsu”) is entitled to a prior art date of March 12,
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`2008 (the filing date of the ’660 application) under 35 U.S.C. § 102(e) with respect
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`to subject matter having written description support in the ’660 application. See,
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`e.g., In re Giacomini, 612 F.3d 1380, 1383 (Fed. Cir. 2010). As shown in section
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`VIII below, the relevant disclosures of the ’660 patent are fully supported by the
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`’660 application, and thus predate the Earliest Potential Filing Date of the ’675
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`patent.
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`B.
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`Forming the Gate Electrodes in Hsu
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`In the gate-last process of Hsu, two high-k dielectric layers 24 and 26 are
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`formed on interfacial layer 22. Hsu at 5:16-27, Fig. 1 (annotated); see Lee Decl. ¶
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`43.
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`As shown in below, metal layer 32, polysilicon layer 34, and mask layer 36
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`are then formed over the gate insulating layers. Hsu at 5:47-48, Fig. 2 (annotated);
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`see Lee Decl. at ¶ 44.
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`The deposited layers are then patterned in sequence, forming dummy gate
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`stack 138 in the NMOS region that includes high-k dielectric layers 124 and 126,
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`metal layer 132, polysilicon layer 134, and mask layer 136. Hsu at 6:10-18, Fig. 3
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`(annotated). This patterning step also forms gate stack 238 in the PMOS region
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`that includes gate insulating layer 224, metal layer 232, polysilicon layer 234, and
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`mask layer 236. Id.; see Lee Decl. at ¶ 45.
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`Spacers 143 and 243 are formed on sidewalls of gate stacks 138 and 238.
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`Hsu at 6:19-23, Fig. 4 (annotated); see Lee Decl. at ¶ 46.
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`Source and drain regions are subsequently formed using the gate stacks and
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`spacers as an implantation mask. See Hsu at 6:19-23; Lee Decl. at ¶ 47. Inter-
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`layer dielectric (ILD) 54 is then formed and polysilicon layer 234 (and an upper
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`portion of metal layer 232) is removed. Hsu at 6:32-41, Fig. 6 (annotated); see Lee
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`Decl. at ¶ 48.
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`Polysilicon layer 134 is subsequently removed. Hsu at 7:9-12, Fig. 7
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`(annotated). Although Fig. 7 shows removal of only an upper portion of
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`polysilicon layer 134, Hsu describes removing the entirety of dummy gate
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`electrode 134. Id. (“In the preferred embodiment, polysilicon layer 134 is fully
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`removed”); Lee Decl. at ¶ 49.
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`A second metal layer 60 and third metal layer 62 are then deposited. Hsu
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`discloses that second metal layer 60 is formed of “tantalum or titanium containing
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`materials such as TaC, TaN, TiN, TaAlN, TaSiN, and combinations thereof.” Hsu
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`at 7:24-31. Hsu further discloses that the third metal layer 62 may include three
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`sublayers: the bottom layer (621) may be formed of “tungsten-containing materials
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`such as tungsten and tungsten nitride, ruthenium-containing materials such as
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`rutheninm and ruthenium oxynitride, molybdenum-containing materials such as
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`molybdenum and molybdenum nitride, and combinations thereof,” the middle
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`layer (622) may be formed of “TiN, TaN, Ti, Ta, and the like,” and the top layer
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`(623) may be formed of “aluminum, tungsten, and the like.” Id. at 7:44-54, Fig. 9
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`(annotated and excerpted); see Lee Decl. at ¶ 50.
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`Metal layers 62 and 60 are planarized using CMP, creating composite metal
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`gate electrodes between the sidewalls of spacers 143 and 243. Hsu at 7:57-63, Fig.
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`10 (annotated); see Lee Decl. at ¶ 51.
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`C.
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`’675 Patent Prosecution History
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`In the prosecution history of the ’675 patent, the Patent Office did not
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`discuss or cite Hsu. Thus, the Examiner likely did not consider this reference. In
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`the Reasons for Allowance, the examiner merely recited the limitations of the
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`independent claims and stated “these limitations in combination with the other
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`limitations as set forth in the claims are neither taught nor suggested in the prior
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`art.” For the dependent claims, the examiner only stated that they depend from the
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`independent claims and are allowable for at least that reason. As discussed below,
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`Hsu discloses this combination of limitations in the independent claims and
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`dependent claims.
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`VI. CLAIM CONSTRUCTION
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`While no claim terms are proposed for construction, all claim terms in this
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`section have been accorded their broadest reasonable interpretation as understood
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`by a person of ordinary skill and are consistent with the specification and
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`prosecution history of the ’675 patent. See Lee Decl. at ¶ 71-75. Furthermore, the
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`district court’s construction of certain terms in the ’675 patent does not affect the
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`positions set forth in this Petition. See Memorandum Opinion, Samsung
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`Electronics Co., Ltd. et al. v. NVIDIA Corp. et al., No. 3:14-cv-00757-REP (E.D.
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`Va. July 30, 2015), Dkt. No. 221 (Ex. 1107) (“Claim Construction Op.”).
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`The district court construed “[d]epositing a second metal gate electrode layer
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`onto inner sidewalls of the spacers and onto an upper surface of the patterned first
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`metal gate electrode layer,” which appears in claim 6, to have its plain and
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`ordinary meaning. Id. at 6-9. The district court further explained that “in order to
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`comply with the claim's plain language, the second metal gate electrode layer can
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`only consist of one layer.” Id. at 8. Thus, the broadest reasonable construction is
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`no narrower than the district court’s construction, which limits the second metal
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`gate electrode layer to one layer. See Lee Decl. at ¶ 72.
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`The district court construed “[d]epositing a third metal gate electrode layer
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`onto the second metal gate electrode layer,” which appears in claim 6, to mean
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`“depositing a third metal gate electrode layer comprised of one or more metal
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`sublayers onto the second metal gate electrode layer.” Claim Construction Op. at
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`9-12. The broadest reasonable construction is no narrower than the district court’s
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`construction. See Lee Decl. at ¶ 73.
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`The district court construed “a gate insulating layer” to be “a gate
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`comprising one or more insulating sublayers.” Claim Construction Op. at 14-15.
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`The broadest reasonable construction is no narrower than the district court’s
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`construction. See Lee Decl. at ¶ 74. Because the claims are invalid under the
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`district court’s constructions, they are invalid under the broadest reasonable
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`interpretation of the claims as well. Id. at ¶ 75.
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`Petitioner reserves all rights to propose constructions in other proceedings
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`where the standards may differ.
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`VII. LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME
`
`For purposes of this review, a person of ordinary skill is a person with an
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`undergraduate degree in electrical engineering (or equivalent subject) with either:
`
`(1)
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`three
`
`to
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`four years of post-graduate experience designing
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`semiconductor devices and fabrication processes;
`
`(2)
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`or a master’s degree in electrical engineering (or equivalent subject)
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`together with one to two years of post-graduate experience in
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`designing semiconductor devices and fabrication processes.
`
`Lee Decl. at ¶ 20. A person of ordinary skill also would have been familiar with
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`the gate-last (or gate replacement) technique of forming metal gate electrodes. Id.
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`This description is approximate, and a higher level of education or skill might
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`make up for less experience, and vice-versa. Id.
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`VIII. DIFFERENCES BETWEEN HSU AND U.S. PATENT NO.
`2009/0065809 (“YAMAKAWA”)
`On June 1, 2015, petitioner filed a petition requesting institution of inter
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`partes review of the ’675 patent based on Yamakawa as the primary prior art
`
`references. See IPR2015-01318. At the time the previous petition was filed,
`
`neither Petitioner nor its expert, Dr. Jack Lee had knowledge of Hsu. See Lee
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`Decl. at ¶ 76. Furthermore, at the time the previous petition was filed, the district
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`court had not yet issue the claim construction order. See generally Claim
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`Construction Op. In connection with the district court litigation, petitioner
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`disclosed Hsu to Samsung after petitioner became aware of it (after IPR2015-
`
`01318 petition was filed). As explained by Dr. Lee, Hsu makes disclosures
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`regarding the portion of third metal gate electrode layer of the PMOS transistor
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`(layer 262 of Hsu) and the upper metal gate electrode (layers 160 and 162 of Hsu)
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`that may be more relevant to the invalidity of the ’675 patent. See Lee Decl. at ¶
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`77.
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`IX. PRECISE REASONS FOR THE RELIEF REQUESTED
`
`A. Ground 1: The Challenged Claims Are Anticipated By
`U.S. Patent No. 8,536,660 (“Hsu”)
`
`1.
`
`Claim 1
`
`a. 1[pre] A method of forming an insulated-gate transistor,
`comprising:
`
`To the extent the preamble is limiting, Hsu discloses a method of forming an
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`insulated-gate transistor. Lee Decl. at ¶¶ 80-81; Hsu at 2:47-50 (“a semiconductor
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`structure includes a first [metal-oxide-semiconductor] device including a first
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`gate….”); 1:16-19 (“This invention relates generally to semiconductor devices, and
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`more particularly to structures of metal-oxide semiconductor (MOS) devices and
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`manufacturing methods for forming
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`the same.”); 1:23-24 (“Metal-oxide-
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`semiconductor (MOS) devices are basic building elements in integrated circuits.”);
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`4:62-64
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`(“A method
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`for
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`forming hybrid complementary metal-oxide-
`
`semiconductor (CMOS) devices with dual metal gates is provided.”). The method
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`includes the steps discussed below. See Lee Decl. at ¶ 81.
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`Second Petition for Inter Partes Review of USP 8,252,675
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`b. 1[a] forming a gate insulating layer on a substrate;
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`Hsu discloses forming a gate insulating layer (high-k dielectric layer 24) on
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`a substrate (semiconductor substrate 20), as shown in annotated Fig. 1:
`
`
`See id. at ¶ 82-83. Hsu provides that a “first high-k dielectric layer 24 is formed on
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`interfacial layer 22.” Id. at 5:16-17. Hsu discloses that “the first high-k dielectric
`
`layer 24 … may include a metal oxide [or] a silicate of Hf, Al, Zr, combinations
`
`thereof, and multi-layers thereof.”2 Id. at 5:17-20. A hafnium oxide (HfO2) gate
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`2 Hsu contains a minor typographical error because it omits the word “or” between
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`“metal oxide” and “a silicate.” A person of ordinary skill in the art would
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`nevertheless understand that Hsu discloses using a metal oxide or a silicate of Hf,
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`Al, Zr. See Lee Decl. at ¶ 84, fn. 2. This is confirmed by the application that led
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`to Hsu which discloses that “the first high-k dielectric layer 24 … may include a
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`metal oxide or a silicate of Hf, Al, Zr….” Ex. 1106, U.S. Patent Application No.
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`12/047,113 at [0022]. In addition, I have been informed that under the law, the
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`application that led to Hsu, U.S. Patent Application No. 12/047,113, was open to
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`dielectric is electrically insulating. The high-k dielectric layer 24 is a “gate
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`insulating layer” under the district court’s construction. See Ex. 1107, Claim
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`Construction Op. at 14-15; see also Lee Decl. at ¶ 84.
`
`c. 1[b] forming a metal buffer gate electrode layer on the
`gate insulating layer;
`
`Hsu discloses forming a metal buffer gate electrode layer (metal layer 32) on
`
`the gate insulating layer (high-k dielectric layer 24) as shown in annotated Fig. 2:
`
`
`See also Lee Decl. at ¶ 85-86. Hsu teaches that after high-k dielectric layer 24 is
`
`formed, “metal layer 32, polysilicon layer 34, and hard mask layer 36 are
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`sequentially formed.” Hsu at 5:47-48. Hsu further discloses that metal layer 232
`
`(which is metal layer 32 after patterning) “protect[s] the underlying high-k
`
`
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`inspection by the public by September 17, 2009, the date the Hsu application was
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`published as U.S. Publication No. 2009/0230479.
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`dielectric layer 224.” Id. at 6:64-67; see also id. at 7:14-16. Thus, Hsu discloses
`
`this limitation. Lee Decl. at ¶ 85-86.
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`d. 1[c] forming a dummy gate electrode layer on the buffer
`gate electrode layer, said dummy gate electrode layer
`and said buffer gate electrode layer comprising different
`materials;
`
`Hsu discloses forming a dummy gate electrode layer (polysilicon layer 34)
`
`on the buffer gate electrode layer (metal layer 32) as shown in annotated Fig. 2:
`
`
`See also Lee Decl. at ¶ 87-88. Hsu explains that “metal layer 32, polysilicon layer
`
`34, and hard mask layer 36 are sequentially formed.” Id. at 5:47-48. The dummy
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`gate electrode layer (polysilicon layer 34) includes polysilicon, and the buffer gate
`
`electrode layer (metal layer 32) includes, for example, titanium nitride (TiN) or
`
`tantalum nitride (TaN). Id. at 5:55-58. The dummy gate electrode layer
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`(polysilicon layer 34) and the buffer gate electrode layer (metal layer 32) thus
`
`comprise different materials. Lee Decl. at ¶ 88.
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`e. 1[d] patterning the dummy gate electrode layer and the
`buffer gate electrode layer in sequence to define a buffer
`gate electrode on the gate insulating layer and a dummy
`gate electrode on the buffer gate electrode;
`
`Hsu discloses patterning the dummy gate electrode layer (polysilicon layer
`
`34) and the buffer gate electrode layer (metal layer 32) in sequence to define a
`
`buffer gate electrode (metal layer 232) on the gate insulating layer (high-k
`
`dielectric layer 224) and a dummy gate electrode (polysilicon layer 234) on the
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`buffer gate electrode (metal layer 232), as shown in annotated Fig. 3:
`
`
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`See Lee Decl. at ¶ 89; see also Hsu at 6:10-43.
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`Hsu discloses “patterning of the previously formed stacked layers, forming
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`gate stack 138 in NMOS region 100, and gate stack 238 in PMOS region 200.” Id.
`
`at 6:10-13. “Gate stack 238 includes high-k dielectric 224, metal layer 232,
`
`polysilicon layer 234, and mask layer 236.” Id. at 6:14-16. The patterning
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`disclosed by Hsu is sequential because etching removes the dummy gate electrode
`
`layer (polysilicon layer 34) first, before removing the layer below it, the buffer gate
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`electrode layer (metal layer 32), in sequence. See Lee Decl. at ¶¶ 90-91.
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`f. 1[e] forming electrically insulating spacers on sidewalls
`of the dummy gate electrode and on sidewalls of the
`buffer gate electrode;
`
`Hsu discloses forming electrically insulating spacers (spacers 243) on
`
`sidewalls of the dummy gate electrode (polysilicon layer 234) and on sidewalls of
`
`the buffer gate electrode layer (metal layer 232) as shown in annotated Fig. 4:
`
`
`Lee Decl. at ¶ 92; see also Hsu at 6:19-23 (Figure 4 “illustrates the formation …
`
`spacers 143 and 243….”). Given that the spacers are in contact with both the gate
`
`electrode and the source and drain regions, if they were not electrically insulating,
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`the gate electrode would be short circuited wit