CONFIDENTIAL
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF VIRGINIA
`RICHMOND DIVISION
`
`
`SAMSUNG ELECTRONICS CO., LTD., and
`SAMSUNG ELECTRONICS AMERICA,
`INC.,
`
`CIVIL ACTION NO. 3:14-cv-00757-REP
`
`.
`
`
`
`
`
`
`
`Plaintiffs,
`
`
`v.
`
`NVIDIA CORPORATION, VELOCITY
`MICRO, INC. D/B/A VELOCITY MICRO,
`AND VELOCITY HOLDINGS, LLC
`
`Defendants.
`
`REBUTTAL EXPERT REPORT OF DR. RICHARD B. FAIR REGARDING
`U.S. PATENT NO. 8,252,675
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`
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`NVIDIA Corp.
`Exhibit 1110
`Page 001
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`CONFIDENTIAL
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`titanium, or tantalum. Thus I conclude that the ’108 Korean Application discloses each element
`
`of the Claim 13 of the ’675 Patent.
`
`56.
`
`Paragraph 47 (SAMS-NVD-19827; SAMS-NVD-0121866) refers to the layer 20
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`(the first metal gate electrode layer) formed of titanium nitride or tantalum nitride. Thus I
`
`conclude that the ’108 Korean Application discloses each element of the Claim 14 of the ’675
`
`Patent.
`
`57.
`
`In light of all of the evidence cited above, it is my opinion that ’108 Korean
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`Application (and, of course, the English language translation of the ’108 Korean Application)
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`discloses all of the elements of all of the asserted claims of the ’675 Patent. Dr. Lee does not
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`challenge that the ’108 Korean Application (or its translation) fully discloses the elements of the
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`asserted claims of the ’675 Patent in his opening expert report. I also understand that NVIDIA
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`does not contend that any element of the asserted claims of the ’675 Patent is missing from the
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`disclosure of the ’108 Korean Application. Should Dr. Lee or NVIDIA challenge the disclosure
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`of the ’108 Korean Application, I will further provide rebuttal opinions to support my conclusion
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`that the ’108 Korean Application adequately supports every element of every claim of the ’675
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`Patent.
`
`V.
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`CLAIMS 12, 13, AND 14 OF THE '675 PATENT ARE NOT INVALID IN VIEW
`OF THE ALLEGED PRIOR ART
`
`A.
`
`58.
`
`U.S. Patent No. 8,536,660 (the “’660 patent” or “Hsu”)
`
`The ‘660 patent discloses structures and methods of making dual metal gate MOS
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`transistors in a gate last process. The ’660 patent addresses the complexity and number of steps
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`involved in the prior art processes and focuses on how to reduce the complexity of forming metal
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`gates for PMOS and NMOS transistors with high-k gate dielectrics over prior art methods. Hsu
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`2: 39-43.
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`16
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`NVIDIA Corp.
`Exhibit 1110
`Page 002
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`59.
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`In the ’660 patent, a semiconductor substrate having a first MOS device region
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`and a second MOS device region is provided. Blanket-deposited first and second high-k
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`dielectric layers are formed over the semiconductor substrate. The second high-k dielectric layer
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`is then removed from the second MOS device region. A blanket forming first metal layer is
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`formed over the first and the exposed second high-k dielectric layers, wherein the first metal
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`layer has a thickness great enough for dominating a work-function of a respective MOS device.
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`60.
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`Dummy gates are then fabricated. A blanket forming polysilicon layer is then
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`deposited over the first metal layer. Masking and patterning the first and the second high-k
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`dielectric layers, the first metal layer, and the polysilicon layer follows to form a first gate stack
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`in the first MOS device region, and a second gate stack in the second MOS device region.
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`Following the application of a blanket insulating layer, gate spacers on sidewalls of the first and
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`the second gate stacks are formed by etching. Next, an inter-layer dielectric (ILD) is deposited
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`over the semiconductor substrate and the first and the second gate stacks. The ILD is planarized
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`to expose a top surface of the polysilicon layer. The second gate stack is etched until at least an
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`upper portion of the first metal layer is removed to form a first opening. The first gate stack is
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`then etched until at least an upper portion of the polysilicon layer is removed to form a second
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`opening, wherein the first metal layer in the first gate stack is not etched. A blanket-forming
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`second metal layer extending into the first and the second openings is deposited. A third metal
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`layer deposition follows to fill the remaining portions of the first and the second openings. A
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`planarization step follows to remove portions of the second and the third metal layers over the
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`ILD. Col. 3: 48-col. 4: 13.
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`B.
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`61.
`
`Hsu Does Not Anticipate The Asserted Claims Of The ’675 Patent
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`I am informed by counsel that NVIDIA did not disclose the ’660 Patent to Hsu,
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`or the U.S. Patent Application Publication 2009/02340479 in their initial invalidity contention.
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`17
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`NVIDIA Corp.
`Exhibit 1110
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`Therefore I understand that the Hsu reference was not timely disclosed and Dr. Lee may not be
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`allowed to opine on the alleged invalidity of the ’675 Patent based on Hsu. Nonetheless, I
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`present my opinion regarding Hsu in the following paragraphs in the event Dr, Lee’s opinion on
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`Hsu is permitted..
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`1.
`
`Claim 6
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`62.
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`Dr. Lee asserts that Hsu (the ’660 patent) discloses every limitation of, and
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`therefore anticipates, Claim 6. Lee ’675 Report at ¶ 78. I disagree for the reasons set forth
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`below.
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`a.
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`6(h) “depositing a second metal gate electrode layer onto inner
`sidewalls of the spacers and onto an upper surface of the
`patterned first metal gate electrode layer;”
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`63.
`
`The ’660 patent does not disclose this element. Dr. Lee asserts that “Hsu
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`discloses depositing a second metal gate electrode layer (metal layer 60) onto inner sidewalls of
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`the spacers (spacers 243) and onto an upper surface of the patterned first metal gate electrode
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`layer (metal layer 232), as shown in Fig. 8.” Lee ’675 Report at ¶ 106. I disagree with this
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`assertion.
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`64.
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`According to the ‘660 patent, the PMOS region is etched while the NMOS region
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`is covered with photoresist: “In the preferred embodiment, metal layer 232 is fully removed
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`without damaging high-k dielectric layer 224.” Hsu 6: 63-64. Thus, in this preferred
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`embodiment the first metal gate electrode layer of the PMOS transistor, 232, is removed. As a
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`result, a second metal gate electrode layer 60 could not be deposited onto an upper surface of the
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`patterned first metal gate electrode layer 232, since it was previously removed.
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`65.
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`The ’660 patent also states: “If, however, the selectivity of the etching is not high
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`enough, a thin metal layer 232 may be left un-etched to protect the underlying high-k dielectric
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`layer 224. In this case, the thickness of the remaining metal layer 232 is preferably less than 2
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`18
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`NVIDIA Corp.
`Exhibit 1110
`Page 004
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`nm, for example, between about 0.5 nm and about 2 nm, so that it will not substantially affect the
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`work function of PMOS device 202.” Hsu 6: 64-67 to 7: 4.
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`66.
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`Thus, claim element 6[h] of the ’675 Patent recites an essential limitation that
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`requires depositing a second metal layer onto an upper surface of the patterned first metal gate
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`electrode layer. In contrast, the ’660 Patent does not require the patterned first metal gate
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`electrode layer, and teaches that the metal layer 232 is removed by etching. Even where the ’660
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`patent discloses an embodiment where the metal layer 232 remains, it teaches etching of layer
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`232 so that only “a thin metal layer 232 may be left un-etched.” Thus, the remaining metal layer
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`232 would no longer retain the upper surface of the patterned first metal gate electrode layer.
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`67.
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`The upper surface of the patterned first metal gate electrode layer, 232, is shown
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`in annotated Fig. 5 below. After dummy gate electrode 234 is etched and metal layer 232 is
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`partially etched or removed, the resulting structure is shown in annotated Fig. 6 below.
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`19
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`NVIDIA Corp.
`Exhibit 1110
`Page 005
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`CONFIDENTIAL
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`
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`68.
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`Depositing a second metal gate electrode layer, 60, onto the remaining metal layer
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`232 is shown in annotated Fig. 8 below. The upper surface of the patterned first metal gate
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`electrode layer no longer is present as required by claim element 6(h).
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`69.
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`I conclude that for at least the above reasons, the ’660 patent does not disclose or
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`render this element obvious.
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`20
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`NVIDIA Corp.
`Exhibit 1110
`Page 006
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`CONFIDENTIAL
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`2.
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`Claim 10
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`70.
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`Dr. Lee asserts that Hsu (the ‘660 patent) discloses every limitation of, and
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`therefore anticipates, Claim 10. Lee ’675 Report at ¶ 117. I disagree for the reasons set forth
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`
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`below.
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`a.
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`10. The method of claim 6, wherein said patterning the dummy
`gate electrode layer and the first metal gate electrode layer
`comprises patterning the dummy gate electrode layer and the
`first metal gate electrode layer in sequence to define a second
`dummy gate electrode on the patterned first metal gate
`electrode layer; and wherein said forming electrically
`insulating spacers on sidewalls of the dummy gate electrode is
`followed by replacing the second dummy gate electrode with
`an upper metal gate electrode of an NMOS transistor.
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`71.
`
`Because Claim 10 depends on Claim 6, and because Hsu does not disclose or
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`render obvious all elements of Claim 6 as explained above, Hsu does not disclose or render
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`Claim 10 obvious.
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`72.
`
`The ’660 patent does not disclose the method of Claim 6, nor does it disclose
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`replacing the second dummy gate electrode with an upper metal gate electrode of an NMOS
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`transistor. Dr. Lee asserts that “Hsu discloses that after an upper portion (or the entirety) of
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`21
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`NVIDIA Corp.
`Exhibit 1110
`Page 007
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`polysilicon layer 134 is removed, metal layer is deposited. . . . Hsu thus discloses replacing the
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`second dummy gate electrode (polysilicon layer 134) with an upper metal gate electrode (metal
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`layers 160 and 162) of an NMOS transistor.” Lee ’675 Report at ¶ 124. I disagree with this
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`assertion.
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`73.
`
`The ordinary meaning of “replacing” in Claim 10 is “taking the place of as a
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`substitute.” According to the specification of the ‘675 patent, when the dummy gate electrode is
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`replaced with a metal gate electrode, the following steps are performed: “The dummy filler layer
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`is then removed from between the inner sidewalls of the spacers to expose the first metal layer.
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`A second metal layer is then deposited onto a portion of the first metal layer extending between
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`the inner sidewalls of the spacers, to thereby define a metal gate electrode containing a
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`composite of the first and second metal layers.” Summary of the Invention, ’675 Patent at 1: 51-
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`57.
`
`74.
`
`In the preferred embodiment in Hsu, polysilicon layer 134 is fully removed
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`without damaging the underlying metal layer 132. However, Figure 11 of Hsu shows, a portion
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`of the polysilicon layer remains in the NMOS gate stack. Thus, Hsu teaches the option of leaving
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`a portion of the polysilicon layer 134 rather than the requirement that it be replaced with the
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`upper metal gate electrode layer of an NMOS transistor. Thus, Dr. Lee would rewrite the
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`language of Claim 10 in the following way to read the ‘660 patent onto Claim 10: wherein said
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`forming electrically insulating spacers on sidewalls of the dummy gate electrode is followed by
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`replacing the upper portion (or the entirety) of the second dummy gate electrode with an upper
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`metal gate electrode of an NMOS transistor, which would make modified Claim 10 indefinite.
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`By contrast, the language of Claim 10 of the ‘675 patent requires complete removal of the
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`second dummy gate electrode layer to affect replacement.
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`22
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`NVIDIA Corp.
`Exhibit 1110
`Page 008
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`75.
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`I conclude that for at least the above reasons, in my opinion the '660 patent does
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`not disclose or render Claim 10 obvious.
`
`3.
`
`Claim 12
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`76.
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`Dr. Lee asserts that Hsu (the ’660 Patent) discloses every limitation of, and
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`therefore anticipates, Claim 12. Lee ’675 Report at ¶ 133. I disagree for the reasons set forth
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`below.
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`a.
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`12. The method of claim 11, wherein the portion of third metal
`gate electrode layer of the PMOS transistor and the upper
`metal gate electrode of the NMOS transistor comprise different
`metals.
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`77.
`
`Because Claim 11 depends on Claims 6 and 10, and because Hsu does not
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`disclose or render obvious all elements of Claims 6 and 10, Hsu does not disclose or render
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`Claim 12 obvious.
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`78.
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`The ’660 Patent does not disclose this element. According to Dr. Lee, Hsu
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`discloses that the third metal gate electrode layer (metal layer 262) of the PMOS transistor and
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`the upper metal gate electrode (metal layers 160 and 162) of the NMOS transistor comprise
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`different metals. However, Dr. Lee’s opinion is not supported by the specification of the ’660
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`Patent.
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`79.
`
`The layers in the transistors disclosed in the ’660 patent that correspond to the
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`portion of third metal gate electrode layer (metal layer 262) of the PMOS transistor and the upper
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`metal gate electrode (metal layers 160, 162) of the NMOS transistor are shown in annotated
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`Fig.10 below. Hsu explains that, after metal layer 62 is deposited in the form of sublayers 621,
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`622 and 623, (see Fig. 9), a patterning step that etches metal layer 62 forms metal layers 162 and
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`262 in the gate stacks of the NMOS and PMOS regions respectively. Thus, metal layers 162 and
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`262 are made from the same metal layer 62. Hsu at 7:57-61. The metal layers 162 and 262 may
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`23
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`NVIDIA Corp.
`Exhibit 1110
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`include,
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`for example,
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`tungsten-containing materials,
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`ruthenium-containing materials,
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`molybdenum-containing materials and combinations thereof. Hsu at 7:34-40. Alternately, metal
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`layers 162 and 262 may be made from titanium-containing materials, like Ti and TiN, tantalum-
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`containing materials, like Ta and TaN and the like, and aluminum, tungsten and the like. Hsu 7:
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`44-56.
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`80. Metal layer 160 of the upper metal gate electrode of the NMOS transistor is also
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`formed from exemplary materials that include tantalum or titanium-containing materials and
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`combinations thereof. Hsu 7: 24-31. Thus, the combination of metal layers 160 and 162 (the
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`upper metal gate electrode of the NMOS) and metal layer 262 (the portion of third metal gate
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`electrode layer of the PMOS transistor) comprise the same metals. A summary chart accounting
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`for the disclosed metals in the two structures is shown in the table below.
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`24
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`Exhibit 1110
`Page 010
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`Table. Comparison of metals
`Portion of third metal gate
`Upper metal gate electrode
`electrode layer of the
`of the NMOS transistor – metal
`PMOS transistor –metal
`layers 160,162
`layer 262
`
`tungsten-containing materials
`ruthenium-containing materials,
`molybdenum-containing materials
`titanium-containing materials
`tantalum-containing materials
`aluminum
`
`tungsten-containing materials
`ruthenium-containing materials,
`molybdenum-containing materials
`titanium-containing materials
`tantalum-containing materials
`aluminum
`
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`There is also no suggestion that the metal layers 160 and 162 (the upper metal
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`81.
`
`gate electrode of the NMOS) and metal layer 262 (the portion of third metal gate electrode layer
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`of the PMOS transistor) should be different. In fact, Hsu’s selection of exemplary materials
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`shows that they would be the same materials. For example, Hsu states that layer 60 (160 in
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`NMOS stack) may comprise a mid-gap material such as certain tantalum-containing materials or
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`titanium-containing materials and combinations thereof. Hsu at 7: 24-31. Hsu also states that
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`layer 62 (162 in NMOS stack and 262 in the PMOS stack) should have a preferred work function
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`higher than about 5.0eV and optionally comprise certain tantalum-containing materials and
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`titanium-containing materials and the like. Hsu at 7: 44-50.
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`82.
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`I conclude that for at least the above reasons, in my opinion the ’660 patent does
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`not disclose or render Claim 12 obvious.
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`4.
`
`Claim 13
`
`83.
`
`Dr. Lee asserts that Hsu (the ‘660 patent) discloses every limitation of, and
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`therefore anticipates, Claim 13. Lee ’675 Report at ¶ 137. I disagree for the reasons set forth
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`below.
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`25
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`Exhibit 1110
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`CONFIDENTIAL
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`a.
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`13. The method of claim 12, wherein the portion of third metal
`gate electrode layer of the PMOS transistor comprises titanium
`nitride and the upper metal gate electrode of the NMOS
`transistor comprises aluminum.
`
`84.
`
`Because Claim 12 depends on Claims 6, 10 and 11, and because Hsu does not
`
`disclose or render obvious all elements of Claims 6, 10 and 11, Hsu does not disclose or render
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`Claim 13 obvious.
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`85.
`
`Claim 13 further requires the presence of specific elements (TiN for the third
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`metal gate electrode layer of PMOS, and Al for the upper metal gate electrode layer of NMOS)
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`chosen from various available materials. As I discussed above, Hsu generically discloses a large
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`class of materials, such as tungsten-containing materials, ruthenium-containing materials,
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`molybdenum-containing materials, titanium-containing materials, tantalum-containing materials,
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`or aluminum. Thus, a person of ordinary skill in the art would not have understood this
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`disclosure as requiring the use of titanium nitride and aluminum in the PMOS and NMOS,
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`respectively.
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`86.
`
`I conclude that for at least the above reasons, in my opinion the ’660 Patent does
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`not disclose or render Claim 13 obvious.
`
`5.
`
`Claim 14
`
`87.
`
`Dr. Lee asserts that Hsu (the ’660 Patent) discloses every limitation of, and
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`therefore anticipates, Claim 14. Lee ’675 Report at ¶ 141. I disagree for reasons I discussed
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`with regards to Claims 6, 10, and 12 above. Because Claim 14 depends on Claims 6, 10, and 12,
`
`and because Hsu does not disclose or render obvious all elements of Claims 6, 10, and 12, Hsu
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`does not disclose or render Claim 14 obvious.
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`26
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`NVIDIA Corp.
`Exhibit 1110
`Page 012
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`CONFIDENTIAL
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`56
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`NVIDIA Corp.
`Exhibit 1110
`Page 013