111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US008536660B2
`
`c12) United States Patent
`Hsu et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,536,660 B2
`Sep.17,2013
`
`(54) HYBRID PROCESS FOR FORMING METAL
`GATES OF MOS DEVICES
`
`(75)
`
`Inventors: Peng-Fu Hsu, Hsin-Chu (TW);
`Yong-Tian Hou, Singapore (SG); Ssu-Yi
`Li, Jhubei (TW); Kuo-Tai Huang,
`Hsin-Chu (TW); Mong Song Liang,
`Hsin-Chu (TW)
`
`(73) Assignee: Taiwan Semiconductor Manufacturing
`Company, Ltd., Hsin-Chu (TW)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 844 days.
`
`(21) Appl. No.: 12/047,113
`
`(22) Filed:
`
`Mar. 12, 2008
`
`(65)
`
`Prior Publication Data
`
`US 2009/0230479 Al
`
`Sep. 17, 2009
`
`(51)
`
`(2006.01)
`
`Int. Cl.
`HOJL21102
`(52) U.S. Cl.
`USPC ................................... 257/410; 257/E29.137
`(58) Field of Classification Search
`USPC ................. 257/369, 371, 374, 410, 411, 412,
`257/E27.064, E27.067, E27.108, E29.128,
`257/E29.137
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`4,974,056 A *
`1111990 Brodsky et a!. ............... 25717 51
`6,089,695 A
`7/2000 Takagi eta!.
`6,323,115 Bl
`1112001 Tanabe et a!.
`6,373,111 Bl *
`4/2002 Zheng et al ................... 257/407
`6,696,345 B2
`2/2004 Chau et a!.
`
`6,727,129 Bl
`6,794,234 B2
`6,831,310 Bl
`6,855,641 B2
`6,936,508 B2
`6,998,686 B2
`7,157,378 B2
`7,160,767 B2
`
`4/2004 Nakajima
`9/2004 Polishchuk eta!.
`12/2004 Mathew eta!.
`2/2005 Ryu et a!.
`8/2005 Visokay eta!.
`2/2006 Chau et a!.
`112007 Brask eta!.
`112007 Brask eta!.
`(Continued)
`
`CN
`CN
`CN
`
`FOREIGN PATENT DOCUMENTS
`1667808 A
`9/2005
`1274018 c
`9/2006
`1992273 A
`7/2007
`
`OTHER PUBLICATIONS
`
`Chudzik, M., et al., "High-Performance High-k/Metal Gates for
`45nm CMOS and Beyond with Gate-First Processing," Symposium
`on VLSI Technology Digest of Technical Papers, 2007, pp. 194-195.
`
`(Continued)
`
`Primary Examiner- Vongsavanh Sengdara
`(74) Attorney, Agent, or Firm- Slater & Matsil, L.L.P.
`
`ABSTRACT
`(57)
`A semiconductor structure includes a first MOS device
`including a first gate, and a second MOS device including a
`second gate. The first gate includes a first high-k dielectric
`over a semiconductor substrate; a second high-k dielectric
`over the first high-k dielectric; a first metal layer over the
`second high-k dielectric, wherein the first metal layer domi(cid:173)
`nates a work-function of the first MOS device; and a second
`metal layer over the first metal layer. The second gate includes
`a third high-k dielectric over the semiconductor substrate,
`wherein the first and the third high-k dielectrics are formed of
`same materials, and have substantially a same thickness; a
`third metal layer over the third high-k dielectric, wherein the
`third metal layer and the second metal layer are formed of
`same materials, and have substantially a same thickness; and
`a fourth metal layer over the third metal layer.
`
`17 Claims, 11 Drawing Sheets
`
`102
`
`\
`
`202
`
`/
`
`143
`
`160
`
`143 134
`
`243
`
`260
`
`243 232
`
`144
`
`144
`
`100
`
`200
`
`NVIDIA Corp.
`Exhibit 1105
`Page 001
`
`

`
`US 8,536,660 B2
`Page 2
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`7,253,053 B2 * 8/2007
`Eppich eta!. ................. 438/244
`Doris et al.
`7,432,567 B2
`10/2008
`2002/0079548 A1 * 6/2002
`Hu ................................ 257/412
`3/2003
`2003/0057499 A1
`Yamamoto
`2003/0128384 A1
`7/2003
`Nelson eta!.
`2004/0066535 A1
`4/2004
`Oyumi
`2004/0245578 A1
`Park eta!.
`12/2004
`2004/0256679 A1
`12/2004
`Hu
`2005/0082605 A1
`Akasaka
`4/2005
`Lander eta!.
`2005/0112875 A1
`5/2005
`2005/0157138 A1
`7/2005
`Silverbrook eta!.
`2005/0260806 A1
`1112005
`Chang et al.
`2006/0121678 A1
`Brask eta!.
`6/2006
`2006/0166424 A1
`7/2006
`Schaeffer, III et a!.
`2007/0018244 A1 *
`112007
`Hung et al.
`................... 257/337
`2007/0075351 A1
`4/2007
`Schulz eta!.
`2007/0105317 A1
`5/2007
`Nakajima
`2007/0138559 A1
`6/2007
`Bohr
`2007/0272975 A1 * 1112007
`Schaeffer et al. ............. 257/327
`
`2008/0099851 A1 *
`2008/0173947 A1
`2008/0188044 A1
`2009/0039433 A1
`2009/0152636 A1 *
`OTHER PUBLICATIONS
`
`5/2008 Hsu eta!. ...................... 257/369
`7/2008 Hou et a!.
`8/2008 Hsu eta!.
`212009 Yang eta!.
`6/2009 Chudzik eta!. ............... 257/369
`
`Tateshita, Y., et a!., "High-Performance and Low-Power CMOS
`Device Technologies Featuring Metal/High-k Gate Stacks with
`Uniaxial Strained Silicon Channels on (100) and (110) Substrates,"
`IEEE International Electron Devices Meeting, 2006,4 pages, IEEE.
`Hou, Y. T., et al., "High Performance Tantalum Carbide Metal Gate
`Stacks for nMOSFET Application," IEEE International Electron
`Devices Meeting, IEDM Technical Digest, Dec. 2005, pp. 31-34,
`Washington, D.C., United States.
`Hsu, P. F., et al., "Advanced Dual Metal Gate MOSFETs with High-k
`Dielectric for CMOS Application," Symposium in VLSI Technology,
`Digest of Technical Papers, 2006, pp. 11-12, IEEE, Honolulu,
`Hawaii, United States.
`* cited by examiner
`
`NVIDIA Corp.
`Exhibit 1105
`Page 002
`
`

`
`U.S. Patent
`
`Sep.17,2013
`
`Sheet 1 of 11
`
`US 8,536,660 B2
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`NVIDIA Corp.
`Exhibit 1105
`Page 003
`
`

`
`U.S. Patent
`
`Sep.17,2013
`
`Sheet 2 of 11
`
`US 8,536,660 B2
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`Exhibit 1105
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`NVIDIA Corp.
`Exhibit 1105
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`NVIDIA Corp.
`Exhibit 1105
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`Exhibit 1105
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`Exhibit 1105
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`NVIDIA Corp.
`Exhibit 1105
`Page 012
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`NVIDIA Corp.
`Exhibit 1105
`Page 013
`
`

`
`US 8,536,660 B2
`
`1
`HYBRID PROCESS FOR FORMING METAL
`GATES OF MOS DEVICES
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This application relates to the following connnonly
`assigned U.S. patent application: application Ser. No. 11/552,
`704, filed Oct. 25, 2006, entitled "Semiconductor Devices
`with Dual-Metal Gate Structures and Fabrication Methods
`Thereof," which patent application is incorporated herein by
`reference.
`
`TECHNICAL FIELD
`
`This invention relates generally to semiconductor devices,
`and more particularly to structures of metal-oxide-semicon(cid:173)
`ductor (MOS) devices and manufacturing methods for form(cid:173)
`ing the same.
`
`BACKGROUND
`
`2
`Existing processes for forming dual-metal complementary
`MOS (CMOS) devices include two main categories, gate-first
`approach and gate-last approach. Both approaches have
`advantageous and disadvantageous features. In a typical gate(cid:173)
`first approach, two metal layers having different work func(cid:173)
`tions are separately formed in PMOS and NMOS regions.
`The metal layers are then patterned to form gate electrodes.
`Other components of MOS devices, such as spacers, lightly
`doped source/ drain (LD D) regions, source/ drain regions, sili-
`10 cides, and contact etch stop layers are then formed. This
`process is relatively simple, and the resulting contact etch
`stop layers are continuous, so that they can effectively apply
`stresses. However, since the metal gates are formed before the
`formation and the activation ofLDD regions and source/drain
`15 regions, they suffer from high thermal budgets, and the work
`functions of PMOS devices may shift. In addition, if compos(cid:173)
`ite metal layers are used, the oxygen in the composite metal
`layer may be released under the thermal budgets, and cause
`interfacial layer re-growth. Further, patterning metal layers
`20 by etching is relatively difficult, particularly for metals used
`for the PMOS devices.
`Gate-last approach, on the other hand, typically includes
`the steps of forming dunnny gates for both PMOS and NMOS
`devices. LDD regions, gate spacers, source/drain regions, and
`25 contact etch stop layers are then formed. The dunnny gates of
`PMOS and NMOS devices are then removed, and metals with
`different work functions are then filled into the openings for
`PMOS and NMOS devices. In the gate-last approach, metal
`gates of PMOS devices and NMOS devices both take the
`30 advantage oflow thermal budgets since they are formed after
`the formation and activation ofLDD regions and source/drain
`regions. However, the process is complex. In addition, in the
`cases wherein the formation of high-k dielectrics also uses
`gate-last approach, the quality of the high-k dielectrics was
`35 often not satisfactory. Besides, forming high-k dielectrics on
`sidewalls of the openings will adversely increase the fringing
`capacitance between the gate and nearby features, such as
`source/drain regions and contacts.
`Accordingly, what is needed in the art is a semiconductor
`40 structure and respective formation methods that may incor(cid:173)
`porate dual metal gates thereof to take advantage of the ben(cid:173)
`efits associated with band-edge work functions while at the
`same time overcoming the deficiencies of the prior art.
`
`Metal-oxide-semiconductor (MOS) devices are basic
`building elements in integrated circuits. A conventional MOS
`device typically has a gate electrode comprising polysilicon
`doped with p-type or n-type impurities, using doping opera(cid:173)
`tions such as ion implantation or thermal diffusion. It is pre(cid:173)
`ferred to adjust the work function of the gate electrode to the
`band-edge of the silicon; that is: for an NMOS device, adjust(cid:173)
`ing the work function close to the conduction band, and for a
`PMOS device, adjusting the work function close to the
`valence band. Adjusting the work function of the polysilicon
`gate electrode can be achieved by selecting appropriate impu(cid:173)
`rities.
`MOS devices with polysilicon gate electrodes exhibit car(cid:173)
`rier depletion effect, which is also referred to as a poly deple(cid:173)
`tion effect. The poly depletion effect occurs when applied
`electrical fields sweep away carriers from regions close to
`gate dielectrics, forming depletion layers. In ann-doped poly(cid:173)
`silicon layer, the depletion layer includes ionized non-mobile
`donor sites, whereas in a p-doped polysilicon layer, the deple(cid:173)
`tion layer includes ionized non-mobile acceptor sites. The
`depletion effect results in an increase in the effective gate
`dielectric thickness, making it more difficult for an inversion
`layer to be created at the surface of the semiconductor.
`The use of thin gate dielectrics tends to make the carrier
`depletion effect worse. With thin gate dielectrics, the deple(cid:173)
`tion layer in the polysilicon gate becomes more significant in
`thickness when compared to the thickness of the thin gate
`dielectrics, and thus device performance degradation wars- 50
`ens. As a result, the carrier depletion effect in the gate elec(cid:173)
`trodes limits device scalability by imposing a lower bound on
`how much the effective gate dielectric thickness can be
`reduced.
`The poly depletion effect was previously solved by form- 55
`ing metal gate electrodes or metal silicide gate electrodes,
`wherein the metallic gates used in NMOS devices and PMOS
`devices also preferably have band-edge work functions. Cur(cid:173)
`rently, materials suitable for forming gate electrodes of
`NMOS devices, such as TaC, have been found. However, for 60
`PMOS devices, even though metallic materials having band(cid:173)
`edge work functions have been found, these materials have
`poor thermal stability. When exposed to the high tempera(cid:173)
`tures in the front-end-of-line processes, the work functions of
`these metallic materials shift, for example, toward the mid- 65
`gap level. The performance of the resulting PMOS devices is
`thus adversely affected.
`
`45
`
`SUMMARY OF THE INVENTION
`
`In accordance with one aspect of the present invention, a
`semiconductor structure includes a first MOS device includ(cid:173)
`ing a first gate, and a second MOS device including a second
`gate. The first gate includes a first high-k dielectric over a
`semiconductor substrate; a second high-k dielectric over the
`first high-k dielectric; a first metal layer over the second
`high-k dielectric, wherein the first metal layer dominates a
`work-function of the first MOS device; and a second metal
`layer over the first metal layer. The second gate includes a
`third high-k dielectric over the semiconductor substrate,
`wherein the first and the third high-k dielectrics are formed of
`same materials, and have substantially a same thickness; a
`third metal layer over the third high-k dielectric, wherein the
`third metal layer and the first metal layer are formed of same
`materials, and have substantially a same thickness; and a
`fourth metal layer over the third metal layer.
`In accordance with another aspect of the present invention,
`a semiconductor structure includes a first MOS device includ(cid:173)
`ing a first gate, and a second MOS device including a second
`gate. The first gate includes a first high-k dielectric over a
`semiconductor substrate; a second high-k dielectric over the
`
`NVIDIA Corp.
`Exhibit 1105
`Page 014
`
`

`
`US 8,536,660 B2
`
`3
`first high-k dielectric, wherein the first and the second high-k
`dielectrics are formed of different materials; a first metal layer
`over the secondhigh-k dielectric, wherein the first metal layer
`has a thickness great enough for dominating a work-function
`of the first MOS device; a second metal layer over the first
`metal layer, wherein the first and the second metal layers are
`formed of different materials; and a third metal layer over the
`second metal layer, wherein the third metal layer has a work
`function close to a valence band of silicon. The second gate
`includes the first high-k dielectric over the semiconductor
`substrate; the second metal layer over the first high-k dielec(cid:173)
`tric, wherein the second metal layer in the second gate has a
`bottom surface lower than a bottom surface of the second
`metal layer in the first gate; and the third metal layer over the
`second metal layer.
`In accordance with yet another aspect of the present inven(cid:173)
`tion, a semiconductor structure includes a semiconductor
`substrate; a first high-k dielectric over the semiconductor
`substrate; a second high-k dielectric over the first high-k
`dielectric, wherein the first and the second high-k dielectrics
`include different materials; a first metal layer over the second
`high-k dielectric, wherein the first metal layer has a mid-gap
`work function; a polysilicon layer over the first metal layer;
`and a second metal layer over the first metal layer.
`In accordance with yet another aspect of the present inven(cid:173)
`tion, a method for forming a semiconductor structure includes
`providing a semiconductor substrate; forming a first MOS
`device including a first gate, and forming a second MOS
`device including a second gate. The step of forming the first
`gate includes forming a first high-k dielectric over the semi(cid:173)
`conductor substrate; forming a second high-k dielectric over
`the first high-k dielectric, wherein the first and the second
`high-k dielectrics are formed of different materials; forming a
`firstmetallayeroverthe secondhigh-kdielectric, wherein the
`first metal layer has a thickness great enough for dominating 35
`a work-function of the first MOS device; and forming a sec(cid:173)
`ond metal layer over the first metal layer, wherein the first and
`the second metal layers are formed of different materials. The
`step of forming the second gate includes forming a third
`high-k dielectric over the semiconductor substrate, wherein
`the first and the third high-k dielectrics include same materi(cid:173)
`als, and have substantially a same thickness; forming a third
`metal layer over the third high-k dielectric, wherein the third
`metal layer and the second metal layer include same materi(cid:173)
`als, and have substantially a same thickness; and forming a 45
`fourth metal layer over the third metal layer, wherein the third
`and the fourth metal layers are formed of different materials.
`In accordance with yet another aspect of the present inven(cid:173)
`tion, a method for forming a semiconductor structure includes
`providing a semiconductor substrate having a first MOS 50
`device region and a secondMOS device region; blanket form(cid:173)
`ing a first high-k dielectric layer over the semiconductor
`substrate; blanket forming a second high-k dielectric layer
`over the first high-k dielectric layer, wherein the first and the
`second high-k dielectric layers are formed of different mate- 55
`rials; removing the second high-k dielectric layer from the
`second MOS device region; blanket forming a first metal
`layer over the first and the second high-k dielectric layers,
`wherein the first metal layer has a thickness great enough for
`dominating a work-function of a respective MOS device; 60
`forming a polysilicon layer over the first metal layer; pattern(cid:173)
`ing the first and the second high-k dielectric layers, the first
`metal layer, and the polysilicon layer to form a first gate stack
`in the first MOS device region, and a second gate stack in the
`second MOS device region; forming gate spacers on side- 65
`walls of the first and the second gate stacks; forming an
`inter-layer dielectric (ILD) over the semiconductor substrate
`
`4
`and the first and the second gate stacks; performing a pla(cid:173)
`narization and exposing a top surface of the polysilicon layer;
`etching the second gate stack until at least an upper portion of
`the first metal layer is removed to form a first opening; etching
`the first gate stack until at least an upper portion of the poly(cid:173)
`silicon layer is removed to form a second opening, wherein
`the first metal layer in the first gate stack is not etched; blanket
`forming a second metal layer extending into the first and the
`second openings; forming a third metal layer to fill remaining
`10 portions of the first and the second openings; and performing
`a planarization to remove portions of the second and the third
`metal layers over the ILD.
`In accordance with yet another aspect of the present inven-
`15 tion, a method for forming a semiconductor structure includes
`providing a semiconductor substrate; forming a first high-k
`dielectric layer over the semiconductor substrate; forming a
`second high-k dielectric layer over the first high-k dielectric
`layer, wherein the first and the secondhigh-k dielectric layers
`20 are formed of different materials; forming a first metal layer
`over the second high-k dielectric layer, wherein the first metal
`layer has a thickness great enough for dominating a work(cid:173)
`function of a respective MOS device; forming a polysilicon
`layer over the first metal layer; patterning the first and the
`25 second high-k dielectric layers, the first metal layer, and the
`polysilicon layer to form a gate stack; forming a gate spacer
`on a sidewall of the gate stack; forming an inter-layer dielec(cid:173)
`tric (ILD) over the semiconductor substrate and gate stack;
`performing a planarization and exposing a top surface of the
`30 polysilicon layer; etching the gate stack to form an opening,
`until at least an upper portion of the polysilicon layer is
`removed, and wherein the first metal layer is not removed by
`the etching; forming a second metal layer lining the opening;
`and forming a third metal layer to fill the opening.
`The hybrid method of the present invention provides band-
`edge work functions for both PMOS and NMOS devices. The
`stresses applied to the channel regions of PMOS devices are
`increased due to the adoption of the gate-last approach in
`PMOS devices. In addition, the threshold voltages of both
`40 PMOS and NMOS devices are both reduced.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`For a more complete understanding of the present inven(cid:173)
`tion, and the advantages thereof, reference is now made to the
`following descriptions taken in conjunction with the accom(cid:173)
`panying drawings, in which:
`FIGS. 1 through 11 are cross-sectional views of interme(cid:173)
`diate stages in the manufacturing of an embodiment of the
`present invention.
`
`DETAILED DESCRIPTION OF ILLUSTRATIVE
`EMBODIMENTS
`
`The making and using of the presently preferred embodi(cid:173)
`ments are discussed in detail below. It should be appreciated,
`however, that the present invention provides many applicable
`inventive concepts that can be embodied in a wide variety of
`specific contexts. The specific embodiments discussed are
`merely illustrative of specific ways to make and use the inven(cid:173)
`tion, and do not limit the scope of the invention.
`A method for forming hybrid complementary metal-oxide(cid:173)
`semiconductor (CMOS) devices with dual metal gates is pro(cid:173)
`vided. The method combines gate-first and gate-last
`approaches to achieve better effects. The intermediate stages
`of manufacturing a preferred embodiment of the present
`invention are illustrated. Throughout the various views and
`
`NVIDIA Corp.
`Exhibit 1105
`Page 015
`
`

`
`US 8,536,660 B2
`
`5
`illustrative embodiments of the present invention, like refer(cid:173)
`ence numbers are used to designate like elements.
`Referring to FIG.1, substrate 20 is provided, which may be
`formed of commonly used semiconductor materials and
`structures such as bulk silicon, silicon-on-insulator (SOl), 5
`silicon-germanium (SiGe), embedded SiGe (eSiGe), germa(cid:173)
`nium, and the like. Shallow trench isolation regions 18 are
`formed in substrate 20, and may be used to define NMOS
`device region 100 and PMOS device region 200. Interfacial
`layer 22 is formed on substrate 20. Interfacial layer 22 helps 10
`buffer substrate 20 and the overlying high-k dielectric layer,
`and may be formed of chemical oxide, thermal oxide, silicon
`oxynitride, and the like. In an exemplary embodiment, the
`nitrogen atomic ratio of interfacial layer 22 is less than about
`15 atomic percent.
`A first high-k dielectric layer 24 is formed on interfacial
`layer 22. Preferably, the first high-k dielectric layer 24 has a k
`value of greater than about 7 .0, and may include a metal oxide
`a silicate ofHf, AI, Zr, combinations thereof, and multi -layers
`thereof. The thickness of high-k dielectric layer 24 may be 20
`between about 1 urn and about 10 nm. One skilled in the art
`will realize, however, that the dimensions recited throughout
`the specification are merely examples, and will change with
`the down-scaling of the formation technology.
`A second high-k dielectric layer 26, preferably having a k 25
`value greater than about 1 0.0, is formed on the first dielectric
`layer 24. The second high-k dielectric layer 26 may include
`metals such as La, Mg, Ba, Ti, Pb, Zr, and may be in the form
`of metal oxides, metal alloyed oxides, and combinations
`thereof. Exemplary materials include MgOx, BaTixOy, Ba 30
`SrxTiyOz, PbTixOy, PbZrxTiyOz, and thelike.Althoughhigh-k
`dielectric layer 26 is referred to as a dielectric layer, it may
`actually be formed of pure metals such as La and/or Mg.
`Preferably, the secondhigh-k dielectric layer 26 has the func(cid:173)
`tion of depriving substrate 20 from the oxygen that may be 35
`released by the first high-k dielectric layer 24 and/or interfa(cid:173)
`ciallayer 22. During the subsequent annealing such as source/
`drain activations, layer 26 may be turned into metal oxides.
`The thickness ofhigh-k dielectric layer 26 may be between
`about 0.3 nm and about 3 nm. The formation methods of 40
`dielectric layers 24 and 26 include molecular-beam deposi(cid:173)
`tion (MBD), atomic layer deposition (ALD), physical vapor
`deposition (PVD), and the like. Next, photo resist 28 is
`formed and patterned, exposing PMOS region 200. The
`exposed portion ofhigh-k dielectric layer 26 is then removed,
`leaving high-k dielectric layer 26 in NMOS region 100.
`Referring to FIG. 2, thick metal layer 32, polysilicon layer
`34, and hard mask layer 36 are sequentially formed. Through(cid:173)
`out the description, the term "metallayer(s)" refers to con(cid:173)
`ductive metal-containing layer(s). Preferably, metal layer 32
`has a mid-gap work function (in the middle of the conduction
`and valence bands of silicon), for example, between about 4.1
`eV and about 5.2 eV. Alternatively, metal layer 32 may have
`a conduction band-edge work function (close to the conduc(cid:173)
`tion band of silicon, which is about 4.1 eV). The exemplary
`materials include tantalum or titanium containing materials
`such as TaC, TaN, TiN, TaAIN, TaSiN, and combinations
`thereof. These metal-containing materials may be in the form
`of metal carbides, metal nitrides, or conductive metal oxides.
`Metal layer 32 determines the work function of the resulting
`NMOS device, and hence has a thickness greater than the
`thickness required for dominating the work function of the
`respective NMOS device. In an exemplary embodiment, the
`thickness of metal layer 32 is greater than about 3 nm. The
`formation methods of metal layer 32 include ALD, PVD,
`metal-organic chemical vapor deposition (MOCVD), and the
`like.
`
`6
`Polysilicon layer 34 may have a thickness ofbetween about
`30 nm and about 100 nm. The functions of polysilicon layer
`34 include preventing contamination of metal layer 32, and
`maintaining the height of the gate stack to a level convenient
`for the gate formation processes. Polysilicon layer 34 is pref(cid:173)
`erably pre-doped with ann-type impurity. Mask layer 36 is
`preferably formed of dielectric materials, such as silicon
`oxide, silicon nitride, silicon oxynitride, silicon carbide, and
`the like.
`FIG. 3 illustrates the patterning of the previously formed
`stacked layers, forming gate stack 138 in NMOS region 100,
`and gate stack 238 in PMOS region 200. Gate stack 138
`includes high-k dielectrics 124 and 126, metal layer 132,
`polysilicon layer 134, and mask layer 136. Gate stack 238
`15 includes high-k dielectric 224, metal layer 232, polysilicon
`layer 234, and mask layer 236. Interfacial layer 22 is also
`patterned as layers 122 and 222. For a clear view, interfacial
`layers 122 and 222 are not shown in subsequent drawings.
`FIG. 4 illustrates the formation of source/drain extension
`regions 142 and 242, spacers 143 and 243, source/drain
`regions 144 and 244, and source/drain silicides 146 and 246,
`which are the components of NMOS device 102 and PMOS
`device 202, respectively. Contact etch stop layer (CESL) 140,
`preferably having a tensile stress, is formed over NMOS
`device 102. Contact etch stop layer (CESL) 240, preferably
`having a compressive stress, is formed over PMOS device
`202. PMOS device 202 may further include stressors 248
`(preferably formed of silicon germanium) overlapping por(cid:173)
`tions of source/drain regions 244. The formation methods and
`materials of the above-discussed regions are known in the art,
`and thus are not repeated herein.
`In FIG. 5, inter-layer dielectric (ILD) 54 is blanket formed
`to a height higher than the top surface of hard masks 136 and
`236. In an embodiment, ILD 54 may include carbon-contain(cid:173)
`ing oxides. A chemical mechanical polish (CMP) is then
`performed to remove top portions ofiLD 54, and hard masks
`136 and 236, hence exposing polysilicon layers 134 and 234.
`FIG. 6 illustrates the selective removal of the dummy gate
`including polysilicon layer 234 and at least an upper portion
`of metal layer 232, which is preformed by applying and
`patterning photo resist 156 to cover NMOS region 100. The
`removal of polysilicon layer 234 may be performed using
`either dry or wet etching. In the case dry etching is used, the
`process gas may include CF4 , CHF3 , NF 3 , SF 6 , Br2 , HBr, Cl2 ,
`45 or combinations thereof. Diluting gases such as N 2 , 0 2 , or Ar
`may optionally be used. In the case wet etching is used, the
`chemicals may include NH4 0H:H20 2 :H20 (APM), NH20H,
`KOH, HN03 :NH4 F:H2 0, ethylenediamine:C6Hi0H)2 :
`H20, HF:NH4 F:H20, HF:LN03 :H20, KCI:H20, KOH:H20:
`50 Br2/I 2 , KOH, HF:HN03 :Hac:I2 :triton, HF:HN03 :Hac,
`Iodine Etch:Hac, Nal, NaOH, HF:HN03 , HF:HN03 :H2 0,
`and/or the like. The removal of metal layer 232 may also be
`performed using either dry or wet etching. In the case dry
`etching is used, a chlorine containing gas mixture such as
`55 BCI3 , Cl2 , or a combined gas ofN2 and CHF 3 , may be used as
`the etchant gas. In the case wet etching is used, the wet
`etching chemicals may include H2S04 :H20 2 : H20(SPM),
`H20:HF:HN03 , H 20:HF:H20 2 , RCA-1, x % Br2 :ethyl
`acetate (hot), x% I2 :MeOH (hot), HF:CuS04 NH40H:H20 2 ,
`60 HF:HN03 :H20, COOHCOOH:H20, HF:H20 2 :LN03 ,
`HF:H20, HF:HCI:H20, HCI, % KOH, % NaOH, H2S04 ,
`CCI3 COOC2H5 , HCOOH, H3 P04 , HF, or the like.
`In the preferred embodiment, metal layer 232 is fully
`removed without damaging high-k dielectric layer 224. If,
`65 however, the selectivity of the etching is not high enough, a
`thin metal layer 232 may be left un-etched to protect the
`underlying high-k dielectric layer 224. In this case, the thick-
`
`NV